1

The Memory

2

Types of Memory

• Random Access Memory(RAM)• Read Only Memory(ROM)• Programmable ROM(PROM)• Erasable Programmable ROM(EPROM)• Electrically Erasable ROM(EEPROM)

3

But we’ll have a look on

1. Random Access Memory(RAM)2. Read Only Memory(ROM)

4

What is RAM ?

In your Knowledge

5

Ok…! Thank You Friends :)

Now let’s have a look, at a video!

6

BASIC CONCEPTS OF MEMORY SYSTEM

• The maximum size of the Main Memory (MM) that can be used in any computer is determined by its addressing scheme.

16-bit address = memory location.• If a machine generates 32-bit addresses, it can access

upto memory locations. • This number represents the size of address space of

the computer

7

Some Basic Concepts • Smallest addressable unit of information is a

memory word, called as Word-Addressable.• Most modern computers are Byte Addressable

eg. 32-bit comp, each memory word contains 4 bytes. A possible word-address

0 1 2 34 5 6 78 9 10 11… … … …

048…

Word Address Byte Address

8

CPU-Main Memory Connection

• The MM unit can be viewed as a “Black Box”.• Data transfer between CPU and MM take

place by MAR and MDR. • If MAR is ‘k’ bits long and MDR is ‘n’ bits long

2^k addressable location &

each location will be ‘n’ bits wide• While the word length is = ‘n’ bits.

Connection Of MM to CPU

• During “Memory Cycle”, ‘n’ bits of data transferred between MM & CPU .

• This transfer takes place over processor bus, which has ‘k’ address line and ‘n’ data lines and control lines like Read, Write.

Up to 2 k addressableMDR

MAR

k-bitaddress bus

n-bitdata bus

Control lines( , MFC, etc.)

Processor Memory

locations

Word length = n bits

WR /

10

Virtual MemorySeveral techniques to increase the effective size and

speed of the memory: Cache memory (to increase the effective speed). Virtual memory (to increase the effective size).

11

Virtual MemorySeveral techniques to increase the effective size and

speed of the memory: Cache memory (to increase the effective speed). Virtual memory (to increase the effective size).

12

Virtual Memory

• This’s an another important concept related to MR

• VM increase the apparent size of the MM.• Only the active portion are mapped into MM, remaining are mapped into Bulk storage which is Magnetic device. VM

13

Internal Organization of Memory Chip

• Each memory cell can hold one bit of information.• Memory cells are organized in the form of an array. • One row is one memory word. • All cells of a row are connected to a common line,

known as the “word line”. • Word line is connected to the address decoder.• Sense/write circuits are connected to the data

input/output lines of the memory chip.

Internal organization of memory chips (Contd.,)

FF

circuitSense / Write

Addressdecoder

FF

CS

cellsMemory

circuitSense / Write Sense / Write

circuit

Data input /output lines:

A0

A1

A2

A3

W0

W1

W15

7 1 0

WR /

7 1 0

b7 b1 b0

•••

•••

•••

•••

•••

•••

••••••

•••

15

Read/Write Memory(RAM)–Types of RAM:

1. Static RAM (SRAM)

2. Dynamic RAM (DRAM)

16

Static Memory• Bits stored as on/off switches• No charges to leak• No refreshing needed when powered• More complex construction• Larger per bit• More expensive• Does not need refresh circuits• Faster• Cache• Digital

– Uses flip-flops

SRAM Cell

• Two transistor inverters are cross connected to implement a basic flip-flop.• The cell is connected to one word line and two bits lines by transistors T1 and T2• When word line is at ground level, the transistors are turned off and the latch

retains its state• Read operation: In order to read state of SRAM cell, the word line is activated to

close switches T1 and T2. Sense/Write circuits at the bottom monitor the state of b and b’

YX

Word line

Bit lines

b

T 2T1

b¢

Static RAM Operation• Transistor arrangement gives stable logic state• State 1– b high, b’ low– T1 off, T2 on

• State 0– b’ high, b low– T2 off, T1 on

• Address line transistors T1 T2 is switch• Write – apply value to B & compliment to B• Read – value is on line B

CMOS Cell (Ciruit)

CMOS Cell • Transistor pairs (T3,T5) and (T4,T6) form the invertors to the Latch• As in the SRAM itself the read and write operation occurs, i.e.,

when T3 n T6 are on, T4 n T5 are off. The vice-versa is also true.• Voltage supply in the older cells was 5V or 3.3 in new low-voltage

cells• If power interrupt occurs, cell’s content is lost• Major advantage is their very low power consumption• Access time is just a few nano seconds• They are found in Commercially available chips

• It is used when speed is of critical concern

Dynamic RAM• Bits stored as charge in capacitors• Charges leak• Need refreshing even when powered• Simpler construction• Smaller per bit• Less expensive• Need refresh circuits• Slower• Used in main memory• Essentially analogue

– Level of charge determines value

Dynamic RAM Structure

DRAM Operation• Address line active when bit read or written

– Transistor switch closed (current flows)• Write

– Voltage to bit line• High for 1 low for 0

– Then signal address line• Transfers charge to capacitor

• Read– Address line selected

• transistor turns on– Charge from capacitor fed via bit line to sense amplifier

• Compares with reference value to determine 0 or 1– Capacitor charge must be restored

1M X 1 DRAM Structure

• Each row can store 512 bytes. 12 bits to select a row, and 9 bits to select a group in a row. Total of 21 bits.

• First apply the row address, RAS signal latches the row address. Then apply the column address, CAS signal latches the address.

• Timing of the memory unit is controlled by a specialized unit which generates RAS and CAS.

• This is asynchronous DRAM

Column

CSSense / Writecircuits

cell arraylatchaddress

Row

Column

latch

decoderRow

decoderaddress

4096 512 8´( )´

R /W

A20 9- A8 0-¤

D0D7

RAS

CAS

( 1M X 1 DRAM chip )

SRAM v DRAM• Both volatile

– Power needed to preserve data• Static

– Faster– Doesn’t need refresh– Cache– Consumes more power

• Dynamic cell – Simpler to build, smaller– More dense– Less expensive– Needs refresh– Larger memory units

Read Only Memory (ROM)

• Permanent storage– Nonvolatile

• Microprogramming (see later)• Library subroutines• Systems programs (BIOS)• Function tables

27

Types of ROM• Programmable ROM(PROM)• Erasable Programmable ROM(EPROM)• Electrically Erasable ROM(EEPROM)• Flash Memory• BIOS

Types of ROM• Written during manufacture

– Very expensive for small runs• Programmable (once)

– PROM– Needs special equipment to program

• Read “mostly”– Erasable Programmable (EPROM)

• Erased by UV– Electrically Erasable (EEPROM)

• Takes much longer to write than read– Flash memory

• Erase whole memory electrically, no byte-level erase• But much faster write

ROM

• A logic value of 0 is stored when the cell in the transistor is connected to ground at the point P, otherwise, 1 is stored

• The Bit line is Connected through a resistor to the power supply• To read the state of the cell, the word line is activated• Thus the transistor switch is closed & the voltage on the bit line drops to near zero,

if there is a connection b/w the transistor and ground• If there is no connection to the ground, bit line remains at the high voltage, 1• A sense circuit at the end of the bit line generates the proper output value• Data are written into ROM when it is manufactured

Read-Only Memories (Contd.,)Read-Only Memory:

Data are written into a ROM when it is manufactured.

Programmable Read-Only Memory (PROM): Allow the data to be loaded by a user. Process of inserting the data is irreversible. Storing information specific to a user in a ROM is expensive.

Providing programming capability to a user may be better. Erasable Programmable Read-Only Memory

(EPROM): Stored data to be erased and new data to be loaded. Flexibility, useful during the development phase of digital systems. Erasable, reprogrammable ROM. Erasure requires exposing the ROM to UV light.

Read-Only Memories (Contd.,) Electrically Erasable Programmable Read-Only Memory (EEPROM):

To erase the contents of EPROMs, they have to be exposed to ultraviolet light.

Physically removed from the circuit. EEPROMs the contents can be stored and erased electrically.

Flash memory: Has similar approach to EEPROM. Read the contents of a single cell, but write the contents of an entire

block of cells. Flash devices have greater density.▪ Higher capacity and low storage cost per bit.

Power consumption of flash memory is very low, making it attractive for use in equipment that is battery-driven.

Single flash chips are not sufficiently large, so larger memory modules are implemented using flash cards and flash drives.

FLASH MEMORY• Approach is similar to EEPROM • It is based on single transistor controlled by trapped charges• In flash Drives it is possible to read contents of single cell, but it is only

possible to write an entire block of cells• They have greater density, which leads to higher capacity and lower cost

per bit• Lower power consumption, portability and low cost are its advantages• Flash Drives are solid state electronic devices that has no movable parts • They are Insensitive to Vibrations• Disadvantages are their smaller capacity and higher cost per bit• It will als0 deteriorate after it has been written a no. of times

33

Speed, Size, Cost

Speed, Size, and Cost

A big challenge in the design of a computer system is to provide a sufficiently large memory, with a reasonable speed at an affordable cost.

Static RAM: Very fast, but expensive, because a basic SRAM cell has a complex circuit making it impossible

to pack a large number of cells onto a single chip. Dynamic RAM:

Simpler basic cell circuit, hence are much less expensive, but significantly slower than SRAMs. Magnetic disks:

Storage provided by DRAMs is higher than SRAMs, but is still less than what is necessary. Secondary storage such as magnetic disks provide a large amount

of storage, but is much slower than DRAMs.

Memory HierarchyProcessor

Primarycache

Mainmemory

Increasingsize

Increasingspeed

Magnetic disksecondarymemory

Increasingcost per bit

Registers

L1

Secondarycache L2

•Fastest access is to the data held in processor registers. Registers are atthe top of the memory hierarchy.•Relatively small amount of memory thatcan be implemented on the processor chip. This is processor cache. •Two levels of cache. Level 1 (L1) cache is on the processor chip. Level 2 (L2) cache is in between main memory and processor. •Next level is main memory, implementedas SIMMs. Much larger, but much slowerthan cache memory.•Next level is magnetic disks. Huge amountof inexepensive storage. •Speed of memory access is critical, the idea is to bring instructions and data that will be used in the near future as close to the processor as possible.

I’m Done..!Wake Up..!