はじめに ??してください。VHDLによる論理回路設計では、VHDL対応のシミュレータによる検証、VHDL対 応の論理合成ツールを使用することが前提となります。それらは各ツールのマニュアルを参照してく ださい。 論理回路設計に使用する言語 ...

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<ul><li><p> IP (Intellectual Property) (Sys-tem-on-a-Chip)</p><p>IPVSI(Virtual Socket Interface)IPIP1</p><p> IP HDL(Hardware Description Language)RTL(Register TransferLevel)RTLHDL</p><p> IP</p><p>HDL</p><p>VHDLVHDLLRM(Language Reference Manual) VHDLVHDLVHDLVHDL</p><p>VHDL Verilog-HDLVHDLVerilog-HDLVerilog</p><p>VHDL( Verilog-HDL)IP IP</p><p>2002 4 1</p></li><li><p> 2002</p><p>20012001</p><p> 3.3. LSI9 37</p><p>Design CompilerBuild Gates</p><p> 3.4. 3.5.7. 3.5.9.CVS 14</p><p> 12 3</p><p> 3.3, 3.4, 3.5.714 27 59</p><p>RAM</p></li><li><p> RTLVHDLRTLRTL process subprogramif case</p><p> RTL</p><p>A-5 Design CompilerA-6 Build Gates</p><p> 2</p><p> 3</p><p> 1</p></li><li><p>1</p><p>1 ............................................................................................................................ 1-1</p><p>1.1. ................................................................................................................................. 1-21.1.1. ...................................................................................................... 1-21.1.2. ................................................ 1-51.1.3. ............................................................................. 1-91.1.4. constant)(Verilog) .......................................... 1-111.1.5. ................................ 1-141.1.6. (VHDL only) ............................................................... 1-16</p><p>1.2. ............................................................................................................................... 1-181.2.1. ......................................................................................... 1-18</p><p>1.3. ....................................................................................................................... 1-191.3.1. ....................................................................... 1-191.3.2. ......................................................................................... 1-231.3.3. .............................................................................. 1-24</p><p>1.4. ............................................................................................................................... 1-261.4.1. .................................................................... 1-261.4.2. ..................................................... 1-271.4.3. ........................................................................... 1-291.4.4. 2 ................................................................................................. 1-31</p><p>1.5. ........................................................................................................................... 1-331.5.1. .............................................. 1-331.5.2. ..................................................... 1-381.5.3. RAM / ..................................... 1-39</p><p>1.6. ............................................................................................................................... 1-411.6.1. .............................................................................. 1-411.6.2. FF ............................................... 1-441.6.3. ........................................... 1-451.6.4. ..................................................... 1-471.6.5. ........................................................................... 1-491.6.6. 20 ......................................... 1-51</p><p> 2RTL ............................................................................................................... 2-1</p><p>2.1. RTLVHDL .............................................................................................. 2-22.1.1. (VHDL only) .............................................................................................. 2-22.1.2. (VHDL only) ....................................................................................... 2-42.1.3. (VHDL only) .......................................................................................... 2-72.1.4. Verilog.................................................................. 2-92.1.5. when-else 5(VHDL only) .......................................... 2-11</p></li><li><p>2</p><p>2.1.6. ........................................................................................................... 2-122.1.7. (VHDL only) .............................................................................. 2-142.1.8. function procedure (VHDL only) ............................................................ 2-162.1.9. RTL(VHDL only) ........................................................ 2-192.1.10. RTL(VHDL only) ........................................................... 2-20</p><p>2.2. process ........................................................................................ 2-222.2.1. .................................................................................. 2-222.2.2. process ................... 2-242.2.3. process (VHDL only) ........................................................................ 2-26</p><p>2.3. FF ............................................................................................................................. 2-292.3.1. FF ............................................................................ 2-292.3.2. (VHDL only) .......................................... 2-342.3.3. ........................................................................... 2-362.3.4. FF(Verilog) .......................................... 2-372.3.5. FF ........................................................................ 2-382.3.6. ............................................................ 2-39</p><p>2.4. ........................................................................................................................... 2-402.4.1. ......................................................... 2-40</p><p>2.5. .................................................................................................. 2-432.5.1. .................................................................... 2-432.5.2. ......................... 2-47</p><p>2.6. process ..................................................................................... 2-482.6.1. .............................................................................. 2-482.6.2. 1 process .............................. 2-51</p><p>2.7. if ............................................................................................................................... 2-532.7.1. if ............................................................. 2-532.7.2. if .......................................................................... 2-552.7.3. if ...................................................................................... 2-57</p><p>2.8. case .......................................................................................................................... 2-592.8.1. case / ...................................................... 2-592.8.2. if ...................................................... 2-612.8.3. others ................................................................................................... 2-632.8.4. if case (Verilog 2.8.6) ............................ 2-66</p><p>2.9. for ............................................................................................................................. 2-682.9.1. for ................................................................. 2-682.9.2. for ..................................................................... 2-692.9.3. for exit,next (VHDL only) ............................................................ 2-71</p><p>2.10. ...................................................................................................................... 2-722.10.1. ............................................................................................. 2-722.10.2. boolean(VHDL only) .................................................. 2-762.10.3. (VHDL only) ............................................................................................ 2-772.10.4. (VHDL only) ............................................................................................ 2-792.10.5. ............................ 2-822.10.6. process ............................................... 2-842.10.7. .............................................................................. 2-87</p></li><li><p>3</p><p>2.11. ........................................................................................................ 2-882.11.1. .............................................................................. 2-882.11.2. ........................................................................... 2-912.11.3. FF case ............................................................................................. 2-932.11.4. .................................................................................. 2-942.11.5. constant (VHDL only) ................................................... 2-96</p><p>3RTL ........................................................................................................................... 3-1</p><p>3.1. ........................................................................................................... 3-23.1.1. ................................................................................ 3-23.1.2. ...................................................................... 3-33.1.3. ....................................................... 3-53.1.4. RTL ...................................................................................... 3-73.1.5. .................................................... 3-83.1.6. if generate for generate(VHDL only) ........................................................ 3-11</p><p>3.2. ................................................................................................................ 3-123.2.1. (Verilog) .......................... 3-123.2.2. (Verilog) ....................... 3-153.2.3. ..................................................... 3-173.2.4. (Verilog) . 3-193.2.5. ............................ 3-20</p><p>3.3. (DFT) ...................................................................................................... 3-223.3.1. DFT .................................................................. 3-253.3.2. .............................................................................. 3-283.3.3. FF ............................................................................................................ 3-303.3.4. .................................................................................................... 3-323.3.5. DFT .................................................................................... 3-343.3.6. DFT ....................................................................................... 3-403.3.7. ............................................................................................. 3-433.3.8. DFT ................................................................................ 3-453.3.9. ASIC ............................. 3-48</p><p>3.4. .................................................................................................................... 3-533.4.1. ..................................................... 3-533.4.2. ................................................................ 3-563.4.3. ..................................................... 3-58</p><p>3.5. ....................................................................................... 3-593.5.1. ........................................................................... 3-593.5.2. ......................................................................................... 3-623.5.3. .................................................................... 3-633.5.4. .............................................................................. 3-643.5.5. ........................................................................... 3-663.5.6. .................................................................................................... 3-673.5.7. CVS ............................................................................. 3-70</p></li><li><p>4</p><p>3.5.8. CVS checkout commit ............................................... 3-713.5.9. CVS () .......................................................... 3-733.5.10. CVS ................................................................... 3-75</p><p>4 ..................................................................................................................... 4-1</p><p>4.1. .................................................................................................................. 4-24.1.1. ....................................................................................... 4-24.1.2. .................................................................................... 4-34.1.3. ....................................................................................... 4-64.1.4. process (Verilog) .................................... 4-84.1.5. ......................................................................... 4-94.1.6. constant ............................................................................................... 4-124.1.7. ............................................................ 4-134.1.8. (Verilog) ...................... 4-144.1.9. ....................................................................... 4-214.1.10. ..................................................... 4-234.1.11. Verilog............................ 4-254.1.12. (VHDL only) ...................................................................... 4-27</p><p>4.2. ................................................................................................................ 4-294.2.1. ......................................................... 4-294.2.2. ........................................................................... 4-304.2.3. (Verilog) ........................................ 4-33</p><p>4.3. ....................................................................................................................... 4-354.3.1. ............................................................................................. 4-354.3.2. ............................................................................................. 4-374.3.3. ......................................................... 4-434.3.4. .................................................................................. 4-474.3.5. .................................................. 4-494.3.6. ............................................................ 4-504.3.7. ................................................................ 4-544.3.8. ............................................................................................. 4-564.3.9. .............................................. 4-584.3.10. ................................................................ 4-59</p><p>4.4. ....................................................................................... 4-614.4.1. .................................................................... 4-614.4.2. XRTL ............................... 4-644.4.3. .............................................................</p></li></ul>

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