ザイリンクス Xcell Journal 日本語版 93 号

S O L U T I O N S F O R A P R O G R A M M A B L E W O R L D

Time-to-Market

FPGA

Zynq MPSoC Xen

XDC

FPGA

12japan.xilinx.com/xcell

93 2015

L E T T E R F R O M T H E P U B L I S H E R

Mike Santarini

Xcell journal

Xcell Journal 93

2015 12 21

Xilinx, Inc2100 Logic DriveSan Jose, CA 95124-3400

2015 Xilinx, Inc. All Right Reserved.

XILINX Xcell Xilinx

Xilinx, Inc.

Xilinx, Inc.

/

Mike [email protected]+1-408-626-5981

Jacqueline Damian

Scott Blair

Teie, Gelwicks & Associates

[email protected]

[email protected]

141-00321-2-2 4F

Zynq UltraScale+ Hello World 3 Zynq MPSoC XCZU9EG Zynq UltraScale+

MPSoC 28nm 7 20nm UltraScale 16/14nm FinFET UltraScale+ 3

2015 9 30 2 2 Zynq MPSoC TSMC

9 Linux ()

UltraScale+ 1 Zynq UltraScale+ MPSoC Linux

Xcell Journal 90 TSMC 16nm FinFET+ Zynq MPSoC 64 ARM Cortex-A53 32 ARM Cortex-R5 ARM Mali-400MP 16nm FPGA (UltraRAM ) Zynq UltraScale+ MPSoC 28nm Zynq SoC 5

Xcell Publications 28nm Zynq-7000 All Programmable SoC Zynq MPSoC Xcell Software JournalZynq MPSoC

This years best release.

SDx IDE C/C++OpenCL

FPGA SDx All Programmable

Xcell Software Journal

( [email protected] )

Solutions for a

Progammable World

Xcell Publications

VIEWPOINTS

Letter from the Publisher

Zynq UltraScale+ Hello World 2

XCELLENCE BY DESIGN APPLICATION FEATURES

Xcellence in Vision Systems

FPGA 12

Xcellence in Test & Measurement

Zynq SoC 20

Xcellence in Test & Measurement

Artix-7 FPGA USB 24

Xcellence in Industrial

FPGA 28

Cover Story

6

Time-to-Market

28

12 20

THE XILINX XPERIENCE FEATURES

Xplanation: FPGA 101

Zynq MPSoC Xen 34


Vivado IPI Aurora FPGA 42


XDC 50

Tools of Xcellence

56

42

34

50

93

6 Xcell Journal 93 6 Xcell Journal 93

Xilinx Speeds Customer Medical Innovations to Market

Time-to-Market

Mike Santarini Publisher, Xcell Journal, Xilinx, Inc. [email protected]

C O V E R S T O R Y

C O V E R S T O R Y

6 Xcell Journal 93 http://japan.xilinx.com/ 76 Xcell Journal 93

All Programmable IP

All Programmable

30

FPGA ( Zynq-7000

All Programmable SoC

)

()

(CTMRI)

X

FPGA

FPGA

FPGA ( Zynq SoC)

All Programmable

( 1)

Kamran Khan

73 2050 97

65

23% 2050 32%

(31 )

C O V E R S T O R Y

8 Xcell Journal 93

Khan

Khan

2019 2,120

60

Khan

Siemens

General Electric

X

Khan

Time-to-

Market

Khan

1

1

TI Freescale

MotorControl

UnitMC

MotorControl

UnitMC

Processor

ApplicationSpecificFeatures

Single Core ARM

RTOS

PeripheralsAnalytics

HMIMC

Video

Network

Sensors

MemoryLPDDR2

Network

MemoryLPDDR3

TI OMAP orFreescale i.MX6d

Higher Potentialfor Failure

Small FPGA forSensory input

MultipleDevices,

Extra BOM

Older Memory,Slower

Single ChipSolution with

7010

RTOSon isolated core

Higher reliablitywith real-time

analytics

Single chip =lower BOM

Lower power,Faster memory

FPGA

RTOSPeripherals

Dual Core A9

FabricAnalytics

Motor ControlHMI

Video

Zynq SoC

Traditional Clinical Designs Single-Chip Clinical Designs

Sensors

VideoUnit

Video

MotorControl

UnitMC

e Core ARMVideo

1 Zynq SoC

C O V E R S T O R Y

8 Xcell Journal 93 http://japan.xilinx.com/ 9

Khan

Khan

Khan

2

Khan

1

1

/

2

Khan

OEM

Khan

Khan

Khan

PC

Khan

FPGA Zynq SoC

All Programmable

All Programmable FPGA

SoC

Khan

IP

SDSoC

Zynq SoC

Zynq SoC ARM

( 2)

30

10

ASIC ASSP FPGA

C O V E R S T O R Y

10 Xcell Journal 93

ASIC ASSP

Khan 1980

1990

FPGA

FPGA ASIC ASSP

(Zynq SoC

Zynq SoC

Zynq

UltraScale+ MPSoC)

Khan

Zynq SoC

SDSoC

Khan

Khan

IDT

SDx (FPGA

CC++OpenCL

SDAccelZynq SoC

C/C++

SDSoC)

C

(

)

MotorControl

UnitMC

MotorControl

UnitMC

Processor

ApplicationSpecificFeatures

Single Core ARM

RTOS

PeripheralsAnalytics

HMIMC

Video

Network

Sensors

MemoryLPDDR2

Network

MemoryLPDDR3

TI OMAP orFreescale i.MX6d

~$20

Higher Potentialfor Failure

Small FPGA forSensory input

~$10

MultipleDevices,

Extra BOM

Older Memory,Slower

Single ChipSolution with7010 for

C O V E R S T O R Y


Khan

Khan

Vivado

Design Suite IP ( IP

)

ISO 60601 3 ISO 13485

ICE 61508 ()

ICE 62304 (RTOS )

Khan

IP

ICE 62304 RTOS

QNX

RTOS ICE 62304

Zynq SoC

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TOPIC

Embedded Products

IP IP

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)

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Khan

Zynq SoC 1

Khan Zynq SoC

Khan

(2 3 )

10 15

3

1 3

10

5

Khan Zynq SoC MPSoC

I/O

Zynq

SoC MPSoC

BOM

Time-to-

Market Khan

http://japan.xilinx.com/

applications/medical.html

3 TOPIC Embedded Products Dyplo IP


X C E L L E N C E I N V I S I O N S Y S T E M S

Xilinx FPGAs Advance Autonomous Monitoring of Crowds

FPGA Muhammad Bilal MSc CandidateCenter for Advanced Studies in EngineeringIslamabad, Pakistan [email protected]

Dr. Shoab. A. Khan ProfessorCenter for Advanced Studies in Engineering (www.case.edu.pk)Islamabad, Pakistan [email protected]



24 CCTV

/

/

FPGA

Vivado Design Suite (HLS)

UltraFast

FPGA

FPGA

MicroBlaze

FPGA

Vivado

HLS

(EDK)ISE Design Suite

EDA

Spartan-6 /


14 Xcell Journal 93

Spartan-6

LX45 FPGA

2

1

2

FPGA 2

FPGA

1

FPGA

(

)

[1]

1

[2]

KLT (Kanade-

Lucas-Tomasi)

(SWAD)

2

1

900

1

FPGA

360

1

Microsoft Visual C++ OpenCV

Web

FPGA

FPGA

FPGA

FPGA

3

1

FPGA

2

3

FPGA

FPGA

[3]

EDK

/

FPGA



1 ()

ADC

DAC

MicroBlaze

MicroBlaze

MicroBlaze


16 Xcell Journal 93

2 MicroBlaze

ID (

)

(ISR) MicroBlaze

ISR

DMA

ISR

(

API )

ISR

API

/

MicroBlaze

API

3

MicroBlaze

MicroBlaze

(SRAMSDRAM )

EDK DMA

MicroBlaze

API

ISR

4 FPGA

Picture

in Picture

Vivado HLS

()

2

Video Display Port

Video Capture PortMicroBlaze Processor

Video CaptureDMA Controller

InterruptController

Video DisplayDMA Controller

Processor Core

Display PortInterfaceController

ilmb dlmb

32K DPR

A B

Capture PortInterfaceControllerMicroBlaze Peripheral Bus (PLB or AXI)

Local Mem

oryLocal M

emory

BT-656 StreamEncoder

BT-656 StreamDecoder

Video ADC

Camera

Video DAC

Display

C MNote: Donate Control and Memory interfaces respectively.

C M

C M

FPGA



C/C++

Vivado

HLS RTL

Vivado HLS RTL

1

Vivado HLS

( )

(2D )

Vivado

8

RAM

4

8 RAM

RAM MicroBlaze

DMA

Vivado HLS

MicroBlaze GPIO

8 RAMMicroBlaze

5

5 SA1TA1 SA4

TA4 RAM

16 KBSA1TA1

SA4TA4 1

4

RAM

MicroBlaze

( 4

)

200MHz

10

2

MicroBlaze

(SDK)

C/C++

SDK

3 ISR API

User Application(Algorithm Control & Data Flow)

Video Frame Queue APIGrab_Capture_Frame()

Submit_Display_Frame()Push_Frame_Queue()Pop_Frame_Queue()Frame_Queue_Rest()

Video Ports Low-Level ISRsVideo_Capture_ISR()Video_Display_ISR()

4 FPGA ( )


18 Xcell Journal 93

API

(OSD)

OSD SDK

C/C++

(

/

)

FPGA

PC

2

(http://mha.

cs.umn.edu/proj_recognition.shtml)

www.gettyimages.com

Spartan-6-LX45 FPGA

LUT 30%

RAM 60%DSP48E

12% 6

()

Digilent Atlys Spartan-6

FPGA ADC DAC

5 Vivado HLS

4-Core SAD ComputationHardware Acceleration

MicroBlaze Processor

SWADEngine-1

SWADEngine-2

SWADEngine-3

SWADEngine-4

ControlHandshake

FPGA

16K DPR

A B

TA1

16K DPR

A B

SA1

16K DPR

A B

TA2

16K DPR

A B

SA2

16K DPR

A B

TA3

16K DPR

A B

SA3

16K DPR

A B

TA4

16K DPR

A B

SA4

Search AreaBRAM

Controller

Template AreaBRAM

Controller

SA-X, TA-XChip-Select

GPIOController

HardwareAcceleratorHandshake

GPIOController

HardwareAccelerator DMA

Controller

InterruptController

Processor Core

ilmb dlmb

32K DPR

A B

Micro

Blaze P

LB o

r AX

I Perip

heral Bus

M

M

M

M

M

M

M

M

M

M

MNote: Denotes the memory port.



FPGA

Web

http://www.dailymotion.com/video/

x2av1wo_fpga-based-real-time-human-

crowd-motion-classification-demo_school


x23icxj_real-time-motion-vectors-

computation-on-fpga_news


x28sq1c_crowd-motion-classification-

using-motion-vectors-statistical-

features_school

FPGA

FPGA

EDK

Vivado HLS

FPGA

1. Ramin Mehran, Mubarak Shah,

Abnormal Crowd Behavior Detection

Using Social Force Model, IEEE

International Conference on Computer

Vision and Pattern Recognition (CVPR),

Miami, 2009

2. Duan-Yu Chen, Po-Chung Huang,

Motion- based unusual-event detection

in human crowds, Journal of Visual

Computation and Image Representation,

Vol. 22 Issue 2 (2011), pages 178186

3. OmniTek OSVP: http://omnitek.tv/sites/

default/files/OSVP.pdf

Shoab A. Khan

Dr.

Darshika G. Parera Dr. Umair Ahsun

6 () FPGA


X C E L L E N C E I N T E S T & M E A S U R E M E N T

Test New Memory Technology Chips Using the Zynq SoC

Zynq SoC ZC706 Qualcomm MRAM



Botao Lee Senior Staff EngineerQualcomm Technologies, Inc. [email protected]

Baodong Liu Staff EngineerQualcomm Technologies, [email protected]

Wah Hsu Senior Staff EngineerQualcomm Technologies, [email protected]

Bill Lu Staff EngineerQualcomm Technologies, [email protected]

PRAMMRAMRRAM

Zynq- 7000

All Programmable SoC ZC706

DRAMSRAM

1 0

DRAM PC

SRAM

DRAM SRAM

DRAM SRAM


22 Xcell Journal 93

RAM (MRAM)

2

MRAM SRAM

DRAM

MRAM

MRAM

Zynq SoC

ZC706 FPGA

(FMC) FMC

Zynq SoC

(PL)

2 ARM A9 Zynq

SoC (PS)

PS

1

Zynq SoC ARM A9

PS

DMA

FMC FMC

2

3

3

Linux Linux

1

Xilinx ZC706 Evaluation Board

FMC

XC7Z045 SoC

ZYNQ PS

ZYNQ PL

DMA

MemoryController

FMC Daughtercard

Test Chip



2

1

1

FAE 1

Zynq SoC

1

1

/

Zynq SoC

1 Vivado

Design Suite

Vivado

Vivado Design

Suite

RTL

Linux OS

GUI

Linux OS Linux

GUI

Zynq-7000 All Programmable SoC

ZC706

2

Application Test Configuration Performance Profiling OS Linaro Linux

Device Driver Memory Controller Device Driver

Core 2x ARM A9 Memory Controller

Device XC7Z045 SoC Memory Test Chip

Board ZC706 Evaluation Board FMC Daughtercard

Xcell journal PR

Xcell Journal

9,000

Web iPad

Xcell Journal

E-mail

[email protected]



Unleashing High-Performance USB Devices with Artix-7 FPGA

Artix-7 FPGA USB

FPGA USB



Tom Myers Senior Hardware EngineerAnritsu [email protected]

USB ( )

USB

FPGA

Artix-7

Vivado Design Suite

Artix-7 MicroBlaze

USB 2.0

Anritsu Company ()

USB 2.0

USB

500mA ( 5V)


26 Xcell Journal 93

200MB

4 (Gb)

LPDDR2

Xilinx Power Estimator

MicroBlaze (

(MIG)

)

Vivado IP

I/O

Vivado

MIG LPDDR2

AXI

AXI Shim

MIG

LPDDR2

1

Vivado Design Suite :

(UG907)

1

USB 5V

1

FPGA

USB

USB

Artix-7 USB Bus-Powered Device Architecture

FPGAXilinx

XC7A100TFGG484-2L

PLL, Core Logicat 100 MHz

Reset Controller

XADCTemp/VoltageMonitor

SPIController

SPI FLASH Config/Boot 256Mb/1.8V

AXI4 LiteInterconnect

LPDDR24Gb 128Mx32

LPDDR2Memory

Onterface

AXI shim

AXI4Interconnect

32 bit datapath @

100 MHz

MicroBlaze

Cache

Interruptcontroller

JTAGconfig/debug

5V to 1,8VReg

JTAGconnector

AXI4 LitePeripherals

[email protected] 200 MHz

DMA

USBCore

USB ULPITransceiver

USBconnector

5V to 1.2VReg

5V to 1.0VReg

5V to 1.8VReg

USBULPI100 MHz

osc

SystemClock

1 Artix-7



2 QuickBoot

Configuration Step 1:FPGA configuration

starts here readcritical switch word

Flash MemoryAddr 0

Component 1:QuickBoot Header

Configuration Step 2A:If critical switch word is ON,

then execute warm bootand jump to update bitstream.

Configuration Step 2B:Synchronize and load

update bitstream.

Configuration Step 3A:If critical switch word isOFF, then ignorewarm boot sequence.

Configuration Step 3B:Synchronize and loadgolden bitstream.

CriticalSwitch Word

Warm BootJump Sequence

Component 2:Golden

Bitstream

Component 3:Update

Bitstream

XAPP1081

QuickBoot

2 7

FPGA

XAPP1081

QuickBoot

SDRAM

16nm UltraScale+

UltraRAM

ARM7 Zynq-7000 All

Programmable SoC

[email protected]


X C E L L E N C E I N I N D U S T R I A L

FPGA-Based Fuzzy Controller Manages Sugarcane Extraction

FPGA Deepali Vyas Masters CandidateMody University of Science and TechnologyLakshmangarh, Rajasthan, India [email protected]

Yogesh Misra Research ScholarMewar UniversityChittorgarh, Rajasthan, [email protected]

H. R. Kamath DirectorMalwa Institute of TechnologyIndore, Madhya Pradesh, [email protected]



Virtex-6 FPGA 3

6,000 120

MITS (Mody

Institute of Science and Technology)

FPGA

1 2,500t

26.6kg/

3

1

2

1 2cm

Donnelly

2 3

5

6

Donnelly

2014 1

Donnelly

2

2 [1]

26.6 kg/

2

3

3

2

2014 3

[2]


30 Xcell Journal 93

3

MATLAB

3

[3]

FPGA

FPGA

FPGA

Virtex-6 FPGA

2 3

2

3 MATLAB

3 (Roll Low (RL):

12cm/Roll Medium (RM): 14.3cm/

Roll High (RR): 16.6cm/)

MATLAB

PSpice

(ADC)

5

VHDL

5

IF-THEN

Mamdani Sugeno 2

Mamdani

Mamdani

2

Sugeno

Sugeno

3

3

WEIGHT ()

500kg 1,000kg 11

(LV)

HEIGHT (

) 0 180cm 7

LV

ROLLSPEED ()

12cm/ 16.6 cm/

3 LV

VHDL

3 3

2

( 1)

( 2)

S1= (y2-y1/ 2-x1) S2= (y2-y1/x2- 2)

(DOM) ()

4

Segment1 (=0)Segment2 {( -

1)* 1}Segment3 {( - 1

Cane Carrier

Cane Knives

ShredderKnives

Rake

Car

rier

Bagassefor Boiler

Juice forClarification

CHUTE



2 3

Roll Speed

RL RM RR

HEIGHT = EL HEIGHT = VL HEIGHT = L

NO NO NO

YES YES YES

HEIGHT = VH HEIGHT = H HEIGHT = JR

NO NO NO

YES YES YES

Feed Rate = +42% of Flow Rate

For WEIGHT = SL, UL, EL, VL, l,JR, H, VH, EH, UH and SH









Feed Rate = Flow Rate




HEIGHT = EH

YES

NO

Y2

Y1

X1 X2

1

1.5

0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Segment 1Segment 2 Segment 3 Segment 4

Point 1

Point 2

Point 3

Slope 1Slope 2

3 3 2


32 Xcell Journal 93

2)* 2}Segment4 (=0)

DOM

< 1 (Segment

1)DOM =0

2 1

(Segment 2)DOM = (

1) * 1

3 1

(Segment 3)DOM = FF- (

2) * 2

3 (Segment

4)DOM = 0

If-Then

MATLAB

Fuzzy Logic Toolbox

AND 3

3

231

3

3

DOM

LV

1

1 (

)

Sugeno

Virtex-6

3

1 90cm

Parameters Cane Cane Motor Carrier Cane in Feed Data for Cane Cane level weight speed speed carrier rate next level (MATLAB) (cm) (kg) (rpm) (cm/s) (kg/cm) (kg/s) sampling *(VHDL) ** (cm)

Time Roll kg cm (sec) speed (cm/s)

0 15.4 90.0 750 47.0 24.6 0.938 23.1 -16.0 -6.4 83.6 85.7 10 15.8 83.6 729 52.0 27.2 0.911 24.8 -5.0 -2.0 81.6 84.3 20 15.0 81.6 792 50.0 26.2 0.990 25.9 +19.0 +7.6 89.2 90.4 30 16.2 89.2 908 42.0 22.0 1.135 25.0 -9.0 -3.6 85.6 86.5 40 16.6 85.6 965 44.0 23.0 1.206 27.7 +11.0 +3.9 89.5 90.5 50 13.4 89.5 720 49.0 25.7 0.900 23.1 +16.0 +6.4 95.9 95.9 60 13.8 95.9 760 39.0 20.4 0.950 19.4 -27.0 -9.6 86.3 86.3 70 13.4 86.3 790 44.0 23.0 0.988 22.7 +12.0 +4.8 91.1 91.3 80 15.4 91.1 820 46.0 24.1 1.025 24.7 0.0 0.0 91.1 93.4 90 16.2 91.1 555 73.0 38.2 0.694 26.5 -4.0 -1.6 89.5 93.4 100 13.0 89.5 609 51.0 26.7 0.761 20.3 -5.0 -2.0 87.5 92.3 110 14.3 87.5 578 62.0 32.5 0.723 23.5 +6.0 +2.4 89.9 90.2 120 14.6 89.9 598 57.0 29.8 0.748 22.3 -11.0 -4.4 85.5 87.0 130 12.3 85.5 700 44.0 23.0 0.875 20.1 +4.0 +1.6 87.1 88.8 140 12.6 87.1 679 48.0 25.1 0.849 21.3 +11.0 +4.4 91.5 91.7 150 15.4 91.5 800 46.0 24.1 1.000 24.1 -6.0 -2.4 89.1 91.3 160 12.0 89.1 845 32.0 16.8 1.056 17.7 -15.0 -6.0 83.1 84.2 170 14.3 83.1 835 45.0 23.6 1.044 24.6 +17.0 +6.1 89.2 90.3 180 14.6 89.2 874 42.0 22.0 1.093 24.0 +6.0 +2.4 91.6 92.1 190 15.0 91.6 900 41.0 21.5 1.125 24.2 +2.0 +0.8 92.4 92.1 200 15.4 92.4 924 40.0 20.9 1.155 24.1 -6.0 -2.4 90.0 91.4

* Cane level of FPGA-implemented system after each sampling ** Cane level of MATLAB-implemented system after each sampling



MATLAB

Fuzzy Toolbox 7.11.0.584

(R2020b) 3

ISE Design Suite 14.5

VHDL Virtex-6

FPGA

10 200

6 756

90cm

750kg

1

VHDL

FPGA

MITS

3

VHDL

ISim

ISim

4

750kg

Donnelly

90cm 16.6 cm/

54.2rpm (MATLAB)

36H

54rpm MATLAB

Virtex-6

(LUT) 78%

93% 1%LUT

1%

VHDL

( 2 )

-

MITS Spartan-6

FPGA

LUT

Virtex-6

National

Sugar Institute

National

Sugar Institute

1. Y. Misra and H.R. Kamath, Design

Algorithm of Conventional and Fuzzy

Controller for Maintaining the Cane

Level During Sugar Making Process,

International Journal of Intelligent

Systems and Applications, ISSN: 2074-

9058,Vol.7 No.1, December 2014

2. Y. Misra and H.R. Kamath,

Implementation and Performance

Analysis of a Three Inputs Conventional

Controller to Maintain the Cane Level

During Cane Crushing in FPGA using

VHDL, International Journal of

Engineering Research & Technology

(IJERT), ISSN: 2278-0181, Vol. 3 Issue 9,

September 2014

3. Y. Misra and H.R. Kamath, Analysis and

design of a three input fuzzy system for

maintaining the cane level during sugar

manufacturing, Journal of Automation

and Control (accepted), ISSN: 2372-3041

4 750 kg 90 cm 16.6 cm/s

2

Three-inputconventional

controller

Three-inputfuzzy

controller(MATLAB)

Three-inputfuzzy

controller(Xilinx VHDL)

Percentage of time cane is in between 85cm-95 cm (% Time)

45.8 94.7 88.0

Lowest level of cane in chute (cm) 61.7 84.2 81.6

Highest level of cane in chute (cm) 103.5 95.9 95.9

34 Xcell Journal 93

X P L A N AT I O N : F P G A 1 0 1

Zynq MPSoC Gets Xen Hypervisor Support

Zynq MPSoC Xen Steven H. VanderLeest Chief Operating OfficerDornerWorks, [email protected]

X P L A N A T I O N : F P G A 1 0 1


Zynq Xen

Xen

DornerWorks

Zynq UltraScale+ MPSoC

Xen

Xen Zynq

(OS )

()

Zynq MPSoC

Xen Xen Zynq


36 Xcell Journal 93

OS

(OS

)

OS (

)

1960

1974 Popek Goldberg

3

(VMM)

VMM ()

()

VMM

VMM

VMM

GUI

(

OS )

Type 1

Type 2

OS

OS

OS

Mac MacBook

Parallels Windows

Windows VirtualBox

Linux

(

)

(FAA)

DO-248C

FAA

1

MILS (Multiple Independent Levels of

Security)

MRI

()CT

(

)

OEM

(ADAS)

VMM

(CPU I/O)

CPU

1

OS

CPU

() 1

I/O

RAW



I/O

2

I/O

1 I/O

(

)

I/O

GNU General Public License (

GPLv2 GPLv3)GNU

Lesser General Public LicenseApache

LicenseBSD ()

(

)

1 Red Hat

Linux OS 10

Xen Zynq Zynq UltraScale+

MPSoC Xen

ARMv8

64

ARM Cortex-A53

Zynq MPSoC

Xen

DornerWorks

Xen Zynq

Xen

OS

OS

CPU

I/O Xen

Xen

Xen 1

dom0 dom0

Time

First-StageBoot Loader

(FSBL)U-Boot XenKernel

dom0

Guest 1

Guest 2

1 OS


38 Xcell Journal 93

(domU )

I/O

ARM

Zynq

MPSoC

(Cortex-A53

Cortex-R5)

2

Xen Zynq

Cortex-A53

1 Cortex-R5

OS

FSBL ( 1

) R5

R5 R5 A53 (

FSBL )

U-Boot 2

Xen

dom0

dom0

1

dom0

OS

dom0

domU

Xen XSM-FLASK

ARM

Cortex-A53

ARMv8 2

4

1

EL3

ARM TrustZone Monitor

EL2

OS EL1

EL0

64 32

Xen Zynq ARMv8

AArch64 64

32

dom0

3

1 (dom0 )

1

2 3

CPU

2 ARM EL2

EL0

EL1

EL2

EL3

App 1 App 2 App 3 App 4

Guest OS 1 Guest OS 2 Secure World OS

Hypervisor

TrustZone Monitor

Cortex

-A53

Cortex-R

5

TrustedApp 6

TrustedApp 5



(MMU)

I/O

Cortex-A53

I/O FPGA

I/O

I/O dom0

Xen

dom0

I/O

dom0

I/O Xen

(I/O ) Xen

Xen

I/O

OS

API dom0

dom0

I/O

3 1 2 3

dom0

Hyp

ervi

sor

OS App OS AppOS App OS App

dom0

Hyp

ervi

sor

OS App OS App

dom0

Hyp

ervi

sor

OS App OS App

Guest 1

Hyp

ervi

sor

OS1 App1 OS1 App2

Guest 2

Hyp

ervi

sor

OS2 App3 OS2 App4

Guest 3H

yper

viso

r

OS3 App5 OS2 App6

Guest 1

Hyp

ervi

sor

OS1 App1 OS1 App2

Guest 3

Hyp

ervi

sor

OS3 App5 OS3 App6

Guest 3

Hyp

ervi

sor

OS3 App5 OS3 App6

Guest 1

Hyp

ervi

sor

OS1 App1 OS1 App2

Guest 3

Hyp

ervi

sor

OS3 App5 OS3 App6

Guest 2

Hyp

ervi

sor

OS2 App3 OS2 App4

Core 0

Core 1

Core 2

Core 3

Time


40 Xcell Journal 93

Xen Zynq Zynq SoC

(

)

DornerWorks Xen

FPGA

DornerWorks

Xen Zynq MPSoC

Xen

dom0 (Linux )

Xen Zynq

QEMU

x86

Zynq MPSoC

6 Virtex-7 FPGA

Remus

( Xen

)

4 /

DornerWorks Zynq

MPSoC Xen

4 Xen Zynq

Repository

I/O Stimulus

Dashboard

Target FarmCode Under TestTest Scripts

Stimulus Definition

Parsed Results

Test Measurements

Build ImageLoad ImageRun Tests

FutureExpansion

ZynqMPSoC

QEMU

REMUS

Linux GuestOS

BuildConfig

Tests

FSBL U-Boot

DeveloperBuild and

DebugEnvironment

Build &Test Server



5 Xen

Developer PC

Xen source

Xilinx Linux,ARM FSBL,

U-Boot source

64-bit ARM GCCcross-compiler

Buildroot source

ARM FSBL,U-Boot,

Xilinx Linux image

PetalinuxBuildroot

Xen image dom0 image

Pull Pull Pull

Program

CompileBuild

Generate

Passed as VirtualSATA Drive

TFTP

Load

Load

Load

Load

On Chip Memory QEMU

U-Boot

Xen

dom0

domU

Target

DornerWorks

DornerWorks

(

)

Jira

DornerWorks Xen

http://xen.world

Xen Zynq MPSoC

Xen Xen

x86 PC Type 1

Windows VirtualBox

Xen ARM

ARM

( Cortex-A53 Cortex-A15

)

5

Xen dom0 Linux

OS

http://www.

xenproject.org/

DornerWorks Zynq MPSoC

Xen Zynq

http://dornerworks.com/services/

XilinxXen

OS

Zynq MPSoC Xen



Vivado IPI Opens FPGA Shareable Resources for Aurora Designs

Vivado IPI Aurora FPGA K Krishna Deepak Senior Design EngineerXilinx, [email protected]

Dinesh Kumar Senior Engineering ManagerXilinx, [email protected]

Jayaram PVSS Senior Engineering ManagerXilinx, [email protected]

Ketan Mehta Senior IP Product Manager Xilinx, [email protected]



IP Aurora

1 FPGA

IP (Intellectual Property)

1

Aurora

Vivado Design Suite IP

(IPI)

Aurora

Aurora

IP

Aurora

ASIC

FPGA


44 Xcell Journal 93

Aurora

Aurora

Vivado Design

Suite IP Aurora

64b66b Aurora 8b10b

Vivado IP (IPI)

IPI Aurora

64b66b Aurora 8b10b

Aurora 64b66b

IP Aurora 8b10b

Aurora

Aurora 64b66b

1

(MMCM)BUFGIBUFDS

GT GT

(GT) 7

2

GT1 GT2

Kintex-7 FPGA KC705

16 Aurora

64b66b GT

1

Tx Aurora ProtocolEngine

Tx Aurora ProtocolEngine

ScramblerScrambler

DescramblerRx Aurora ProtocolEngineRx Aurora Protocol

Engine

TxRx StartupFSM

CBCC

FIFO

CBCC

FIFO

TXMMCM

GTCommon

User IF GT1 GT2

IBUFDS

IBUFDS_GT

BUFG

BUFG

BUFGCE

64 64 64

64 6432

32

gt_ref_clk

drp_clk drp_clk

user_clk

rxrec_clk

rxusr_clkrxusr_clk2

init_clk

txusr_clk

txusr_clk2

tx_out_clkX

X

1 Aurora 64b66b



FPGA GT

IP

AURORA GT

Aurora

()

(

)

2

GT

IP

IP (IPI)

IPI

IP

I/O

1168Vivado IP

AXI IP

(XAPP1168)

IPI

Aurora

GT PLL

GT GT

(

)

1

1 1

IP Aurora

1

Aurora

Aurora

1 FPGA

4

4 Aurora

Aurora 1 GT

4

GT

4 GT GT

1 Aurora

3 Aurora

3 Kintex-7 FPGA KC705 GT

16-Lane Aurora Design

Resource Availability in Device Used by Aurora

MMCME2_ADV 10 1

IBUFDS_GTE2 8 2

GTE2_COMMON 4 4

GTXE2_CHANNEL 16 16


46 Xcell Journal 93

2 1 Aurora () 3

USER_DATA_S_AXIS_TX

GT_DIFF_REFCLK1

INIT_DIFF_CLK

CORE_CONTROL

GT_SERIAL_RX

reset_pb

pma_init

drp_clk_in

GT_DIFF_REFCLK1INIT_DIFF_CLK

USER_DATA_M_AXIS_RX

CORE_STATUS

channel_up

gt_pll_lock

lane_up[0:0]

hard_err

mmom_not_locked_out

soft_err

GT_SERIAL_TX

tx_out_clk

link_reset_out

user_clk_out

sync_clk_out

gt_qpllclk_quad1_out

gt_qpllrefclk_quad1_out

init_clk_out

sys_reset_out

gt_reset_out

gt_refclk1_out

aurora_64b66b_master

Aurora 64B66B

aurora_64b66b_slave1

Aurora 64B66B

USER_DATA_S_AXIS_TX

CORE_CONTROL

GT_SERIAL_RX

gt_rxcdrovrden_in

loopback[2:0]

mmcm_not_locked

power_down

refclk1_in

user_clk

sync_clk

reset_pb

pma_init

drp_clk_in

init_clk

gt_qpllclk_quad1_in

gt_qpllrefclk_quad1_in

USER_DATA_M_AXIS_RX

CORE_STATUS

GT_SERIAL_TX

tx_out_clk

link_reset_out

sys_reset_out


Aurora 64B66B

USER_DATA_S_AXIS_TX

CORE_CONTROL

GT_SERIAL_RX

gt_rxcdrovrden_in

loopback[2:0]

mmcm_not_locked

power_down

refclk1_in

user_clk

sync_clk

reset_pb

pma_init

drp_clk_in

init_clk

gt_qpllclk_quad1_in


USER_DATA_M_AXIS_RX

CORE_STATUS

GT_SERIAL_TX

tx_out_clk

link_reset_out

sys_reset_out


Aurora 64B66B

USER_DATA_S_AXIS_TX

CORE_CONTROL

GT_SERIAL_RX

gt_rxcdrovrden_in

loopback[2:0]

mmcm_not_locked

power_down

refclk1_in

user_clk

sync_clk

reset_pb

pma_init

drp_clk_in

init_clk

gt_qpllclk_quad1_in


USER_DATA_M_AXIS_RX

CORE_STATUS

GT_SERIAL_TX

tx_out_clk

link_reset_out

sys_reset_out

4 4

Design with Four Single Lanes

Resource Without Shared Logic With Shared Logic

MMCME2_ADV 4 1

IBUFDS_GTE2 4 1

GTE2_COMMON 4 1

GTXE2_CHANNEL 4 4



( 2)

Aurora

2 4

12 GT 7 FPGA

GT

1

12 GT

12

2 1 + 3

1+3

3 6

2

INIT_CLK GT

3 3 1 2 4 Aurora



aurora_64b66b_master1aurora_64b66b_master1

aurora_64b66b__slave1

Aurora 64B66B

GT_DIFF_REFCLK1INIT_DIFF_CLK

USER_DATA_M_AXIS_RX

CORE_STATUS

tx_out_clk

link_reset_out

QPLL_CONTROL_OUT

GT_SERIAL_TX

gt_qplllock_quad1_out

gt_qplllock_quad2_out

gt_qplllock_out

gt_qpllrefclklost_out

gt_qpllrefclklost_quad1_out

gt_qpllrefclklost_quad2_out

user_clk_out

sync_clk_out







init_clk_out

sys_reset_out

gt_reset_out

gt_refclk1_out

USER_DATA_S_AXIS_TX

GT_DIFF_REFCLK1

INIT_DIFF_CLK

CORE_CONTROL

GT_SERIAL_RX

reset_pb

pma_init

drp_clk_in

GTXQ2

GTXQ1

GTXQ0

3 4

X X

X X

X 2

X X

1 X

GT Refclk1 GT Refclk2GTXQ1 None


USER_DATA_S_AXIS_TX

CORE_CONTROL

GT_SERIAL_RX

QPLL_CONTROL_IN

gt_qplllock_in

gt_qplllock_quad1_in

qt_qpllrefclklost_in

qt_qpllrefclklost_quad1_in

refclk1_in

user_clk

sync_clk

reset_pb

pma_init

drp_clk_in

init_clk

gt_qpllclk_quad1_in


gt_qpllclk_quad2_in


Aurora 64B66B

GTXQ2

GTXQ1

GTXQ0

X X

X X

X X

4 2

2 3

X 1

USER_DATA_M_AXIS_RX

CORE_STATUS

GT_SERIAL_TX

tx_out_clk

link_reset_out

sys_reset_out

aurora_64b66bb_slave2


USER_DATA_S_AXIS_TX

CORE_CONTROL

GT_SERIAL_RX

QPLL_CONTROL_IN

gt_qplllock_in

gt_qplllock_quad1_in

qt_qpllrefclklost_in

qt_qpllrefclklost_quad1_in

refclk1_in

user_clk

sync_clk

reset_pb

pma_init

drp_clk_in

init_clk

gt_qpllclk_quad2_in


gt_qpllclk_quad3_in


Aurora 64B66B

GTXQ2

GTXQ1

GTXQ0

X X

3 4

1 2

X X

X X

X X

USER_DATA_M_AXIS_RX

CORE_STATUS

GT_SERIAL_TX

tx_out_clk

link_reset_out

sys_reset_out

5 12

12-Single-Lane Designs

Resource Without Shared LogicWith Shared Logic

(default)

With Shared Logic (using single-ended master input clocks)

MMCME2_ADV 12 3 3

IBUFDS_GTE2 12 3 1

GTE2_COMMON 12 3 3

GTXE2_CHANNEL 12 12 12


48 Xcell Journal 93

6 2

IBUFDS/IBUFDS_GTE2

( 3)IBUFDS_GTE2

MMCM

3 x 4 3 4

3 4 Aurora

3 1

2

Aurora

(16 )

48

4 Aurora

Tx

TxRx

Rx

Board1/Chip1 Board2/Chip2N != M

#M lanes

#N lanes

6 3 x 4

Optimized Lane Selection for 3 x 4-Single-Lane Designs

GTQ2 Master1_3 Master1_4

Slave2_3 Slave2_4

GTQ1 Slave2_1 Slave2_2

Slave1_4 Master1_2

GTQ0 Slave1_3 Slave1_2

Master1_1 Slave1_1



Aurora

GT

12

2*12

12

MMCM

( 5)

ROI

4 (

) (

) GT

Aurora

(/) TX

RX

2 Aurora

7 FPGA

1

1227

Aurora 64B/66B IP

(XAPP1227)

1

BUFG

Aurora

Aurora

(BUFG)

BUFG BUFR/BUFH

GT

TX

7 Aurora 1

BUFG

(DRP)

Aurora

DRP

Aurora

DRP

BUFG

Aurora

Aurora

Aurora

Vivado IP

All

Programmable

UltraScale

GT GT

Aurora IP

IPIAurora (http://

japan.xilinx.com/products/design_

resources/conn_central/grouping/

aurora.htm)

7 48

48-Single-Lane Designs

Resource Without Shared Logic With Shared Logic

MMCME2_ADV 48 4

IBUFDS_GTE2 48 4

GTE2_COMMON 48 12

GTXE2_CHANNEL 48 48

50 Xcell Journal 93


Making XDC Timing Constraints Work for You

XDC Adam Taylor Chief Engineer [email protected]



RTL FPGA

FPGA SoC

(

)

Vivado Design Suite

1

( 1 )

Vivado

Vivado

3

/

/

()


52 Xcell Journal 93

2

1,000

1,000

Vivado

Vivado

(XDC)

XDC Tcl

Synopsys

(SDC) XDC

set_clock_groups name logically_exclusive physically_exclusive asynchronous group

name group

(

)

logically_exclusive

physically_exclusive

(BUFGMUX

BUFGCTL )

Vivado

asynchronous

2

set_input_jitter

set_system_ jitter

()

1

2

(

)

2

( 2 )

XDC

XDC

set_multicycle_path path_multiplier [-setup|-hold] [-start|-end][-from ] [-to ] [-through ]

(

) path_multiplier

1

path_

mutiplier 2

OSC 1

OSC 2

CLK1Domain

CLK2Domain

CLK1Domain

1 CLK1 CLK2



= -

1 -

= - 1 (

)

XDC

2

1

I/O

I/O

I/O

I/O I/O

Vivado Design Suite

3

DONT_TOUCH

MARK_DEBUG RTL

CLOCK_DEDICATED_ROUTE

I/O

I/O

I/O FPGA

I/O

I/O

I/O

FPGA

I/O I/O

I/O

I/O

I/O

FPGA I/O

I/O

Zynq-7000

All Programmable SoC (

7 ) I/O

High Performance (HP)

High Range (HR) 2

HP

LVCMOS 33 LVCMOS 25

HR HP

I/O

HR

3.3V 2.5V

3

Propagation Time

> 1 CLK period

Timing analysis between registers uses 1 CLK period by default.

2


54 Xcell Journal 93

SI ( )

SI IBIS

IBIS Vivado

[File] [Export] [Export

IBIS model]

SI

SI PCB

SI

I/O

set_property PACKAGE_PIN G17 [get_ports {dout}] set_property IOSTANDARD

LVCMOS33 [get_ports {dout}] set_property SLEW SLOW [get_ports {dout}]

set_property DRIVE 4 [get_ports {dout}]

HP I/O

(DCI)

I/O

SI

I/O

I/O

FPGA

I/O

3

BEL (Basic Element of Logic)

LOC (Location)

PBlock ( (P) )

FPGA

LOC

BEL

PBlock

PBlock

PBlock

RPM (

)

RPM DSP

LUTRAM

RPM PBlock

()

RPM

3 7 HP () HR I/O

Bank 18HP

50 I/0

Bank 17HP

50 I/0

Bank 16HP

50 I/0

Bank 32HP

50 I/0

Bank 33HP

50 I/0

Bank 34HP

50 I/0

Bank 12HP

50 I/0

Bank 13HP

50 I/0

Bank 14HP

50 I/0

Bank 15HP

50 I/0



2

3

HDL

U_SET RPM

HU_SET RPM

RLOC SET

RLOC RLOC = XmYm

X Y FPGA

RLOC

RPM_GRID

RPM_GRID

4 HDL

HDL

4

SIGNAL ip_sync : STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS =>0);SIGNEL shr_reg : STD_LOGIC_VECTOR(31 DOWNTO 0) :=(OTHERS =>0);

ATTRIBUTE RLOC : STRING;ATTRIBUTE HU_SET : STRING;ATTRIBUTE HU_SET OF ip_sync : SIGNAL IS ip_sync;ATTRIBUTE HU_SET of shr_reg : SIGNAL IS shr_reg;

japan.xilinx.com/xcell/

Xcell Publications ?

Xcell

Xcell Publication Mike Santarini ([email protected])


T O O L S O F X C E L L E N C E

Toward Easier Software Development for Asymmetric Multiprocessing Systems

Arvind Raghuraman Staff EngineerMentor Graphics Corp. [email protected]



Mentor Embedded Multicore Framework SoC

Zynq UltraScale+ MPSoC

SoC ( )

ARM Cortex-A53 ARM Cortex-R5

SoC

IP FPGA

Zynq MPSoC SoC

(SMP) OS

(AMP)

AMP SoC

(Linux

(RTOS)

)


58 Xcell Journal 93

( OS )

()

(IPC)

Mentor Graphics Mentor Embedded

Multicore Framework AMP

2

1

remoteproc

API 1

AMP OS

IPC rpmsg

API Mentor Embedded Multicore

Framework

AMP

Linux

Mentor

Embedded Multicore Framework

API Mentor

Graphics Linux 3.4.x

remoteproc

rpmsg API Linux remoteproc

rpmsg

Texas Instruments Linux

Linux OS

Linux

Linux rpmsg Linux OS

Linux

OS AMP

remoteproc API rpmsg API

Linux

OS

API

Mentor Embedded Multicore Framework

C

RTOS

remoteproc

rpmsg

Linux API

1a


RTOS

Porting Layer (

)

(HIL) OS

OS

1b Linux remoteproc

rpmsg

1 Mentor Embedded Multicore Framework: RTOS (a) Linux remoteproc rpmsg (b)

a. b.

Application Application

Mentor Embedded Multicore Framework Linux Kernel

Hardware Hardware

Environment

remoteproc remoteprocplatform driver

rpmsg user devicedriver

rpmsg

remoteprocPorting Layer HIL

RTOSOr

Bare-Metal

VirtIO

rpmsg

VirtIO

Chardevice



remoteproc rpmsg

remoteproc

rpmsg

remoteproc

rpmsg

IPC


AMP RTOS

Linux

remoteproc/rpmsg

Linux AMP

OS

AMP 2


AMP

AMP (uAMP)

OS

OS

3a Mentor Embedded

Multicore Framework (

)

SoC

(sAMP)

sAMP OS

(

)

Mentor


sAMP SoC

3b

2

OS

OS

Mentor Embedded Multicore

Framework

/

SoC

2 Mentor Embedded Multicore Framework AMP

remoteproc

Linux

remoteproc &rpmsg

Master Core

RTOSor

Baremetal

RemoteCore

Master CoreRemote

Core Master CoreRemote

Core

Linux

remoteproc &rpmsg

rpmsg rpmsg rpmsg

Master

Remote

RTOSor

Baremetal

RTOSor

Baremetal

RTOSor

Baremetal

MEMF

MEMF

MEMF

MEMF

remoteproc remoteproc

Configuration a Configuration b Configuration c


60 Xcell Journal 93

Mentor Embedded Multicore

Framework

RTOS

()

Linux

Linux

RTOS


API AMP

AMP

API

AMP

(1

) (

)

OS

OS

IPC

OS SoC

AMP

AMP OS

OS

OS

BSP

I/O

OS

OS

OS

(

)

Linux OS Linux

3 Mentor Embedded Multicore Framework : uAMP (a) sAMP (b)

Cortex-A53Core

Cortex-A53Core

Cortex-R5

Core

Cortex-R5

Core

a.

IPC between OS contexts using rpmsg

b.

Cortex-A53Core

Cortex-A53Core

Cortex-R5

Core-

Baremetal

RTOSMentor

EmbeddedLinux (SMP)

LinuxGuest 0

LinuxGuest 1

Baremetal

RTOS

Hypervisor

remoteproc remoteproc

IPC between OS contexts using rpmsg

M E M F M E M F M E M F

M E M F

M E M F M E M F

remoteproc

Cortex-R5

Core Cortex-A53Core

remoteprocrpmsg

remoteprocrpmsg



(DTS)

Nucleus RTOS

remoteproc

OS

Mentor Embedded

Multicore Framework

Linux

RTOS

ELF

ELF

IPC

remoteproc

remoteproc_

init API

remoteproc

remoteproc

rpmsg/VirtIO

IPC

remoteproc remoteproc_

boot API

remoteproc_

shutdown API

remoteproc_deinit API

( 5

remoteproc

API )

API

API

remoteproc

remoteproc_resource_init API

remoteproc_resource_

deinit API

Linux remoteproc

Linux

RPMSG (IPC)

rpmsg API

rpmsg

rpmsg

rpmsg

(rpmsg )

rpmsg rpmsg

rpmsg

rpmsg

rpmsg

rpmsg

rpmsg

rpmsg

4 rpmsg

remoteproc

rpmsg

remoteproc

rpmsg

rpmsg

rpmsg

rpmsg

rpmsg_sendxx API (

) rpmsg_ trysendxx

API ()

remoteproc_resource_

deinit rpmsg

rpmsg


62 Xcell Journal 93

remoteproc_shutdown API

5

remoteproc

API rpmsg API

rpmsg

VirtIO

VirtIO lguestKVMMentor

Embedded Hypervisor

I/O

rpmsg VirtIO

rpmsg

rpmsg VirtIO

VirtQueue

AMP AMP

AMP

SoC

OS

OS

Mentor

Embedded Sourcery CodeBench

OS

(Mentor Embedded Linux Nucleus

RTOS ) IDE

Sourcery CodeBench

Linux Nucleus

RTOS

JTAG Linux

Nucleus RTOS

GDB

AMP

OS

OS

4 rpmsg

1

1

21

2

Application logic producing data

Remote 1

rpmsg channel

endpoint

Master

Remote 2

Endpoint

Data producer



OS

OS

Mentor Embedded

Sourcery Analyzer

Mentor OS OS

AMP


Mentor OS

ARM

SoC

Mentor

OS

AMP

AMP

AMP

Linux

RTOS

Mentor Graphics

Zynq-7000 All Programmable SoC

Mentor


OpenAMP

Mentor Graphics

/* rpmsg channel created callback - invoked on channel creation */void rpmsg_channel_created(struct rpmsg_channel *rp_chnl) { ..

/* Use RTOS provided primitives (ex., semaphores) to release the application context blocked on rpmsg channel creation */}

/* rpmsg channel deletion callback - invoked on channel deletion */void rpmsg_channel_deleted(struct rpmsg_channel *rp_chnl) { ..

/* Use RTOS provided primitives (ex., semaphores) to release the application context blocked on rpmsg channel deletion */}

/* rpmsg receive callback - invoked when data received on default endpoint */void rpmsg_rx_cb(struct rpmsg_channel *rp_chnl, void *data, int len, void * priv, unsigned long src) { ..

/* Copy received data to application buffer and use RTOS provided primitives (ex., semaphores) to release the application IPC data processing context */}

/* Initialize remote context */int Initialize_Remote_Context(..) { ...

/* Initialize remote context */ remoteproc_init(remote_fw_info, rpmsg_channel_created, rpmsg_channel_deleted, rpmsg_rx_cb, &proc);

/* Boot remote context */ remoteproc_boot(proc); ...

}

/* Send data to remote context after rpmsg channel creation */int Send_Data_To_Remote(..) { ..

rpmsg_send(app_rp_chnl, user_buff, sizeof(user_buff)); ..

}

/* Finalize remote context after rpmsg channel deletion */int Finalize_Remote_Context(..) { ..

/* Shut down and finalize the remote processor */ remoteproc_shutdown(proc); remoteproc_deinit(proc); ..

}

5 remoteproc API rpmsg API

Xcell Journal Daily Blog Xcell Journal Daily Blog

Recent n Use C/C++ to Offload Image Processing to Programmable Logic

n EE Journals Kevin Morris writes some choice words about high-level synthesis and the Xilinx Vivado HLx introduction

n Xcell Software Journal Issue #2 now online, ready for you to read and download

n Bunnie Huangs Novena Open-Source Linux Laptop incorporates a User-Programmable Spartan-6 FPGA

n Auviz offers free eval version of its high-performance OpenCV Computer Vision Library for Xilinx All Programmable devices

: www.forums.xilinx.com/t5/Xcell-Daily/bg-p/Xcell

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Xcell Daily Blog

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Xcell Journal 日本語版 75 & 76 合併号

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Installation and Operating Instructions - BPC Ventilation · 1 Installation and Operating Instructions . Xcell 400 QV . Xcell 400 QVW . Xcell 400 QVI . Mechanical Ventilation Unit

ザイリンクス UltraScale : ザイリンクスの次世代 …...ザイリンクス UltraScale : ザイリンクスの次世代アーキテクチャでカスタマーの次世代アーキテクチャを実現

Xcell Journal 日本語版 81 & 82 合併号

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