01 Test Overview 2pp

1© K.T. Tim Cheng 01_overview, v1.0

About the Instructor

Kwang-Ting (Tim) Cheng– PhD, 1988, Univ. of California, Berkeley– 1988-1993: AT&T Bell Labs– 1993-Present: Professor, Dept. of ECE, Univ. of California,

Santa Barbara– 1999-2002: Director, Computer Engineering Program, UCSB– 2005-2008: Chair, Dept. of ECE, UCSB– July-Dec. 2008: Visiting Professor, Univ. of Tokyo– Research areas: VLSI test, validation and verification;

multimedia computing (image and video content analysis)



UCSB’s SoC Design and Test LabResearch directions:– Test techniques for heterogeneous SOC– Functional and timing verification– Post-silicon debug and validation

Current projects:– Models and coverage metrics for effective post-silicon validation– Low-cost on-line checking for consumer electronics– Self-test and error resilience for high-speed IO and RF systems – Test, yield and reliability analysis for multi-core systems with

spares – Design and test for flexible electronics


Class Website

http://www.cad.t.u-tokyo.ac.jp/~timcheng/index.html



Overview of IC Testing

• Types of Testing at IC level

• IC Production Test Process

• Burn-in

• Board, System and Field Testing

• Costs of Testing

• The Testing Problems

Outline - Overview


Verification vs. Testing

Verifies correctness of design.Performed by simulation, hardware emulation, or formal methods.Performed once prior to manufacturing.Responsible for quality of design.

Verifies correctness of manufactured hardware.Two-part process:– 1. Test generation: software

process executed once during design

– 2. Test application: electrical tests applied to hardware

Test application performed on every manufactured device.Responsible for quality of devices. *from M. Bushnell/V. Agrawal

Verification Testing


Testing Process Is Never Perfect

Based on analyzable fault models, which may not map on real defects.Incomplete coverage of modeled faults due to high complexity.Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss.Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.


Testing as Filter Process

Fabricatedchips

Good chips

Defective chips

Prob(good) = y

Prob(bad) = 1- y

Prob(pass test) = high

Prob(fail test) = high

Prob(failtest) = lowProb(passtest)

= low

Mostlygoodchips

Mostlybad

chipsAck: Bushnell and Agrawal, Essential of Electronic Testing, 2000


Types of TestingCharacterization testing, or design debug– Verifies correctness of design & of test procedure – data will be used for final spec.– data can be used to identify area in which

processing can be helped for increased yield– test time is not important

Manufacturing testing/Production testing– Factory testing of all manufactured chips for

parametric faults and for random defects

Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000


Characterization TestWorst-case test– Choose test that passes/fails chips– Select statistically significant sample of chips– Repeat test for every combination of 2+

environmental variables– Plot results in Shmoo plot– Diagnose and correct design errors

Continue throughout production life of chips to improve design and process to increase yield

Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000


Shmoo Plot


Types of Manufacturing TestsWafer sort or probe test – done before wafer is scribed and cut into chips

Packaged device tests


Where Does Probe Fit In?

Design Photomask WaferFabrication

WaferTest

PackageFinalTest


• Reservoir of ink

• Plunger or fish line dispenses one drop onto each bad die

• Plunger is electro-magnetically or pneumatically driven

Bad Die Inker


Inked Wafer


Typical Probe Test CellTestHead

Probe Card

Prober

Stimulus,Response

Automatic

Test

Equipment

X & Y Location

Good/Bad

Wafer

Spring Assy

Load Board


Probe Test Cell

ATEProber Interface Board

Spring Contactor Assembly

Probe Card

Prober


Production IC Probe Floor


Probe Card

Provides the primary electrical contact between the tester and each device-under-test (DUT) on the wafer“Needles” on the probe card contact the device I/O pads on the die (same pads are used for package interconnects; often called bond pads)There is usually a different, custom probe card for every circuit designThe cards are delicate and fragile


Cantilever Needle, Epoxy Ring Probe Card Technology

Printed Circuit Board (Probe Card)

NeedleEpoxy Ring Needle soldered

to PCB


Cantilever Needle Card


Multi Level Cantilever Needles


Vertical Cards for Area Array

WAFER

DUT Board DUT Board

Vertical NeedlesInsulator

Space Transform

IBM Buckling Beam “Cobra,” Patented in 1978


Vertical Card (3500 Needles)


Where Does Final Test Fit In?

Design Photomask WaferFabrication

WaferTest

PackageFinalTest


Production Testing for Packaged Devices

AC Parametric Test

DC Parametric Test

Functional Test

Burn-In Test

ContactTestTo screen out assembly related failures. To insure that the tester interface is in contact with the device.

Steady state tests

To ensure that state changes occur at the right time

To screen out infant mortalities


Why Do We Burn-In?

Burn-in stress required to meet IM induces early wearout for die size >400 mils

Source: IntelSource: Intel


Burn-in Testing

Correlations have been made between life span at room temperature & life span at elevated temperature.Charts of these correlations have been made for each technologyPut the device in a furnace for a certain length of time at an elevated temperature and voltage– By applying high voltage to the IC’s pins, burn-in accelerates

the time-to-failure of oxide defects (weak oxide, pin holes, uneven layer growth, etc) typically found in MOS devices

– High temperature accelerates these and other defects, such as ionic contamination and silicon defects


An Example of IC Failure Rate vs. System Operating Time With and Without Burn-in

1

10

100

1,000

10,000

100,000

No burn-in125C burn-in

150C burn-in

101 102 103 104 105 106

Time (hr)


Problem of Burn-In: Leakage Dominates Burn-In Power

Thermal runaway– A destructive positive feedback

condition during BI– Test sockets can be destroyed


Functional Testing for Digital Circuits

TestVectors

CircuitResponse

DigitalCircuitDigitalCircuit

ComparatorComparator

Test Result

TrueResponse

TrueResponse

…. 0 1…. 0 0

….

1 1 ….1 0 ….

…. 0 1 ….….

0 1 ….


Tests are done by Parametric Measurement Unit (PMU)– Leakage test– Threshold ViL & ViH test– Output drive current test– Power consumption test– Output short current test

DC Parametric Testing


AC Parametric TestingTo ensure that value/state changes occur at the right time Some of AC parametric tests are mainly for characterization and may not be necessary for production test.– Test for rise and fall times of an output signal– Tests for setup and hold times– Tests for time to tri-state– Tests for measuring delay times

» E.g. tests for memory access time– Functional at-speed tests (speed sorting)


Mov00100.mpg


Shorts testing In-circuit testing – Check devices already mounted on a board– An external tester applies patterns directly to the

inputs of the device & observe the outputs– The tester must be capable of electronically

isolating the IC under test from the board environment

Functional Board Testing

Board Level Testing


Final test in the manufacturing processChecking the right assembly of components such as boards, backplanes, cables and peripheralsIt also involves checking of component interactions and HW/SW functionalityVery long test times required

System Testing


Field TestingNecessary for commissioning and fault-finding the system as a whole in a field-service environmentBoth analog and digital test equipment is needed, issues of– Portability– Ease of use– Range of functions


Testing Costs are Composed of:Test equipment costs– Analog & digital signal and measuring instrumentation– Test head (pin electronics, drivers and cables)– Test controller (computer & storage)

Test development costs– Test planning, test program development and

debuggingTesting-time costs– time using the equipment to support testing

Test personnel costs– training– working time


Types of ATEIC Device ATE– Memory, Logic, Mixed-signal, Analog– Environmental Test - Burn-In

Board-Level ATE– Bare-Board Testers (Assembly Fault Testers)– Manufacturing Defects Analyzers– In-circuit Testers– Functional Board Testers– Combinational Board Testers

Systems Testers Field Service Testers


Cost of Manufacturing Testing in 2000AD0.5-1.0GHz, analog instruments, 1,024 digital pins: ATE purchase price= $1.2M + 1,024 x $3,000 = $4.272M

Running cost (five-year linear depreciation)= Depreciation + Maintenance + Operation= $0.854M + $0.085M + $0.5M= $1.439M/year

Test cost (24 hour ATE operation)= $1.439M/(365 x 24 x 3,600)= 4.5 cents/second


Tremendous Cost PressureThe price to performance ratio of semiconductors continues to decline– $ per MIP or $ per bit follow Moore’s Law

Test equipment cost increases– Tester cost increase 10 X in 30 years– Prober cost increase 20 X in 30 years

Test costs don’t scale with geometry– We must test all the individual parts– We must test them more thoroughly

And the parts get more complicated!And the parts get more complicated!


Summary – Types of IC Testing

Characterization testing vs. Production testingProduction testing: Wafer probe vs. Packaged device testingProduction testing for packaged devices:– Contact test– Burn-in– Functional testing– DC & AC parametric testing


Cost Of Testing - The Rule of Tens

1000

100

10

1

0.5

5.050

500

ICTest

CostPer

Fault(Dollars)

BoardTest

SystemTest

WarrantyRepair


In-Field Failures are Common and Costly

Xbox:16.4% failure rateAdditional warranty and refund will cost Microsoft $1.15B ($86 per $300-item)More than financial cost: reputation and market lossNon-trivial failure rate– 15% in average

http://arstechnica.com/news.ars/post/20080214-xbox-360-failure-rates-worse-than-most-consumer-electornics.html


The Testing ProblemsQ1: Which faults to target?– Fault Modeling

Q2: How is test derived?– Manually– Automatic Test Pattern Generation (ATPG)

Q3: How is test quality measured?– Fault coverage vs. product quality – Fault simulation

Q4: How are tests applied?– Test Engineering, Test programming– Automatic test equipment (ATE)– Wafer probe


The Testing Problems (Cont’d)

Q5: How to make sure high quality test can be derived and applied?– Design for testability– Built-in self-test

Q6: How to identify the source of errors, if any?– Fault Diagnosis

Documents

01 Test Overview 2pp