08rr410408 Advanced Computer Architecture

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Code No: RR410408 Set No. 1

IV B.Tech I Semester Supplimentary Examinations, February 2008ADVANCED COMPUTER ARCHITECTURE

( Common to Electronics & Communication Engineering and Electronics &Computer Engineering)

Time: 3 hours Max Marks: 80Answer any FIVE Questions

All Questions carry equal marks

1. What is meant by parallelism in uniprocessor systems? Identify the various mech-anisms that have been developed for this purpose and describe them. [16]

2. (a) What is the utility of a reservation table? Taking a suitable unifunctionpipeline as an example, draw the reservation table and its state diagram.

(b) What are reconfigurable pipelines? Explain the benefit of these pipelines withthe help of a suitable example. [8+8]

3. (a) Discuss the issues involved for Inter PE Communication in array processors.

(b) What is a Multistage Network? Describe different types of multistage network.[8+8]

4. (a) Describe Merge - Sorting in M(4,4) sorting algorithm using an example.

(b) Explain the advantages of using shuffle interconnection for the implementationof the polynomial evaluation algorithm, as compared with the use of the Illiacmesh network for the same purpose. [8+8]

5. (a) With a diagram explain the construction of 42X32 Delta network.

(b) Compare and contrast the performance of interconnection networks. [10+6]

6. (a) List the major characteristics, advantages and shortcomings of three types ofmultiprocessor operating systems.

(b) List the four main sources of performance degradation of the dynamic coher-

ence check algorithm. [12+4]

7. (a) Describe data flow design alternatives.

(b) Explain the organization of the EDDY data flow machine. [8+8]

8. Write short notes on

(a) Vector instruction in cyber-205.

(b) Input output subsystem configuration of cyber-205. [8+8]

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1. Explain different parallel processing mechanisms that are possible in uniprocessorcomputers. [16]

2. (a) What are pipeline hazards? What are the causes of pipeline hazards? Describebriefly the hazard detection and resolution of hazards in pipelines.

(b) What are the various classes of data-dependant hazards? Describe the hazardsand their removal. [8+8]

3. Design a data routing Network for an SIMD Array processor with 256 P Es. Drawan interconnection Barrel shifting network showing all directly wired connectionsamong the 256 P Es and calculate the minimum number of routing steps from anyP EI to any otherP EI+k for the arbitrary distance 1 k 255 . [16]

4. (a) Describe any two associative searching algorithms.(b) Explain the architecture of STARAN associative processor. [8+8]

5. (a) Give the computer module of a nonhierarchical loosely coupled multiprocessorsystem.

(b) Give the various components of the Kmap in Cm*, architecture and explainthe message transfer mechanism between modules. [10+6]

6. (a) Explain software requirements for multiprocessors.

(b) What is cache coherence? Describe method to avoid this problem. [8+8]

7. (a) Describe the properties of data flow languages.

(b) Draw a data flow graph to represent z = N!. [8+8]

8. (a) Discuss about a simple queuing structure with a single processor having interarrival time and service times.

(b) Discuss in detail the performance of M/M/n queuing structure. [8+8]

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1. (a) Compare and contrast RAM, SAM and DASD.

(b) Explain different addressing schemes for main memory. [8+8]

2. (a) With the help of neat block diagram explain the concept of Linear pipe line,and how it differs with non linear pipe line.

(b) Design a Linear pipe line for a Floating Point Adder. [8+8]

3. (a) With an example illustrate the mechanism of data routing in an array proces-sor.

(b) List down some applications of an array processor. [10+6]

4. (a) Describe various associative search operations.

(b) Describe data routing, comparison and interchange operations performed inthe M(4,2) sorting algorithm with an example. [8+8]

5. (a) Differentiate between buffered and unbuffered 2x2 switches. Give their appli-cations.

(b) Describe a multiport memory without fixed priority assignment. [8+8]

6. (a) What are the two resource allocation decisions that are made in multiprocess-ing systems?

(b) Explain briefly the two basic kinds of processor scheduling in multiprocessors.

(c) With the help of a diagram, explain states of a process and their state transi-tions. [4+4+8]

7. (a) Describe the instruction execution process in a data flow computer for com-putation of a = (b+1)*(b-c) .

(b) Describe VLSI matrix multiplication. [8+8]

8. (a) What are the fundamental classes of performance measures? Explain in detail

(b) Discuss in detail the performance of M/M/1 queuing structure. [8+8]

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1. (a) Explain Flynns computer classification in detail with suitable block diagrams.

(b) Differentiate between WORD-Slice processing and bit-slice processing.

(c) A Computer system can be characterized by T(C) =< KK, D D, WW > What are these six entities ? [6+6+4]

2. (a) What are pipeline hazards? What are the causes of pipeline hazards? Describebriefly the hazard detection and resolution of hazards in pipelines.

(b) What are the various classes of data-dependant hazards? Describe the hazardsand their removal. [8+8]

3. Design a data routing Network for an SIMD Array processor with 256 P Es. Drawan interconnection Barrel shifting network showing all directly wired connections

among the 256 P E

s and calculate the minimum number of routing steps from anyP EI to any otherP EI+k for the arbitrary distance 1 k 255 . [16]

4. (a) Discuss the steps involved in M(j,2) sorting algorithm.

(b) Describe Bit parallel Associative memory organization with suitable diagram.[8+8]

5. Explain various algorithms for Bus arbitration in multiprocessor organization.[16]

6. (a) Describe with a suitable diagram , the dynamic coherence check configurationto avoid cache coherence.

(b) What are problems that occur while multiple processor are shared?

(c) Gives the assumption usually made regarding regarding sections. [8+4+4]

7. (a) Compare Control flow computers against Data flow computers.

(b) Explain with an example, how an instruction is executed in a data flow com-puter. [8+8]

8. (a) Give the features of Hydra operating system.

(b) Demonstrate the effect of memory contention on the performance of C.mmp.[8+8]

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08rr410408 Advanced Computer Architecture