8
1 States report for readout system 1. PHENIX readout system overview 2. High speed data link 3. Digital pilot ASIC 4. Schedule Hiroyuki Kano @RI KEN

1 States report for readout system 1.PHENIX readout system overview 2.High speed data link 3.Digital pilot ASIC 4.Schedule Hiroyuki Kano @RIKEN

Embed Size (px)

Citation preview

Page 1: 1 States report for readout system 1.PHENIX readout system overview 2.High speed data link 3.Digital pilot ASIC 4.Schedule Hiroyuki Kano @RIKEN

1

States report for readout system

1. PHENIX readout system overview

2. High speed data link

3. Digital pilot ASIC

4. Schedule

Hiroyuki Kano @RIKEN

Page 2: 1 States report for readout system 1.PHENIX readout system overview 2.High speed data link 3.Digital pilot ASIC 4.Schedule Hiroyuki Kano @RIKEN

2

Pseudo FEMPilot ModuleXC2VPxx

New digital pilot ASIC

0.8Gbps => 1.6Gbps data link  (Global Optical Link)

Readout chip

4x bus

GOL

Digital pilot ASIC

Tx

Tx

Integrated

de-serializer

Detector

1.6Gbps optical linkWhat we have to test

PHENIX readout system

Page 3: 1 States report for readout system 1.PHENIX readout system overview 2.High speed data link 3.Digital pilot ASIC 4.Schedule Hiroyuki Kano @RIKEN

3

GOL high speed mode

Ready

Optical receiverPseudo FEM

Ready

Optical link

We will start to measure the error rate of GOL 1.6Gbps mode with this setup.

GOL test board

14 Sep. Ready

Page 4: 1 States report for readout system 1.PHENIX readout system overview 2.High speed data link 3.Digital pilot ASIC 4.Schedule Hiroyuki Kano @RIKEN

4

High speed receiver for GOL

VertexIIpro

link cableXilinx VertexIIpro can receive up to 3.12Gbps serial data stream.

Now I am developing the protocol for GOL 1.6Gbps mode.

Error LED

Pseudo FEM

Normal operation

Error detected (test)

States LED

3.12Gbps link test => OK

Page 5: 1 States report for readout system 1.PHENIX readout system overview 2.High speed data link 3.Digital pilot ASIC 4.Schedule Hiroyuki Kano @RIKEN

5

States of new pilot ASIC

• ASIC wafer fabrication was completed and is under dicing at French company. It may be delivered in any moment.

• ASIC test board design will be finished in few weeks.

• Packaging for ASIC chip is ready by FUJITSU. Just need chip! (Ask Hiroaki)

• All equipment for test setup are in our hand.

Page 6: 1 States report for readout system 1.PHENIX readout system overview 2.High speed data link 3.Digital pilot ASIC 4.Schedule Hiroyuki Kano @RIKEN

6

Chip packaging

• Chip will be packaged by Fujitsu IMT.

• We are ready to packaging and just waiting chip.

Netlist (chip-package) Pin assign table

Page 7: 1 States report for readout system 1.PHENIX readout system overview 2.High speed data link 3.Digital pilot ASIC 4.Schedule Hiroyuki Kano @RIKEN

7

Test setup

• We will finish to design ASIC test board in this week.

• Test setup is ready except ASIC and test board (early Oct.).

PPG50 TOMPPG50 TOM

FIFO moduleASIC test board

Pulse generator

PC

Data checking

Page 8: 1 States report for readout system 1.PHENIX readout system overview 2.High speed data link 3.Digital pilot ASIC 4.Schedule Hiroyuki Kano @RIKEN

8

Schedule

Data link

ASIC

Pilot module

10 11 12 1 2

Board fabrication

ASIC board test

board fabrication done

Board developing

System test

Board design completion

10/79/7

9/14

Protocol design

Long term test