30
100+ GHz Transistor Electronics: Present and Projected Capabilities [email protected] 805-893-3244, 805-893-5705 fax 2010 IEEE International Topical Meeting on Microwave Photonics, October 5-6, 2010, Montreal Mark Rodwell University of California, Santa Barbara

100+ GHz Transistor Electronics: Present and Projected

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Page 1: 100+ GHz Transistor Electronics: Present and Projected

100+ GHz Transistor Electronics: Present and Projected Capabilities

[email protected] 805-893-3244, 805-893-5705 fax

2010 IEEE International Topical Meeting on Microwave Photonics, October 5-6, 2010, Montreal

Mark Rodwell University of California, Santa Barbara

Page 2: 100+ GHz Transistor Electronics: Present and Projected

THz Transistors

Page 3: 100+ GHz Transistor Electronics: Present and Projected

Why Build THz Transistors ?

THz amplifiers→ THz radios→ imaging, sensing, communications

precision analog design at microwave frequencies→ high-performance receivers

500 GHz digital logic→ fiber optics

Higher-Resolution Microwave ADCs, DACs, DDSs

Page 4: 100+ GHz Transistor Electronics: Present and Projected

Transistor figures of Merit / Cutoff Frequencies

H21=short-circuit current gain

gai

ns,

dB

MAG = maximum available power gain:impedance-matched

U= unilateral power gain:feedback nulled, impedance-matched

fmax

power-gaincutoff frequency

f

current-gaincutoff frequency

Page 5: 100+ GHz Transistor Electronics: Present and Projected

What Determines Digital Gate Delay ?

CV/I terms dominate

)./5.05.0(

)/5.05.05.0(

)/5.05.0)(/(

)66)(/(

LCfcbijebb

LCfcbicbxex

LCfcbicbxjeC

wirecbicbxjeCLfgate

VICCR

VICCR

VICCCqIkT

CCCCIVT

analog ICs have somewhat similar bandwidth considerations...

Page 6: 100+ GHz Transistor Electronics: Present and Projected

How to Make THz Transistors

Page 7: 100+ GHz Transistor Electronics: Present and Projected

High-Speed Transistor Design

AR contact /

Bulk and Contact Resistances

Depletion Layers

T

AC

v

T

2

2

max)(4

T

Vv

A

I applsat

Thermal Resistance

Fringing Capacitances

~/ LC finging~/ LC finging

LKW

L

LKR

thth

th

1ln

1

dominate rmscontact te

Page 8: 100+ GHz Transistor Electronics: Present and Projected

Frequency Limitsand Scaling Laws of (most) Electron Devices

width

lengthlog

length

power

thicknessarea /

length

width

4area

area/

thickness/area

thickness

2

limit-charge-space max,

T

I

R

R

C

sheetcontactbottom

contacttop

To double bandwidth, reduce thicknesses 2:1 Improve contacts 4:1reduce width 4:1, keep constant lengthincrease current density 4:1

topR

bottomR

PIN photodiode

Page 9: 100+ GHz Transistor Electronics: Present and Projected

FET parameter change

gate length decrease 2:1

current density (mA/mm), gm (mS/mm) increase 2:1

channel 2DEG electron density increase 2:1

gate-channel capacitance density increase 2:1

dielectric equivalent thickness decrease 2:1

channel thickness decrease 2:1

channel density of states increase 2:1

source & drain contact resistivities decrease 4:1

Changes required to double transistor bandwidth

GW widthgate

GL

HBT parameter change

emitter & collector junction widths decrease 4:1

current density (mA/mm2) increase 4:1

current density (mA/mm) constant

collector depletion thickness decrease 2:1

base thickness decrease 1.4:1

emitter & base contact resistivities decrease 4:1

eW

ELlength emitter

constant voltage, constant velocity scaling

nearly constant junction temperature → linewidths vary as (1 / bandwidth)2

fringing capacitance does not scale → linewidths scale as (1 / bandwidth )

Page 10: 100+ GHz Transistor Electronics: Present and Projected

Electron Plasma Resonance: Not a Dominant Limit

*2kinetic

1

nmqA

TL

T

AC

ntdisplaceme

m

scatteringL

Rf

2

1

2

1

frequency scattering

kinetic

bulk

mnmqA

TR

*2bulk

1

2

1

2/1

frequency relaxation dielectric

bulkntdisplaceme

RC

fdielectric

ntdisplacemekinetic

2/1

frequencyplasma

CLf plasma

THz 800 THz 7 THz 74319 cm/105.3

InGaAs-

n

319 cm/107

InGaAs-

pTHz 80 THz 12 THz 13

Page 11: 100+ GHz Transistor Electronics: Present and Projected

0

20

40

60

80

100

120

140

100 200 300 400 500 600 700

junctio

n t

em

pera

ture

ris

e,

Kelv

in

master-slave D-Flip-Flop clock frequency, GHz

substrate: cylindrical+spherical regions

substrate: planar region

package

total

Thermal Resistance Scaling : Transistor, Substrate, Package

2substrate

2/11ln

D

DT

K

P

DLK

P

W

L

LK

PT sub

InPEInPe

e

EInP

junctionnear

flowheat lcylindrica

eLr for

flow spherical

2/for

flowplanar

HBTDr

callylogarithmi

increases

variation

antinsignific

constant is if

lly quadratica increases

subT

.)(bandwidth

as scales

density,Power

h.1/bandwidt

as scale

lenghts Wiring

2

chipCu

chip

packageWK

PT

1

4

1

)/GHz 150( m 40clocksub

fT m

IC CML HBT-2000

Page 12: 100+ GHz Transistor Electronics: Present and Projected

0

20

40

60

80

100

120

140

100 200 300 400 500 600 700

junctio

n t

em

pera

ture

ris

e,

Kelv

in

master-slave D-Flip-Flop clock frequency, GHz

substrate: cylindrical+spherical regions

substrate: planar region

package

total

Thermal Resistance Scaling : Transistor, Substrate, Package

2substrate

2/11ln

D

DT

K

P

DLK

P

W

L

LK

PT sub

InPEInPe

e

EInP

junctionnear

flowheat lcylindrica

eLr for

flow spherical

2/for

flowplanar

HBTDr

callylogarithmi

increases

variation

antinsignific

constant is if

lly quadratica increases

subT

.)(bandwidth

as scales

density,Power

h.1/bandwidt

as scale

lenghts Wiring

2

chipCu

chip

packageWK

PT

1

4

1

)/GHz 150( m 40clocksub

fT m

IC CML HBT-2000Probable best solution:

Thermal Vias ~500 nm below InP subcollector

...over full active IC area.

Page 13: 100+ GHz Transistor Electronics: Present and Projected

BipolarTransistors

Page 14: 100+ GHz Transistor Electronics: Present and Projected

256 nm InP HBT

0

10

20

30

109

1010

1011

1012

10

9

10

10

10

11

10

12

dB

Hz

f = 560 GHz

fmax

= 560 GHz

U

H21

0

2

4

6

8

10

0 1 2 3 4 5

mA

/mm

2

Vce

0

10

20

30

40

109

1010

1011

1012

dB

Hz

UH21

f = 424 GHz

fmax

= 780 GHz

0

5

10

15

20

0 1 2 3 4V

ce

mA

/mm

2

150 nm thick collector

70 nm thick collector340 GHz VCO

340 GHz dynamic frequency divider

Vout

VEE VBB

Vtune

Vout

VEE VBB

Vtune

324 GHz amplifier

Z. Griffith

J. Hacker, TSCIMS 2010

Z. Griffith

E. Lind

M. Seo, UCSB/TSCIMS 2010

M. Seo, UCSB/TSC

204 GHz staticfrequency divider

Z. Griffith, TSCCSIC 2010:to be presented

0

10

20

30

40

109

1010

1011

1012

dB

Hz

U

H21

ft = 660 GHz

fmax

= 218 GHz

0

10

20

30

0 1 2 3

mA

/mm

2

Vce

much better results in press ...

Page 15: 100+ GHz Transistor Electronics: Present and Projected

InP Bipolar Transistor Scaling Roadmap

emitter 512 256 128 64 32 nm width

16 8 4 2 1 mm2 access

base 300 175 120 60 30 nm contact width,

20 10 5 2.5 1.25 mm2 contact

collector 150 106 75 53 37.5 nm thick,

4.5 9 18 36 72 mA/mm2 current density

4.9 4 3.3 2.75 2-2.5 V, breakdown

f 370 520 730 1000 1400 GHz

fmax 490 850 1300 2000 2800 GHz

power amplifiers 245 430 660 1000 1400 GHz

digital 2:1 divider 150 240 330 480 660 GHz

eW

bcWcTbT

Page 16: 100+ GHz Transistor Electronics: Present and Projected

Fabrication Process for 128 nm & 64 nm InP HBTs

Page 17: 100+ GHz Transistor Electronics: Present and Projected

Initial Results: Refractory-Contact HBT ProcessChart 17

0

5

10

15

20

25

30

109

1010

1011

1012

Gain

(d

B)

freq (Hz)

ft = 430 GHz

fmax

= 800 GHz

U

H21

Aje = 0.27mm x 3.5mm

0

5

10

15

20

25

30

109

1010

1011

1012

Gain

(d

B)

Freq (Hz)

ft = 370 GHz

fmax

= 700 GHz

U

H21

Aje = 0.11 mm x 3.5 mm

Need to add E-beam defined base, best base contact technology

110 nm emitter width 270 nm emitter width

Page 18: 100+ GHz Transistor Electronics: Present and Projected

InP DHBTs: August 2010

)(

),/(

),/(

),/(

hence ,

:digital

gain, associated ,F

:amplifiers noise low

mW/

gain, associated PAE,

:amplifierspower

)11(

2/) (

alone or

min

1

max

max

max

max

cb

cbb

cex

ccb

clock

ττ

VIR

VIR

IVC

f

m

ff

ff

ff

ff

m

:metrics better much

:metrics popular

0

200

400

600

800

1000

0 200 400 600 800 1000

Teledyne DHBT

UIUC DHBT

NTT DBHT

ETHZ DHBT

UIUC SHBT

UCSB DHBT

NGST DHBT

HRL DHBT

IBM SiGe

Vitesse DHBT

f ma

x (

GH

z)

ft (GHz)

600

GHz

500

GHz maxff

Updated Aug 2010

800

GHz

900

GHz

700

GHz

400

GHz

250 nm

600nm

350 nm

250 nm

200 nm

110 nm

Page 19: 100+ GHz Transistor Electronics: Present and Projected

670 GHz Transceiver Simulations in 128 nm InP HBT

transmitter exciter

receiver

128nm 64nm 32nm

(a) (b) (c)

-8 -6 -4 -2 0 2 4 6 8-10 10

-5

0

5

10

15

-10

20

Pin

Po

ut

Ga

in

-14 -12 -10 -8 -6 -4 -2 0 2 4-16 6

-5

0

5

10

15

-10

20

Pin

Po

ut

Ga

in

-10 -8 -6 -4 -2 0 2 4 6-12 8

-5

0

5

10

15

-10

20

Pin

Po

ut

Ga

in

LNA: 9.5 dB Fmin at 670 GHz

640 660 680 700620 720

10

20

0

30

SP.freq, GHz

dB

(S(2

,1))

freq, GHz

nf(

2)

1.00 1.02 1.04 1.060.98 1.08

10

20

30

0

35

SP.freq, THz

dB

(S(2

,1))

freq, THz

nf(

2)

820 840 860 880800 900

10

20

30

0

35

SP.freq, GHz

dB

(S(2

,1))

freq, GHz

nf(

2)

128nm 64nm 32nm

(a) (b) (c)

3-layer thin-film THz interconnects

thick-substrate--> high-Q TMIC

thin -> high-density digital

Simulations @ 670 GHz (128 nm HBT)

PA: 9.1 dBm Pout at 670 GHz

VCO:

-50 dBc (1 Hz)

@ 100 Hz offset

at 620 GHz (phase 1)

-150

-100

-50

0

50

101

102

103

104

105

106

107

PL

L s

ing

le-s

ide

ba

nd

ph

ase

no

ise

sp

ectr

al d

en

sity,

dB

c (

1 H

z)

offset from carrier, Hz

free-running

VCO

closed-loop

VCO noisemultiplied

reference noise

Total PLL

phase noise

-1.2

-1.15

-1.1

-1.05

-1

-0.95

-0.9

195 10-12

197.5 10-12

200 10-12

690 GHz Input

Vo

ut , V

ou

t_b

ar

time, seconds

-1.2

-1.15

-1.1

-1.05

-1

-0.95

-0.9

195 10-12

197.5 10-12

200 10-12

950 GHz Input

Vo

ut,

Vo

ut_

ba

r

time, seconds

Dynamic divider:

novel design,

simulates to 950 GHz

-10.00 -5.000 0.0000 5.000 -15.00 10.00

0

5

10

15

20

25

-5

30

LO Power

Nois

e F

igure

, C

onvers

ion G

ain

(dB

)

Mixer:

10.4 dB noise figure

11.9 dB gain

Page 20: 100+ GHz Transistor Electronics: Present and Projected

THz Field-Effect Transistors

(THz HEMTs)

Page 21: 100+ GHz Transistor Electronics: Present and Projected

laws in constant-voltage limit:

FET Scaling Laws

GW widthgate

GL

FET parameter change

gate length decrease 2:1

current density (mA/mm), gm (mS/mm) increase 2:1

channel 2DEG electron density increase 2:1

electron mass in transport direction constant

gate-channel capacitance density increase 2:1

dielectric equivalent thickness decrease 2:1

channel thickness decrease 2:1

channel density of states increase 2:1

source & drain contact resistivities decrease 4:1

Changes required to double device / circuit bandwidth.

Page 22: 100+ GHz Transistor Electronics: Present and Projected

HEMT/MOSFET Scaling: Four Major Challenges

gate dielectric:need thinner barriers→ tunneling leakage

contact regions:need reduced access resistivity

channel:need higher charge densityyet keep high carrier velocity

channel:need thinner layers

Page 23: 100+ GHz Transistor Electronics: Present and Projected

THz FET Scaling Roadmap

Gate length nm 35 25 18 13 9

Gate barrier EOT nm 0.83 0.58 0.41 0.29 0.21

well thickness nm 5.7 4.0 2.8 2.0 1.4

S/D resistance mm 150 100 74 53 37

effective mass *m0 0.05 0.05 0.08 0.08 0.08

# band minima 1 1 2 3 3

f GHz 700 770 1100 1600 2300

fmax GHz 810 930 1400 2000 2900

fdivider GHz 150 220 300 430 580

Id /Wg mA/mm 0.54 0.69 0.95 1.4 1.8@ 200 mV overdrive

high-K gate dielectrics source / drain regrowth G-L transport

source-coupled logic

?

Page 24: 100+ GHz Transistor Electronics: Present and Projected

III-V MOSFETs with Source/Drain Regrowth

27 nm InGaAs MOSFET

Page 25: 100+ GHz Transistor Electronics: Present and Projected

RegardingMixed-Signal ICs

&Waveform Generation

Page 26: 100+ GHz Transistor Electronics: Present and Projected

Clock Timing Jitter in ADCs and DACs

Timing jitter is quantitatively specifiedby the single-sideband phase noise spectral density L(f).

IC oscillator phase noise varies as ~1/f2 or ~1/f3 near carrier

Impact on ADCs and DACs: imposition of 1/fn sidebands on signal of relative amplitude L(f)...not creation of a broadband noise floor.

Dynamic range of electronic DACs & ADCs is limited by factors other than the phase noise of the sampling clock

Page 27: 100+ GHz Transistor Electronics: Present and Projected

Why ADC Resolution Decreases With Sample Rate

dynamic hysteresis

Dynamic Range Determined by Circuit Settling Time vs. Clock Period

1bits#

latchsamplef

metastability

IC time constants→ Resolution decreases at high sample rates

Page 28: 100+ GHz Transistor Electronics: Present and Projected

Fast IC Waveform Generation: General Prospects

Waveform generator → fast digital memory & DAC

Parallel digital memory and 200 Gb/s MUX is feasiblecost limits: power & system complexity vs. # bits, GS/s

Performance limit: speed vs. resolution of DACfaster technologies → increased sample rates

Feasible ADC resolution: 12 SNR bits @ 4 GS/s feasible using 500 nm (400GHz) InP HBT. Feasible sample rate will scale with technology speed..

Page 29: 100+ GHz Transistor Electronics: Present and Projected

THz Transistors&

Mixed-Signal ICs

Page 30: 100+ GHz Transistor Electronics: Present and Projected

Few-THz Transistors

Scaling limits: contact resistivities, device and IC thermal resistances.

Few-THz InP Bipolar Transistors: can it be done ?

62 nm (1 THz f , 1.5 THz fmax ) scaling generation is feasible.

700 GHz amplifiers, 450 GHz digital logic

Is the 32 nm (1 THz amplifiers) generation feasible ?

Few-THz InP Field-Effect Transistors: can it be done?

challenges are gate barrier, vertical scaling,source/drain access resistance, channel density of states.

2DEG carrier concentrations must increase.

S/D regrowth offers a path to lower access resistance.

Solutions needed for gate barrier: possibly high-k (MOSFET)

Implications: 1 THz radio ICs, ~200-400 GHz digital ICs, 20 GHz ADCs/DACs