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Computer Organization

EEC-213

Computer Organization

Electrical and Computer Engineering

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Grading

Homework 10% Midterm Exam 10% Oral Exam 20% Final Exam 60%

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Honor Code

You are encouraged to discuss homework problems with other students and/or obtain the assistance of the instructor. Nevertheless, homework submissions should be

the work of you and your partner.

Exams are closed book, closed notes, no use of calculators, and the normal honor code applies to all exams.

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Textbooks

Computer Organization, 5th ed. Carl Hamacher, et al., ISBN 0-07-232086-9 2002

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Questions?

Basic structure of Computers

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Processor

Computer Functional Units

Memory

Arithmetic& Logic

Control

I/O

Input

Output

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Course Organization

Computer Structure (Ch 1) Instruction Sets & Addressing Modes (Ch 2) Example Computer: Motorola 68000 (Ch 3) Control Unit Design (Ch 7)

Computer Arithmetic (Ch 6) Memory (Ch 5) Input/Output (Ch 4) Pipelining (Ch 8)

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Computer Information (Binary)

(Machine) Instructions (Machine Language) Programs

Data 2's complement BCD ASCII

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Output Display Printer Speakers

I/O

Input Keyboard Mouse Microphone Camera Scanner

Serial Communications Network Modem

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Memory

Primary Random Access

Memory (RAM) Read Only

Memory (ROM)

Organization Word Address Read/Write

Secondary Magnetic

Disks Tape

Optical Disks

Hierarchy Cache Main Virtual

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ALU

Arithmetic Addition Subtraction Multiplication Division Comparison

Logic AND OR NOT XOR

Registers Store Shift

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Control Unit

Coordinates/Directs other Units

Computer Operation Input

Program/Data stored in Memory Processing

Information fetched into RegistersProcessed by ALU

Output

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Computer Instructions

Assembly Language

MOVE NUM1,R1

MOVE #1,R2

ADD #1,R1

ADD R1,R2

Register Transfer Notation

R1 [NUM1]

R2 1

R1 1 + [R1]

R2 [R1] + [R2]

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Processor and Memory

ALUIR

MAR

MEM

PC

MDR

R0

R1

.

.

.

Rn-1

Control

Processor

MAR - Memory Address Register

MDR - Memory Data Register

PC - Program Counter

IR - Instruction Register

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Example Instruction

Fetch MAR [PC] PC [PC] + 1 MDR [MEM(MAR)] IR [MDR]

Execute MAR NUM1 MDR [MEM(MAR)] R1 [MDR]

MOVE NUM1,R1

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Another Example

Fetch MAR [PC] PC [PC] + 1 MDR [MEM(MAR)] IR [MDR]

Execute R1 1 + R1

ADD #1,R1

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Single-Bus Structure

•The computer parts must be connected in some way

•A group of lines that serves as a connecting path for several devices is called bus

•Only one transfer at a time can occurs between 2 units

•Devices includes a buffer register to hold information during transfer

Memory ProcessorInput Output

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Single-Bus Architecture (HW1)

A B

RALU

MDR

MAR

MEM

BUS A

Y

Z

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System Software

Compiler High-level Language Machine Language

Assembler Assembly Language Machine Language

Text Editor Keyboard Input File

Operating System Control Sharing & Interaction Assign & Manage Resources

Memory Disk Space

Handle I/O

Memory Performance Programs and data are stored in memory Instruction are fetched one by one over the bus to the processor, and a

copy is placed in the cache. When a data is executed by an instruction a copy is placed in the cache Later if the same instruction or data item is needed a second time , it’s

red directly from the cache. Execution of instruction and data from the cache is faster than the main

memory

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MainMemory

ProcessorCacheMemory

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Processor Clock

Period (P)

Rate (R)

CLK

R = 1/P

1 GHz = 1/1ns

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Performance Equation

Processor Execution Time (T) Number of Machine Language Instructions (N) Average Steps per Machine Instruction (S) Clock Rate (R)

Performance of a processor of 2.4 GHz & a processor of 2.8 GHz of another type.

T N S

R

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Pipelining

F1 E1

I1

F2 E2

I2

F3 E3

I3

Sequential Execution

F1 E1I1

F2 E2I2

F3 E3I3

Pipelined Execution

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Parallel Processing

Parallel Execution Superscalar (execution of several instructions in every clock cycle)

Multiprocessors Shared-Memory

Multicomputers Message-Passing

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CISC vs RISC

Complex Instruction Set Computers (CISC) Smaller N Larger S

Reduced Instruction Set Computers (RISC) Larger N Smaller S Easier to Pipeline

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History

First Generation (miliseconds) von Neumann (stored program) Vacuum Tubes Magnetic Core Memory Teletypes/Magnetic Tapes

Second Generation (microseconds) Transistor High-level Languages (C++, Pascal, Fortran)

Compilers (translate HHL to M/C instruction)

I/O Processors

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History

Third Generation Integrated Circuits Microprogramming Parallelism/Pipelining Operating Systems (sharing) Cache/VM

Fourth Generation (nanoseconds) VLSI (Single Chip Microprocessor) Personal Computers Networks

Problem 1-3

Load A,R0 Load B,R1 Add R0,R1 Store R1,C

(b) Yes; Move B,C Add A,C

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Review

Binary Hex 2's-complement Overflow