of 44 /44
1 Basic Computer Organization & Design Computer Organization Computer Architectures Lab BASIC COMPUTER ORGANIZATION AND DESIGN • Instruction Codes • Computer Registers • Computer Instructions • Timing and Control • Instruction Cycle • Memory Reference Instructions • Input-Output and Interrupt • Complete Computer Description • Design of Basic Computer • Design of Accumulator Logic

13697_Ch5_ Basic Computer Organization and Design

Embed Size (px)

Text of 13697_Ch5_ Basic Computer Organization and Design

1 Basic Computer Organization & DesignComputer Organization Computer Architectures LabBASIC COMPUTER ORGANIZATION AND DESIGN Instruction Codes Computer Registers Computer Instructions Timing and ControI Instruction CycIe Memory Reference Instructions Input-Output and Interrupt CompIete Computer Description Design of Basic Computer Design of AccumuIator Logic Basic Computer Organization & DesignComputer Organization Computer Architectures LabINTRODUCTIONW Every different processor type has its own design (different registers, buses, microoperations, machine instructions, etc)W Modern processor is a very compIex deviceW It contains Many registers MuItipIe arithmetic units, for both integer and fIoating point caIcuIations The abiIity to pipeIine severaI consecutive instructions to speed execution Etc.W However, to understand how processors work, we wiII start with a simpIified processor modeIW This is simiIar to what reaI processors were Iike ~ years agoW M. Morris Mano introduces a simpIe processor modeI he caIIs the Basic ComputerW e wiII use this to introduce processor organization and the reIationship of the RTL modeI to the higher IeveI computer processor Basic Computer Organization & DesignComputer Organization Computer Architectures LabTHE BASIC COMPUTERW The Basic Computer has two components, a processor and memoryW The memory has 4096 words in it 4096 = 1, so it takes 1 bits to seIect a word in memoryW Each word is 16 bits IongCPU RAM04090 14 Basic Computer Organization & DesignComputer Organization Computer Architectures LabINSTRUCTIONSInstruction codesW Program A sequence of (machine) instructions W (Machine) Instruction A group of bits that teII the computer to perform a specific operation(a sequence of micro-operation) W The instructions of a program, aIong with any needed data are stored in memoryW The CPU reads the next instruction from memoryW It is pIaced in an Instruction Register (IR)W ControI circuitry in controI unit then transIates the instruction into the sequence of microoperations necessary to impIement it Basic Computer Organization & DesignComputer Organization Computer Architectures LabINSTRUCTION FORMATInstruction codesW A computer instruction is often divided into two parts An opcode (Operation Code) that specifies the operation for that instruction An address that specifies the registers and/or Iocations in memory to use for that operationW In the Basic Computer, since the memory contains 4096 (=

1) words, we needs 1 bit to specify which memory address this instruction wiII use W In the Basic Computer, bit 1 of the instruction specifies the addressing mode (0: direct addressing, 1: indirect addressing)W Since the memory words, and hence the instructions, are 16 bits Iong, that Ieaves bits for the instruction's opcodeOpcode AddressInstruction Format1 14 1 0I11Addressing mode6 Basic Computer Organization & DesignComputer Organization Computer Architectures LabADDRESSING MODESInstruction codesW The address fieId of an instruction can represent either Direct address: the address in memory of the data to use (the address of the operand), or Indirect address: the address in memory of the address in memory of the data to use W Effective Address (EA) The address, that can be directIy used without modification to access an operand for a computation-type instruction, or as the target address for a branch-type instruction0 ADD 4

Operand41 ADD 00 10 00Operand 10+AC+ACDirect addressing Indirect addressing Basic Computer Organization & DesignComputer Organization Computer Architectures LabPROCESSOR REGISTERSInstruction codesW A processor has many registers to hoId instructions, addresses, data, etcW The processor has a register, the !rogram Counter (PC) that hoIds the memory address of the next instruction to get Since the memory in the Basic Computer onIy has 4096 Iocations, the PC onIy needs 1 bitsW In a direct or indirect addressing, the processor needs to keep track of what Iocations in memory it is addressing: The Address Register (AR) is used for this The AR is a 1 bit register in the Basic ComputerW hen an operand is found, using either direct or indirect addressing, it is pIaced in the Data Register (DR). The processor then uses this vaIue as data for its operationW The Basic Computer has a singIe general purpose register the Accumulator (AC) Basic Computer Organization & DesignComputer Organization Computer Architectures LabPROCESSOR REGISTERSInstruction codesW The significance of a generaI purpose register is that it can be referred to in instructions e.g. Ioad AC with the contents of a specific memory Iocation; store the contents of AC into a specified memory IocationW Often a processor wiII need a register to store intermediate resuIts or other temporary data; in the Basic Computer this is the %emporary Register (TR)W The Basic Computer uses a very simpIe modeI of input/output (I/O) operations Input devices are considered to send bits of character data to the processor The processor can send bits of character data to output devicesW The Input Register (INPR) hoIds an bit character gotten from an input deviceW The Output Register (OUTR) hoIds an bit character to be send to an output device9 Basic Computer Organization & DesignComputer Organization Computer Architectures LabBASIC COMPUTER REGISTERSList of BC RegistersDR 16 Data Register HoIds memory operandAR 1 Address Register HoIds address for memoryAC 16 AccumuIator Processor registerIR 16 Instruction Register HoIds instruction codePC 1 Program Counter HoIds address of instructionTR 16 Temporary Register HoIds temporary dataINPR Input Register HoIds input characterOUTR Output Register HoIds output characterRegistersRegisters in the Basic Computer11 0PC1 0IR1 0TR 0OUTR1 0DR1 0AC11 0ARINPR0 Memory4096 x 16CPU10 Basic Computer Organization & DesignComputer Organization Computer Architectures LabCOMMON BUS SYSTEMRegistersW The registers in the Basic Computer are connected using a busW This gives a savings in circuitry over compIete connections between registers11 Basic Computer Organization & DesignComputer Organization Computer Architectures LabCOMMON BUS SYSTEMRegistersSS1S0BusMemory unit4096 x 16LD INR CLRAddressRead riteARLD INR CLRPCLD INR CLRDRLD INR CLRAC ALUEINPRIRLDLD INR CLRTROUTRLDCIock16-bit common bus

1

4

61 Basic Computer Organization & DesignComputer Organization Computer Architectures LabCOMMON BUS SYSTEMRegistersARPCDRL I CL I CL I CACL I CALUEIRLTRL I COUTR LDINPRMemory4096 x 16AddressReadrite16-bit Common Bus 1 4 6S0 S1 S

1 Basic Computer Organization & DesignComputer Organization Computer Architectures LabCOMMON BUS SYSTEMRegistersW Three controI Iines, S

, S1, and S0 controI which register the bus seIects as its inputW Either one of the registers wiII have its Ioad signaI activated, or the memory wiII have its read signaI activated iII determine where the data from the bus gets IoadedW The 1-bit registers, AR and PC, have 0's Ioaded onto the bus in the high order 4 bit positionsW hen the -bit register OUTR is Ioaded from the bus, the data comes from the Iow order bits on the bus0 0 0 x0 0 1 AR0 1 0 PC0 1 1 DR1 0 0 AC1 0 1 IR1 1 0 TR1 1 1 MemoryS

S1 S0 Register14 Basic Computer Organization & DesignComputer Organization Computer Architectures LabBASIC COMPUTER INSTRUCTIONSInstructionsW Basic Computer Instruction Format1 14 1 11 0I Opcode AddressMemory-Reference Instructions (OP-code = 000 ~ 110)Register-Reference Instructions (OP-code = 111, I = 0)Input-Output Instructions (OP-code =111, I = 1)1 1 11 0Register operation 0 1 1 11 1 11 0I/O operation1 1 1 11 Basic Computer Organization & DesignComputer Organization Computer Architectures LabBASIC COMPUTER INSTRUCTIONSHex CodeSymbol I = 0 I = 1 DescriptionAND 0xxx xxx AND memory word to ACADD 1xxx 9xxx Add memory word to ACLDA xxx Axxx Load AC from memorySTA xxx Bxxx Store content of AC into memoryBUN 4xxx Cxxx Branch unconditionaIIyBSA xxx Dxxx Branch and save return addressISZ 6xxx Exxx Increment and skip if zeroCLA 00 CIear ACCLE 400 CIear ECMA 00 CompIement ACCME 100 CompIement ECIR 00 CircuIate right AC and ECIL 040 CircuIate Ieft AC and EINC 00 Increment ACSPA 010 Skip next instr. if AC is positiveSNA 00 Skip next instr. if AC is negativeSZA 004 Skip next instr. if AC is zeroSZE 00 Skip next instr. if E is zeroHLT 001 HaIt computerINP F00 Input character to ACOUT F400 Output character from ACSKI F00 Skip on input fIagSKO F100 Skip on output fIagION F00 Interrupt onIOF F040 Interrupt offInstructions16 Basic Computer Organization & DesignComputer Organization Computer Architectures LabINSTRUCTION SET COMPLETENESSW Instruction TypesA computer shouId have a set of instructions so that the user can construct machine Ianguage programs to evaIuate any function that is known to be computabIe.FunctionaI Instructions- Arithmetic, Iogic, and shift instructions- ADD, CMA, INC, CIR, CIL, AND, CLATransfer Instructions- Data transfers between the main memory and the processor registers- LDA, STAControI Instructions- Program sequencing and controI- BUN, BSA, ISZInput/Output Instructions- Input and output- INP, OUTInstructions1 Basic Computer Organization & DesignComputer Organization Computer Architectures LabCONTROL UNITInstruction codesW ControI unit (CU) of a processor transIates from machine instructions to the controI signaIs for the microoperations that impIement themW ControI units are impIemented in one of two waysW Hardwired ControI CU is made up of sequentiaI and combinationaI circuits to generate the controI signaIsW icroprogrammed ControI A controI memory on the processor contains microprograms that activate the necessary controI signaIsW e wiII consider a hardwired impIementation of the controI unit for the Basic Computer1 Basic Computer Organization & DesignComputer Organization Computer Architectures LabTIMING AND CONTROLControI unit of Basic Computer%iming and controlInstruction register (IR)1 14 1 1 11 - 0 x decoder 6 4 1 0ID01 14 . . . . 1 04 x 16decoder4-bitsequencecounter(SC)Increment (INR)CIear (CLR)CIockOther inputsControIsignaIsDTT

10CombinationaIControIIogic19 Basic Computer Organization & DesignComputer Organization Computer Architectures LabINSTRUCTION CYCLEW In Basic Computer, a machine instruction is executed in the foIIowing cycIe:1. Fetch an instruction from memory. Decode the instruction. Read the effective address from memory if the instruction has an indirect address4. Execute the instructionW After an instruction is executed, the cycIe starts again at step 1, for the next instructionW ote: Every different processor has its own (different) instruction cycIe 0 Basic Computer Organization & DesignComputer Organization Computer Architectures LabFETCH and DECODE Fetch and Decode T0: AR PC (S0S1S

=010, T0=1)T1: IR M [AR], PC PC + 1 (S0S1S=111, T1=1)T: D0, . . . , D Decode IR(1-14), AR IR(0-11), I IR(1)S

S1S0Bus

MemoryunitAddressReadARLDPCINRIRLDCIock1

Common busT1T0Instruction Cycle1 Basic Computer Organization & DesignComputer Organization Computer Architectures LabDETERMINE THE TYPE OF INSTRUCTION= 0 (direct)Instrction CycleStartSC AR PCT0IR M[AR], PC PC + 1T1AR IR(0-11), I IR(1)Decode Opcode in IR(1-14),TD= 0 (Memory-reference) (Register or I/O) = 1I IExecuteregister-referenceinstructionSC 0Executeinput-outputinstructionSC 0M[AR] AR Nothing= 0 (register) (I/O) = 1 (indirect) = 1T T T TExecutememory-referenceinstructionSC 0T4 Basic Computer Organization & DesignComputer Organization Computer Architectures LabREGISTER REFERENCE INSTRUCTIONSr = D

[email protected]

=> Register Reference InstructionBi = IR(i) , i=0,1,,...,11- D

= 1, I = 0- Register Ref. Instr. is specified in b0 ~ b11 of IR- Execution starts with timing signaI T

Instruction CycleRegister Reference Instructions are identified whenr: SC 0CLA rB11: AC 0CLE rB10: E 0CMA rB9: AC AC'CME rB

: E E'CIR rB

: AC shr AC, AC(1) E, E AC(0)CIL rB6: AC shI AC, AC(0) E, E AC(1)INC rB

: AC AC + 1SPA rB4: if (AC(1) = 0) then (PC PC+1)SNA rB

: if (AC(1) = 1) then (PC PC+1)SZA rB

: if (AC = 0) then (PC PC+1)SZE rB1: if (E = 0) then (PC PC+1)HLT rB0: S 0 (S is a start-stop fIip-fIop) Basic Computer Organization & DesignComputer Organization Computer Architectures LabMEMORY REFERENCE INSTRUCTIONSAND to ACD0T4: DR M[AR] Read operandD0T

: AC AC DR, SC 0 AND with ACADD to ACD1T4: DR M[AR] Read operandD1T

: AC AC + DR, E Cout, SC 0 Add to AC and store carry in E- The effective address of the instruction is in AR and was pIaced there during timing signaI T

when I = 0, or during timing signaI T

when I = 1- Memory cycIe is assumed to be short enough to compIete in a CPU cycIe- The execution of MR instruction starts with T4R InstructionsSymboI OperationDecoder SymboIic DescriptionAND D0 AC AC M[AR]ADD D1 AC AC + M[AR], E CoutLDA D

AC M[AR]STA D

M[AR] ACBUN D4 PC ARBSA D

M[AR] PC, PC AR + 1ISZ D6 M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+14 Basic Computer Organization & DesignComputer Organization Computer Architectures LabMEMORY REFERENCE INSTRUCTIONSMemory, PC after execution10 BSA 1Next instructionSubroutine0PC = 1AR = 1161 BUN 1Memory, PC, AR at time T40 BSA 1Next instructionSubroutine011PC = 161 BUN 1Memory MemoryLDA: Load to ACD

T4: DR M[AR]D

T

: AC DR, SC 0STA: Store ACD

T4: M[AR] AC, SC 0BUN: Branch UnconditionaIIyD4T4: PC AR, SC 0BSA: Branch and Save Return AddressM[AR] PC, PC AR + 1 Basic Computer Organization & DesignComputer Organization Computer Architectures LabMEMORY REFERENCE INSTRUCTIONSR InstructionsBSA: D

T4: M[AR] PC, AR AR + 1D

T

: PC AR, SC 0ISZ: Increment and Skip-if-ZeroD6T4: DR M[AR]D6T

: DR DR + 1D6T4: M[AR] DR, if (DR = 0) then (PC PC + 1), SC 06 Basic Computer Organization & DesignComputer Organization Computer Architectures LabFLOCHART FOR MEMORY REFERENCE INSTRUCTIONSR InstructionsMemory-reference instructionDR M[AR] DR M[AR] DR M[AR] M[AR] ACSC 0AND ADD LDA STAAC AC DRSC 0AC AC + DRE CoutSC 0AC DRSC 0D T0 4 D T1 4 D T 4 D T 4D T0 D T1 D T PC ARSC 0M[AR] PCAR AR + 1DR M[AR]BUN BSA ISZD T4 4 D T 4 D T6 4DR DR + 1D T D T6 PC ARSC 0M[AR] DRIf (DR = 0)then (PC PC + 1)SC 0D T6 6

Basic Computer Organization & DesignComputer Organization Computer Architectures LabINPUT-OUTPUT AND INTERRUPTW Input-Output ConfigurationI!R Input register - bitsOU%R Output register - bitsFGI Input fIag - 1 bitFGO Output fIag - 1 bitIE Interrupt enabIe - 1 bit- The terminaI sends and receives seriaI information- The seriaI info. from the keyboard is shifted into INPR - The seriaI info. for the printer is stored in the OUTR- INPR and OUTR communicate with the terminaI seriaIIy and with the AC in paraIIeI.- The fIags are needed to synchronize the timing difference between I/O device and the computerA TerminaI with a keyboard and a PrinterI/O and InterruptInput-outputterminaISeriaIcommunicationinterfaceComputerregisters andfIip-fIopsPrinterKeyboardReceiverinterfaceTransmitterinterfaceFGO OUTRACINPR FGISeriaI Communications PathParaIIeI Communications Path Basic Computer Organization & DesignComputer Organization Computer Architectures LabPROGRAM CONTROLLED DATA TRANSFERIoop: If FGI = 1 goto IoopINPR new data, FGI 1Ioop: If FGO = 1 goto Ioopconsume OUTR, FGO 1-- CPU -- -- I/O Device --/* Input */ /* InitiaIIy FGI = 0 */Ioop: If FGI = 0 goto IoopAC INPR, FGI 0/* Output */ /* InitiaIIy FGO = 1 */Ioop: If FGO = 0 goto IoopOUTR AC, FGO 0I/O and InterruptStart InputFGI 0FGI=0AC INPRMoreCharacterENDStart OutputFGO 0FGO=0MoreCharacterENDOUTR ACAC DatayesnoyesnoFGI=0 FGO=1yesyesnono9 Basic Computer Organization & DesignComputer Organization Computer Architectures LabINPUT-OUTPUT INSTRUCTIONSD

IT

= pIR(i) = Bi, i = 6, ., 11p: SC 0 CIear SCINP pB11: AC(0-) INPR, FGI 0 Input char. to ACOUT pB10: OUTR AC(0-), FGO 0 Output char. from ACSKI pB9: if(FGI = 1) then (PC PC + 1) Skip on input fIagSKO pB

: if(FGO = 1) then (PC PC + 1) Skip on output fIagION pB

: IEN 1 Interrupt enabIe onIOF pB6: IEN 0 Interrupt enabIe off0 Basic Computer Organization & DesignComputer Organization Computer Architectures LabPROGRAM-CONTROLLED INPUT/OUTPUTW Program-controIIed I/O- Continuous CPU invoIvementI/O takes vaIuabIe CPU time- CPU sIowed down to I/O speed- SimpIe- Least hardwareI/O and InterruptInputLOOP, SKI DEVBUN LOOPINP DEVOutputLOOP, LDA DATALOP, SKO DEVBUN LOPOUT DEV1 Basic Computer Organization & DesignComputer Organization Computer Architectures LabINTERRUPT INITIATED INPUT/OUTPUT- Open communication onIy when some data has to be passed --> interrupt.- The I/O interface, instead of the CPU, monitors the I/O device. - hen the interface founds that the I/O device is ready for data transfer, it generates an interrupt request to the CPU- Upon detecting an interrupt, the CPU stops momentariIy the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing.* IEN (Interrupt-enabIe fIip-fIop)- can be set and cIeared by instructions- when cIeared, the computer cannot be interrupted Basic Computer Organization & DesignComputer Organization Computer Architectures LabFLOCHART FOR INTERRUPT CYCLER = Interrupt f/f- The interrupt cycIe is a H impIementation of a branchand save return address operation.- At the beginning of the next instruction cycIe, the instruction that is read from memory is in address 1.- At memory address 1, the programmer must store a branch instruction that sends the controI to an interrupt service routine- The instruction that returns the controI to the originaI program is "indirect BUN 0"I/O and InterruptStore return addressR =1 =0in Iocation 0M[0] PCBranch to Iocation 1PC 1IEN 0R 0Interrupt cycIe Instruction cycIeFetch and decodeinstructionsIENFGIFGOExecuteinstructionsR 1=1=1=1=0=0=0 Basic Computer Organization & DesignComputer Organization Computer Architectures LabREGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLERegister Transfer Statements for Interrupt CycIe- R F/F 1 if IEN (FGI + FGO)[email protected]@T

@[email protected]@T

@(IEN)(FGI + FGO): R 1- The fetch and decode phases of the instruction cycIemust be modified RepIace T0, T1, T

with R'T0, R'T1, R'T

- The interrupt cycIe :RT0: AR 0, TR PCRT1: M[AR] TR, PC 0RT

: PC PC + 1, IEN 0, R 0, SC 0After interrupt cycIe0 BUN 11001PC = 6

1 BUN 0Before interruptMainProgram110I/OProgram0 BUN 1100PC = 16

1 BUN 0MemoryMainProgram110I/OProgram6I/O and Interrupt4 Basic Computer Organization & DesignComputer Organization Computer Architectures LabFURTHER QUESTIONS ON INTERRUPTHow can the CPU recognize the device requesting an interrupt ?Since different devices are IikeIy to require different interrupt service routines, how can the CPU obtain the starting address of the appropriate routine in each case ?ShouId any device be aIIowed to interrupt the CPU whiIe another interrupt is being serviced ?How can the situation be handIed when two or more interrupt requests occur simuItaneousIy ?I/O and Interrupt Basic Computer Organization & DesignComputer Organization Computer Architectures LabCOMPLETE COMPUTER DESCRIPTIONFIowchart of OperationsDescription=1 (I/O) =0 (Register) =1(Indir) =0(Dir)startSC 0, IEN 0, R 0RAR PCR'T0IR M[AR], PC PC + 1R'T1AR IR(0~11), I IR(1)D0...D

Decode IR(1 ~ 14)R'T

AR 0, TR PCRT0M[AR] TR, PC 0RT1PC PC + 1, IEN 0R 0, SC 0RT

D

I IExecuteI/OInstructionExecuteRRInstructionAR