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1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

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Page 1: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1

Chapter Five

The Processor: Datapath and Control

Page 2: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-2

• We're ready to look at an implementation of the MIPS

• Simplified to contain only:

– memory-reference instructions: lw, sw – arithmetic-logical instructions: add, sub, and, or, slt– control flow instructions: beq, j

• Não implementadas: mult, div, jal, fp

• Generic Implementation:

– use the program counter (PC) to supply instruction address

– get the instruction from memory

– read registers

– use the instruction to decide exactly what to do

• All instructions use the ALU after reading the registers:

– memory-reference (sw lw), arithmetic, control flow

The Processor: Datapath & Control

Page 3: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-3

• Unclocked vs. Clocked

• Clocks used in synchronous logic

– when should an element that contains state be updated?

cycle time

rising edge

falling edge

State Elements

Page 4: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-4

Our Implementation

• An edge triggered methodology

• Typical execution:

– read contents of some state elements,

– send values through some combinational logic

– write results to one or more state elements

Clock cycle

Stateelement

1Combinational logic

Stateelement

2

Page 5: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-5

Register File (e Memória)

Mux

Register 0

Register 1

Register n – 1

Register n

Mux

Read data 1

Read data 2

Read registernumber 1

Read registernumber 2

Read registernumber 1 Read

data 1

Readdata 2

Read registernumber 2

Register fileWriteregister

Writedata Write

Register File:built out D-FF

Memória:• acesso Mem[addr]

RD WR

Dados

Endereço

Page 6: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-6

Uma visão simplificada

IR Mem[PC]PC PC + 4

R1 Mem[R2+off] R1 R2 op R3

R1 0 R1 1 PC PC +off

R2<R3? R1=R2?

lw, sw arit slt beq

S

N

S

N

Fetch ou busca

Dados: lw, swArit: add, sub, .. op

Log: sltDesvio: beq

lw $t1, 100($t2)add $t1, $t2, $t3slt $t1, $t2, $t3beq $t1, $t2, label

Page 7: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-7

• Primeira abordagem: 1 período de clock por instrução

• Abstract / Simplified View:

Two types of functional units:

– elements that operate on data values (combinational)

– elements that contain state (sequential)

More Implementation Details

Registers

Register #

Data

Register #

Datamemory

Address

Data

Register #

PC Instruction ALU

Instructionmemory

Address

exec de uma instrução

Page 8: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-8

Simple Implementation

• Include the functional units we need for each instruction

Why do we need this stuff?

PC

Instructionmemory

Instructionaddress

Instruction

a. Instruction memory b. Program counter

Add Sum

c. Adder

ALU control

RegWrite

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

ALUresult

ALU

Data

Data

Registernumbers

a. Registers b. ALU

Zero5

5

5 3

16 32Sign

extend

b. Sign-extension unit

MemRead

MemWrite

Datamemory

Writedata

Readdata

a. Data memory unit

Address

Page 9: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-9

Fetch

PC

Instructionmemory

Readaddress

Instruction

4

Add

Page 10: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-10

Tipo R

InstructionRegisters

Writeregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

ALUresult

ALU

Zero

RegWrite

ALU operation3

Page 11: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-11

Referência a Memória

Instruction

16 32

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Datamemory

Writedata

Readdata

Writedata

Signextend

ALUresult

ZeroALU

Address

MemRead

MemWrite

RegWrite

ALU operation3

Page 12: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-12

beq

16 32Sign

extend

ZeroALU

Sum

Shiftleft 2

To branchcontrol logic

Branch target

PC + 4 from instruction datapath

Instruction

Add

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

RegWrite

ALU operation3

Page 13: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-13

Building the Datapath

• Use multiplexors to stitch them together

PC

Instructionmemory

Readaddress

Instruction

16 32

Add ALUresult

Mux

Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

Shiftleft 2

4

Mux

ALU operation3

RegWrite

MemRead

MemWrite

PCSrc

ALUSrc

MemtoReg

ALUresult

ZeroALU

Datamemory

Address

Writedata

Readdata M

ux

Signextend

Add

Page 14: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-14

ALUs e Multiplexadores

• ALU genérica: R1 R2 op R3

• ALU soma para endereço instrução: PC + 4

• ALU soma para endereço de desvio: PC + SignExt (ShiftLeft (Offset))

• MUX 2:1 para escolher segundo operando da ALU genérica

– R2

– SignExt (Offset)

• MUX 2:1 para escolher o que será carregado no PC

– PC + 4

– PC + SignExt (ShiftLeft (Offset))

• MUX 2:1 para escolher qual é a origem do dado a ser escrito no Banco de Registradores

– lido da memória

– resultado da operação da ALU genérica

Page 15: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-15

Control

• Selecting the operations to perform (ALU, read/write, etc.)

• Controlling the flow of data (multiplexor inputs)

• Information comes from the 32 bits of the instruction

• Example:

add $8, $17, $18 Instruction Format:

000000 10001 10010 01000 00000 100000

op rs rt rd shamt funct

• ALU's operation based on instruction type and function code

Page 16: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-16

• e.g., what should the ALU do with this instruction• Example: lw $1, 100($2)

35 2 1 100

op rs rt 16 bit offset

• ALU control input

000 AND001 OR010 add110 subtract111 set-on-less-than

• Why is the code for subtract 110 and not 011?

Control

Page 17: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-17

Controle da ALU

OPCODE Function ALUop Operação

lw ou sw xxx xxx 00 soma

000 000 tipo da instr. 10 depende da instr.

beq xxx xxx 01 subtração

ALUControl

ALU

2

63

ALUop

funct

Unid.Contr.(parte)

6OPCODE

OPCODE Funct.IR

ALUOp Funct field OperationALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0

0 0 X X X X X X 010X 1 X X X X X X 1101 X X X 0 0 0 0 0101 X X X 0 0 1 0 1101 X X X 0 1 0 0 0001 X X X 0 1 0 1 0011 X X X 1 0 1 0 111

Binv - cod

Inst Funct.

add 32=20H

sub 34=22H

and 36=24H

or 37=25H

slt 42=2AH

Page 18: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-18

Lógica de controle da ALU

ALUOp Funct field OperationALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0

0 0 X X X X X X 010X 1 X X X X X X 1101 X X X 0 0 0 0 0101 X X X 0 0 1 0 1101 X X X 0 1 0 0 0001 X X X 0 1 0 1 0011 X X X 1 0 1 0 111

Inst Funct.

add 32=20H

sub 34=22H

and 36=24H

or 37=25H

slt 42=2AH

Operation2

Operation1

Operation0

Operation

ALUOp1

F3

F2

F1

F0

F (5– 0)

ALUOp0

ALUOp

ALU control block

Page 19: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-19

Campos da instrução e MUX adicional

• 2 registradores a serem lidos em todos os tipos: – campos rs (25-21) e rt (20-16)

• offset para beq, lw e sw: – (15-0)

• Registradores de destino (write register) em dois lugares:– lw e sw: rt (20-16)– Tipo R: rd (15-11)– Necessário MUX controlado por RegisterDestination: RegDst

Tipo R op rs rt rd shamt funct

31-26 25-21 20-16 15-11 10-6 5-0

lw sw op rs rt addr

31-26 25-21 20-16 15-0

beq op rs rt addr

31-26 25-21 20-16 15-0

Page 20: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-20

Control

Instruction RegDst ALUSrcMemto-

RegReg

WriteMem Read

Mem Write Branch ALUOp1 ALUp0

R-format 1 0 0 1 0 0 0 1 0lw 0 1 1 1 1 0 0 0 0sw X 1 X 0 0 1 0 0 0beq X 0 X 0 0 0 1 0 1

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Instruction [20– 16]

Instruction [25– 21]

Add

Instruction [5– 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc

Instruction [31– 26]

4

16 32Instruction [15– 0]

0

0Mux

0

1

Control

Add ALUresult

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Shiftleft 2

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1

Instruction [15– 11]

ALUcontrol

ALUAddress

Page 21: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-21

Unidade de Controle

R-format Iw sw beq

Op0

Op1

Op2

Op3

Op4

Op5

Inputs

Outputs

RegDst

ALUSrc

MemtoReg

RegWrite

MemRead

MemWrite

Branch

ALUOp1

ALUOpO

Instruction RegDst ALUSrcMemto-

RegReg

WriteMem Read

Mem Write Branch ALUOp1 ALUp0

R-format 1 0 0 1 0 0 0 1 0lw 0 1 1 1 1 0 0 0 0sw X 1 X 0 0 1 0 0 0beq X 0 X 0 0 0 1 0 1

Formato R: 000 000lw: 100 011sw: 101 011beq: 000 100

Page 22: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-22

• All of the logic is combinational

• We wait for everything to settle down, and the right thing to be done

– ALU might not produce “right answer” right away

– we use write signals along with clock to determine when to write

• Cycle time determined by length of the longest path

Our Simple Control Structure

We are ignoring some details like setup and hold times

Clock cycle

Stateelement

1Combinational logic

Stateelement

2

Page 23: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-23

Single Cycle Implementation

• Calculate cycle time assuming negligible delays except:

– memory (2ns), ALU and adders (2ns), register file access (1ns)

MemtoReg

MemRead

MemWrite

ALUOp

ALUSrc

RegDst

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Instruction [20– 16]

Instruction [25– 21]

Add

Instruction [5– 0]

RegWrite

4

16 32Instruction [15– 0]

0Registers

WriteregisterWritedata

Writedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

Signextend

ALUresult

Zero

Datamemory

Address Readdata M

ux

1

0

Mux

1

0

Mux

1

0

Mux

1

Instruction [15– 11]

ALUcontrol

Shiftleft 2

PCSrc

ALU

Add ALUresult

Page 24: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-24

Adicionando a instrução jump

Shiftleft 2

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Datamemory

Readdata

Writedata

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Instruction [15– 11]

Instruction [20– 16]

Instruction [25– 21]

Add

ALUresult

Zero

Instruction [5– 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

Branch

JumpRegDst

ALUSrc

Instruction [31– 26]

4

Mux

Instruction [25– 0] Jump address [31– 0]

PC+4 [31– 28]

Signextend

16 32Instruction [15– 0]

1

Mux

1

0

Mux

0

1

Mux

0

1

ALUcontrol

Control

Add ALUresult

Mux

0

1 0

ALU

Shiftleft 2

26 28

Address

address2

31-26 25-0

Page 25: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-25

Problemas com a alternativa de ciclo único

• “Vantagem”: CPI = ?

• Desempenho?

– supor unidades em uso: Memória (2ns), ALU (2ns), Registr (1ns)

Classe

R Fetch Registr ALU Registr

lw Fetch Registr ALU Mem Registr

sw Fetch Registr ALU Mem

beq Fetch Registr ALU

j Fetch

ClasseMem.Instr.

RegRD

ALUDataMem

RegWR

total

R 2 1 2 0 1 6

lw 2 1 2 2 1 8

sw 2 1 2 2 7

beq 2 1 2 5

j 2 2

Page 26: 1998 Morgan Kaufmann Publishers Mario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-1 Chapter Five The Processor: Datapath and Control

1998 Morgan Kaufmann PublishersMario Côrtes - MO401 - IC/Unicamp- 2002s1 Ch5A-26

Problemas com o ciclo único (2)

• Desempenho:– TCK = caminho crítico = 8 ns – velocidade limitada pelo pior caso

• Alternativas:– fazer clock com freqüência variável (muito custoso e complicado)– “picar” a instrução em pequenas funções e executá-las em vários ciclos de clock,

uma (ou mais) por ciclo• em vez de duração variável de ciclo, número variável

• Vantagens do multiciclo:– velocidade: ciclo limitado pela “operação” mais lenta e não pela “instrução” mais

lenta– instruções mais simples executam mais rapidamente– economia de hardware

• ter apenas 1: ALU, memória, registrador• usar uma vez todos esses, por ciclo