2. Computer Evolution and Performance

Spring 2016

Spring 2016 CS430 - Computer Architecture 1

Chapter 2: Computer Evolution andPerformance

Reading: pp. 16-49

Good Problems to Work: 2.1, 2.3, 2.4, 2.8, 2.9

Spring 2016 CS430 - Computer Architecture 2

FIRST GENERATION COMPUTERS

Vacuum Tubes

Spring 2016 CS430 - Computer Architecture 3

Brief History

ENIAC (Electronic Numerical Integrator and Computer)

Designed by: John Mauchly and John Presper Eckert

Reason: Response to wartime needs

Completed: 1946

Specifics: 30 tons, 15,000 sq ft, 18000 vacuum tubes, 5000 additions/sec decimal machine with 20 accumulators each accumulator could hold a 10-digit decimal number

Spring 2016 CS430 - Computer Architecture 4

ENIAC

Spring 2016 CS430 - Computer Architecture 5

Colossus

Designed by: Tommy Flowers (and others)

Reason: Codebreaking during World War II

Completed: 1943-1944

Specifics: Technically not a general purpose machine, though a set of 10 wouldmake a Universal Turing Machine

Spring 2016 CS430 - Computer Architecture 6

Colossus

Spring 2016 CS430 - Computer Architecture 7

Stored-Program Computer

ENIAC involved plugging and unplugging cables.

John von Neumann “If however, the program could be stored somehow and held in memory along with the data, this process would not be necessary. “ known as the stored-program concept

Alan Turing developed the idea about the same time

Spring 2016 CS430 - Computer Architecture 8

IAS Computer

Designed by: John von Neumann and others

Reason: Incorporate the stored-program concept

Completed: 1952

Specifics: 1024 words (40-bit words) of storage, both data and instructions are stored, binary representations

Spring 2016 CS430 - Computer Architecture 9

IAS Computer

Spring 2016 CS430 - Computer Architecture 10

IAS Computer

Spring 2016 CS430 - Computer Architecture 11

IAS Computer

Main memory - stores both data and instructions

Arithmetic and logic unit (ALU) - operates on binary data

Control unit - interprets the instruction in memory and causes the instruction to be executed

Input/Output (I/O) - operated by CU

Spring 2016 CS430 - Computer Architecture 12

IAS Memory

A word (40-bits) of storage can represent either an instruction or a number.

An instruction word really contains two instructions (left and right instructions)

Spring 2016 CS430 - Computer Architecture 13

Special IAS Registers

Memory Buffer Register (MBR) - used to store/retrieve a word to/from memory

Memory Address Register (MAR) - specifies the address used to store/retrieve a word to/from MBR

Instruction Register (IR) - contains opcode (8-bit) of the current instruction being executed

Instruction Buffer Register (IBR) - used to hold right instruction

Program Counter (PC) - contains address of next instruction to be executed

Accumulator (AC) and Multipier Quotient (MQ) - holds results of ALU operations. For a multiply of 2 words, the AC holds the most significant 40-bits and the MQ holds the least significant 40-bits.

Spring 2016 CS430 - Computer Architecture 14

Expanded IAS Computer Structure

Spring 2016 CS430 - Computer Architecture 15

Instruction Cycle

1. Fetch the next instruction

2. Execute the next instruction

3. go to 1.

Spring 2016 CS430 - Computer Architecture 16

Fetch Cycle

1. Load the opcode portion of the next instruction into the IR

2. Load the address portion of the next instruction into the MAR

Note: The next instruction can come from the IR, IBR, or MBR (to the IR, MAR & IBR)

Spring 2016 CS430 - Computer Architecture 17

Execute Cycle

1. Control circuitry decodes the opcode

2. Control signals are sent based on the decoded opcode

Spring 2016 CS430 - Computer Architecture 18

Fetch/Execute Partial Flowchart

Spring 2016 CS430 - Computer Architecture 19

IAS Instructions

IAS Instructions are grouped as:

1. data transfer - move data between MEM & ALU or two ALU registers

2. unconditional branch - branch to some location unconditionally. Execution may not be sequential in this case

3. conditional branch - branch is made based on some condition (allows decisions to be made)

4. arithmetic - ALU operations

5. address modify - addresses in an instruction can be modified

Spring 2016 CS430 - Computer Architecture 20

IAS Instruction Set

Spring 2016 CS430 - Computer Architecture 21

IAS Problem

1. Write the IAS assembly language program that will add the numbers stored at location 100 and 101. Place the result at location 102.

2. Assuming your assembly language program is stored beginning at location 110, fill in the table below.

Spring 2016 CS430 - Computer Architecture 22

IAS Problem

• Using the Figure on Slide 15 of the IAS Computer, what does the instruction cycle for adding two numbers defined on the previous slide look like?

Spring 2016 CS430 - Computer Architecture 23

SECOND GENERATION COMPUTERS

Transistors

Spring 2016 CS430 - Computer Architecture 24

Computer Generations

Spring 2016 CS430 - Computer Architecture 25

THIRD GENERATION COMPUTERS

Integrated Circuits

Spring 2016 CS430 - Computer Architecture 26

Integrated Circuits

• Computer consists of:– Gates

– Memory Cells

• Gates and memory cells are constructed of simple digital electronic components:– Transistors, resistors, conductors

– All fabricated from silicon

• Place them on one chip!

Spring 2016 CS430 - Computer Architecture 27

Video

• How do they make silicon wafers and computer chips?

– https://www.youtube.com/watch?v=aWVywhzuHnQ

Spring 2016 CS430 - Computer Architecture 28

Moore’s Law

Gordon Moore cofounder of Intel in 1965

Observed the number of transistors put on a chips doubled every year & predicted this would continue

True until 70’s & slowed to every 18 months and continued ever since

Spring 2016 CS430 - Computer Architecture 29

Moore’s Law

Spring 2016 CS430 - Computer Architecture 30

Consequences of Moore’s Law

1. Chip cost has remained virtually unchanged meaning the cost computer logic/memory circuitry has dramatically dropped

2. Electrical path shortened increasing operating speed

3. Reduction in power & cooling

4. Integrated circuits mean fewer inter-chip connections using solder therefore more reliable

Spring 2016 CS430 - Computer Architecture 31

Evolution of Intel Microprocessors

Spring 2016 CS430 - Computer Architecture 32

Evolution of Intel Microprocessors

Spring 2016 CS430 - Computer Architecture 33

Evolution of Intel Microprocessors

Spring 2016 CS430 - Computer Architecture 34

Evolution of Intel Microprocessors

Spring 2016 CS430 - Computer Architecture 35

Rest of Chapter

Read 2.2, 2.3, 2.4, and 2.5 on your own. You don’t have to understand every little detail as the rest of the course will cover info in these sections in great detail.

I will cover 2.6 at a later date

Spring 2016 CS430 - Computer Architecture 36

Next Time

• Read chapter 11 – pp. 365-380

Spring 2016 CS430 - Computer Architecture 37