41df2 Apple MacBook Pro A1226-EVT

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DRAWING


TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPDENG

DATE

APPDCK

ECNZONEREV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTIOND

SIZE

APPLICABLENOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OFSHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PARTII NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

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A

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A

REV.

DESCRIPTION OF CHANGEOROYA

Schematic / PCB #s

01/23/2007 - EVT

ALIASES RESOLVEDSCHEM,OROYA,M75

88

? ?? ??

1051-7225 10.0.0

SCH CRITICAL051-7225 SCHEM,MLB,M751

820-2101 PCBF,MLB,M75 CRITICALPCB1

(.csa) Contents SyncDatePageTable of Contents N/A1 N/A1

LAST_MODIFIED=Tue Jan 23 15:38:53 2007ABBREV=DRAWINGTITLE=MLB

SyncContents(.csa) DatePageT9_NOME

01/17/200749 SMC45(MASTER)

(MASTER)50 SMC Support46M76_MLB

01/18/200751LPC+ Debug Connector47

(MASTER)(MASTER)52

SMBus Connections48(MASTER)

(MASTER)53Current & Voltage Sensing49

(MASTER)(MASTER)54

Current Sensing50(MASTER)

(MASTER)55Thermal Sensors51

M76_MLB01/18/200756

Fan Connectors52M76_MLB

01/18/200758ALS Support53

M76_MLB01/18/200759

Sudden Motion Sensor (SMS)54T9_NOME

01/17/200761SPI BootROM55

(M59_SYNC)09/09/200669

PBus-In & Battery Connectors56M76_MLB

01/12/200770Power FETs57

M76_MLB01/23/200771

IMVP6 CPU VCore Regulator58M76_MLB

01/23/200772IMVP6 NB Gfx Core Regulator59

M76_MLB01/23/200773 5V / 3.3V Power Supply60

M76_MLB01/23/200774 1.25V / 1.05V Power Supply61

M76_MLB01/23/200775 1.8V DDR2 Supply62

M76_MLB01/23/200776 1.5V Power Supply63

M76_MLB01/23/200777

FW PHY Power Supplies64(MASTER)

(MASTER)78 3.425V G3Hot Supply & Power Control65(MASTER)

(MASTER)80NV G84M PCI-E66

(MASTER)(MASTER)81

NV G84M Core/FB Power67(MASTER)

(MASTER)82NV G84M Frame Buffer I/F68

(MASTER)(MASTER)84 GDDR3 Frame Buffer A69

(MASTER)(MASTER)85

GDDR3 Frame Buffer B70(MASTER)

(MASTER)86NV G84M GPIO/MIO/Misc71

(MASTER)(MASTER)87

GPU Straps72(MASTER)

(MASTER)88NV G84M Video Interfaces73

(MASTER)(MASTER)89

GPU (G84M) Core Supply74(MASTER)

(MASTER)90LVDS Display Connector75

(MASTER)(MASTER)94

DVI Display Connector76(MASTER)

(MASTER)95LVDS Interface Mux77

(M59_SYNC)08/24/200696

M75 Specific Connectors78T9_NOME

01/17/2007100CPU/FSB Constraints79

T9_NOME01/17/2007101

NB Constraints80T9_NOME

01/17/2007102Memory Constraints81

T9_NOME01/17/2007103 SB Constraints (1 of 2)82

T9_NOME01/17/2007104 SB Constraints (2 of 2)83

T9_NOME01/17/2007105 Clock & SMC Constraints84

T9_NOME01/17/2007106

FireWire Constraints85(MASTER)

(MASTER)107 GPU (G84M) Constraints86(MASTER)

(MASTER)108M75 Specific Constraints87

(MASTER)(MASTER)109

M75 Rule Definitions88

System Block Diagram 08/23/20062 (T9_MLB)2Power Block Diagram 08/23/20063 (T9_MLB)3Power Block Diagram N/A4 N/A4BOM Configuration N/A5 N/A5Revision History N/A6 N/A6Functional / ICT Test (MASTER)7 (MASTER)7Power Aliases (MASTER)8 (MASTER)8Signal Aliases 08/23/20069 (T9_MLB)9CPU FSB

01/17/200710T9_NOME10

CPU Power & Ground 01/17/200711 T9_NOME11CPU Decoupling & VID 01/18/200712 M76_MLB12eXtended Debug Port (XDP) 12/12/200613 T9_NOME13NB CPU Interface 01/17/200714 T9_NOME14NB PEG / Video Interfaces 01/17/200715 T9_NOME15NB Misc Interfaces 01/17/200716 T9_NOME16NB DDR2 Interfaces 01/17/200717 T9_NOME17NB Power 1 01/17/200718 T9_NOME18NB Power 2 01/17/200719 T9_NOME19NB Grounds 01/17/200720 T9_NOME20NB Standard Decoupling 01/17/200721 T9_NOME21NB Graphics Decoupling 01/18/200722 M76_MLB22SB Enet, Disk, FSB, LPC 01/17/200723 T9_NOME23SB PCI, PCIe, DMI, USB 01/19/200724 T9_NOME24SB Pwr Mgt, GPIO, Clink 01/22/200725 T9_NOME25SB Power & Ground 01/17/200726 T9_NOME26SB Decoupling 01/17/200727 T9_NOME27SB Misc 08/24/200628 (T9_MLB)28Clock (CK505) 01/22/200729 T9_NOME29Clock Termination 08/23/200630 (MASTER)30DDR2 SO-DIMM Connector A 08/24/200631 (M59_SYNC)31DDR2 SO-DIMM Connector B 08/24/200632 (M59_SYNC)32Memory Active Termination 11/14/200633 (T9_NOME)33Left I/O Board Connector 08/24/200634 (M59_SYNC)34Ethernet (Yukon) 01/17/200737 T9_NOME35Yukon Power Control 01/23/200738 T9_NOME36Ethernet Connector 01/18/200739 M76_MLB37FireWire Link (TSB83AA22) 01/18/200740 M76_MLB38FireWire PHY (TSB83AA22) 01/18/200741 M76_MLB39FireWire Port Power 01/18/200742 M76_MLB40FireWire Ports 01/18/200743 M76_MLB41PATA Connector (MASTER)44 (MASTER)42External USB Connector 01/18/200746 M76_MLB43Left Clutch Barrel Interconnect 01/18/200747 M76_MLB44

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III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT


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APPLE COMPUTER INC.SCALE

NONE

U9250/60J9000/10

U9120

J9400

J6800/1/2/3

J4600

Pg 96

Pg 12/103

Pg 124-130

J5600/10/50/60, J5720/30/50

Power Sense Pg 51, 115-120

U5572

U???U5550U5500

DC/BattSupplyPg 68-76

Conn

PEG Connector

1.05 - 1.25V533/667/800? MHz

Pg30,31

U5920 Sudden Motion Detect Pg 56

J5810/20/90 ALS SENS Pg 55

TERMS

ReGen

Pg ??Pg 52Pg 52Pg 51

Pg 24

LPC

SMB

GPIOs

Pg 24

Pg 22

Core 1.05VSB-ICH8

U2300

Pg 22

SATA

SATA-2

SATA-1

SATA-0

Pg 23

PCI-E

UATA

Pg 22

Ln6

Ln5

Ln4

Ln3

Ln2

Ln1

8-Bit100 MHz

Pg 91

ConnPCI

JB000

Pg 41

ConnFireWire

J4330J4320

FW-PHYPg 39

TSB81BA3U4100

FW-LinkPg 38

TSB82AA2U4000

32-Bit33 MHz

J4630

E-NETConnPg 37

E-NETNINEVEH

U3700

ConnPCI-E

JB500

AirPortMini PCI-E

Pg 33

J3400

Pg 65

AudioConns

Pg 63

AmpsSpeaker

Pg 62

Amp 2Line Out

Amp 1Pg 61

Line Out

Pg 60

AmpLine In

U6600/10/20U6500U6400U6300/1

Pg 59

CodecAudio

U6200 U????

Pg ??

MDC

Pg 45

GeyserTrackpad/Keyboard

J4700

Pg 45

BluetoothJ4720

Pg 45

Camera/IRJ4710

Pg 44

ConnectorsUSB

J4630

Prt 80, Comm 1, SMC, FWHLinda Fnc

CPUGPURight SideCharger

Temp Sense

Power

Pg 66

J6900/50

Fan Conn Pg 53, 54

Pg 48

LPC ConnJ5100

Pg 57

TPMU6000

Pg 46U4900

SMC PrtSerFanADCBSBBSAB,0A

Pg 58

Boot ROMSPI

U6100/50

UC500U2900

J3200J3100

Clk GenDIMMsPg 22

Pg 23

USB

AZALIAPg 23PCI

Pg 24CLnk 1

Pg 22E-NET

Pg 25Core

43

21

59

87

6

Pg 23SPI

Pg 24CLnk 0

Pg 23DMI

MUX

Pg 92

PCI-E

2.5 GHz6 - x1

UB100

Pg 93/4/5

Conns

PCI-E

JB400JB300JB200

Pg 42

Conn

UATA

Pg 43

ConnSATA

1.2 V / 1.5 GHzJ4510/20/30

GPIO Pg 80

MUX

from the PEG based GPU.J9200 Source is the LVDS

J9200 2.5 GHzx4 DMI

Pg 14

LVDS

RGB

Out

TV

Pg 15/1

6

DIMM

J3200J3100

1.8V - 64 BitsDDR2 - Dual Channel

Pg 15CLnk 0

Pg 15DMI

CoreNB-GMCH

Pg 32Term

Parallel

Misc

Main Memoryx16 PCI-E

SDVO

800/1066? MHz64-Bit

FSB

J8000

Pg 14

PCI-E

U1400Pg 13

Clocks

Pg 98

U2900

CK 505

Pg 98Clocks

UC500Pg 29TERMS

Pg 28J1300/JD000

ITP/XDP CONN

Core ~1.2V

Pg 9

CPU2.? GHz

Pg 10

U1000

Pg 78

Int DispConn

GPIO

MUXDVI-I

Pg 35

J4400

100 MHz3.3 V

Pg 79,81

Pg 77

Pg 17,18,19 Pg 15

T9 Diagram -- Needs to be updated to M75

SYNC_DATE=08/23/2006System Block Diagram

051-7225

2 88

10.0.0

SYNC_MASTER=(T9_MLB)

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C

D

A

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A

REV.


NONE

Power Block Diagram

051-7225 10.0.0

883

SYNC_MASTER=(T9_MLB) SYNC_DATE=08/23/2006

DSIZE

OFSHT

DRAWING NUMBER






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B

C

D

A

B

C

D

A

REV.


NONE

SYNC_DATE=N/ASYNC_MASTER=N/A

4 88

10.0.0051-7225

Power Block Diagram

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_ALT_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DSIZE

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NONE

Module Parts

BOM Variants

Bar Code Labels / EEE #s

IS

M75 BOM Groups

BOM ConfigurationSYNC_MASTER=N/A

5 88

10.0.0051-7225

SYNC_DATE=N/A

M75_COMMON,EEE_XXT,CPU_2_4GHZ,FB_256_HYNIXPCBA,OROYA2,VRAM-HY,M75630-8662

M75_COMMON ALTERNATE,COMMON,M75_COMMON1,M75_COMMON2,M75_DEBUG,M75_PROGPARTS

M75_COMMON,EEE_XXS,CPU_2_2GHZ,FB_128_HYNIXPCBA,OROYA1,VRAM-HY,M75630-8659

M75_COMMON,EEE_X5E,CPU_2_4GHZ,FB_256_SAMSUNGPCBA,OROYA2,M75630-7932

M75_COMMON,EEE_X5D,CPU_2_2GHZ,FB_128_SAMSUNGPCBA,OROYA1,M75630-7931

VRAM_256,VRAM_HYNIX,VRAM_256_HYNIXFB_256_HYNIX

VRAM_256,VRAM_SAMSUNG,VRAM_256_SAMSUNGFB_256_SAMSUNG

FB_128_HYNIX VRAM_128,VRAM_HYNIX,VRAM_128_HYNIX

FB_128_SAMSUNG VRAM_128,VRAM_SAMSUNG,VRAM_128_SAMSUNG

ALL157S0011 E&E alt to TDK/BI-Tech magnetics157S0030

ALL TI alt to National353S1681 353S1294

ALL138S0602 Murata alt to Samsung138S0603

VRAM_256_HYNIXU8400,U8450,U8500,U85504 CRITICAL333S0401 IC,SGRAM,GDDR3,16Mx32,700MHZ,136 FBGA

VRAM_128_HYNIXCRITICAL4 U8400,U8450,U8500,U8550IC,SGRAM,GDDR3,8Mx32,700MHZ,136 FBGA333S0409

U49001 SMC_PROGCRITICAL341S2004 IC,SMC,DEVELOPMENT,M75

SLG2AP101IC,SLG2AP101,LW PWR CLCK GEN,CK505,QFN681 CRITICALU2900359S0130

IC,ISL9504B,2PH IMVP6 REG,PMON,QFN48 U7100 ISL9504B353S1651 1 CRITICAL

CRITICALIC,SB,ICH8M,B0,ES1,ES2,BGA338S0335 1 U2300

IC,NB,CRESTLINE,965PM,B0,ES2338S0381 1 CRITICALU1400

353S1461 IC,ISL9504,SYNC REG CTRL,2PHAS,QFN48,LF ISL9504A1 U7100 CRITICAL

IC,GPU,NV G84M,BGA338S0388 1 U8000 CRITICAL

IC,MDC,SR,E0,ES2,2.4G,800FSB,4M,BGA CPU_2_4GHZ337S3429 U10001 CRITICAL

IC,MDC,SR,E0,ES2,2.2G,800FSB,4M,BGA1 U1000337S3428 CPU_2_2GHZCRITICAL

IC,MDC,SR,E0,ES2,2.0G,800FSB,4M,BGA CPU_2_0GHZ1337S3427 U1000 CRITICAL

EEE_XXT[EEE:XXT]LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL826-4393 1EEE_XXS[EEE:XXS]1826-4393 CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM

1 CRITICAL EEE_X5E826-4393 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:X5E]

EXTGPU_RST_YES,GPU_TMP401,HDCP,ISL9504B,LVDS_SEL_RESUME,ONEWIRE_PUM75_COMMON1

M75_DEBUG SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS

M75_PROGPARTS BOOTROM_PROG,SMC_PROG

P1V8S3_1V825,SLG2AP101,SMS_MOT_DIS,YUKON_ULTRA,VGA_TERM_CONNM75_COMMON2

1335S0384 U6100 BOOTROM_BLANKCRITICALIC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8

VRAM_128_SAMSUNG333S0404 IC,SGRAM,GDDR3,8Mx32,700MHZ,136 FBGA CRITICAL4 U8400,U8450,U8500,U8550

VRAM_256_SAMSUNGU8400,U8450,U8500,U8550IC,SGRAM,GDDR3,16Mx32,700MHZ,136 FBGA4 CRITICAL333S0382

152S0276 ALL152S0476 Inductor alternate

341S2002 CRITICAL1 BOOTROM_PROGU6100IC,EFI ROM,DEVELOPMENT,M75

1826-4393 EEE_X5DCRITICALLBL,P/N LABEL,PCB,28MM X 6 MM [EEE:X5D]

U4900IC,SMC,HS8/2116338S0274 CRITICAL SMC_BLANK1

CRITICAL1 IC,88E8058,GIGABIT ENET XCVR,64P QFN U3700338S0386

SLG8LP537U2900 CRITICAL359S0127 1 IC,68 PIN,CK505,LOW POWER CLOCK GENER

DSIZE

OFSHT

DRAWING NUMBER






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B

C

D

A

B

C

D

A

REV.


NONE

01/23/07 -- Released for EVT (Schem Rev 10, PCB Rev 02)

10.0.0:

9.5.0:

01/17/07 -- BOM: Added Hynix BOM configurations9.2.0:

01/18/07 -- IMVP: Updated BOMOPTIONs and values for ISL9504B

01/22/07 -- Clocks: Changed U2900 to SLG2AP101 as primary clock chip (T9_noME change 40975)01/22/07 -- LIO Conn: Removed unnecessary aliases as T9 reference design now matches M75 (T9_noME change 40998)

01/19/07 -- SB GPIOs: Changed SB_GPIO42 to WOW_EN and changed pullup to pulldown (T9_noME change 40787)

9.4.0:01/19/07 -- GPU GPIOs: Added 2 TPs on GPIOs to make G-state externally visible

01/19/07 -- SB Decoupling: Removed filtering for PP1V5_S0_SB_VCCGLANPLL to enable PP1V5_S0 corrections at SB

01/17/07 -- Testpoints: Removed FUNC_TEST from NB_RESET_L and FSB_DPWR_L per PCB request01/17/07 -- Power Sequencing: Added RC delay on PP1V8_S3 switcher enable

9.3.0:

01/19/07 -- Power Sequencing: Added C7859 to create RC delay for 1.5 and 1.05V S0 rails01/19/07 -- Clock Termination: Changed R3050 and R3055 to bypass discrete muxes for pending change to SLG2AP101

9.1.0:

8.2.0:

9.0.0:

EVT8.1.0:

PROTO

01/17/07 -- BOM: Consolidated 3 caps on page 59 from 132S0120 to 132S0131

01/17/07 -- Power FETs: Corrected BOM values for 5V/3.3V S3/S0 FETs

01/18/07 -- ODD Conn: Reconnected ODD power FET gate control circuitry to properly implement soft start (added one cap)

01/17/07 -- Sync with T9 noME (6.1.4) to pull in WOL_EN and Wake-on-Wireless support

01/17/07 -- Power Aliases: Moved LCD panel FET to PP3V3_S5 from S0

01/05/07 -- GPU FB: Corrected FB CLK termination (added cap and removed connection to VDDQ)

See Perforce change notes for updates before Proto Release

01/19/07 -- Power Sequencing: Changed power rail for U7850 to PP3V3_S5 to eliminate a leakage path

01/19/07 -- Ethernet Conn: Changed resistor short reference designators from R392x to RX392x

01/18/07 -- Testpoints: Added NO_TEST property to LVDS_L_DATA_N, _N, _P due to lack of layout space for TP

01/18/07 -- Clock Termination: Changed series termination on all single ended clocks to 33 ohms01/17/07 -- Power Aliases: Deleted alias that accidentally eliminated filtering on PP1V5_S0_SB_VCC1_5_B

01/17/07 -- SMBus: Changed R5260 & R5261 from 4.7K to 3.3K

01/12/07 -- Power Aliases: Moved Ethernet to PP3V3_S3 from S5 (layout improvements)01/12/07 -- Power Supplies: Minor power supply feedback connection changes from M76

01/09/07 -- Temp Sensors: NO STUFFed C5520 (circuit should have only 1 cap)

01/08/07 -- GPU FB: Added VREF support for unterminated memory mode (added FETs and pulldown Rs)

01/05/07 -- Clock Termination: Removed NO STUFF property from R3067

12/22/06 -- Released for Proto (Schem Rev 08, PCB Rev 01)

01/23/07 -- BOM: Changed C3860/61 to 22pF from 27 pF based on -R characterization (T9_noME change 41248)

01/22/07 -- BOM: Selected P1V8S3_1V825 BOMOPTION to lift voltage at FB memories01/22/07 -- BOM: Added BOMOPTIONs for SLG2AP101 (primary) and SLG8LP537 (backup)01/22/07 -- Clock Termination: Added R3051 for Silego 537/101 compatibility

01/23/07 -- BOM: Changed FB memories to new Samsung and Hynix APNs (also added new BOMOPTIONs to GPU straps)

6 88

10.0.0051-7225

Revision HistorySYNC_MASTER=N/A SYNC_DATE=N/A

DSIZE

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DRAWING NUMBER






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C

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A

B

C

D

A

REV.


NONE

FUNC_TESTFUNC_TEST

FUNC_TEST FUNC_TEST

FUNC_TEST

FUNC_TEST

FUNC_TEST

FUNC_TEST

FUNC_TEST FUNC_TEST

FUNC_TESTFUNC_TEST

NO_TEST

System Validation TPs

NB NO_TESTs

6 TPs, 2 with each of above TP pairs

ICT Test PointsFunctional Test Points

Left I/O Power Connector

Battery Digital ConnectorFan Connectors

Left Clutch Barrel Connector

2 TPsper

Other Func Test PointsThermal Diode Connectors

Current Sense Calibration

LPC+ Debug Connector

RTC Battery Connectorcalled out separately in these notes.NOTE: 10 additional GND test points are

Request for at least 10 GND test points

Left ALS Connector

NO_TEST

CPU FSB NO_TESTs

NO_TEST

GPU NO_TESTs

I550

I551

I552

7 88

10.0.0051-7225

Functional / ICT TestSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

TRUE LVDS_L_DATA_P

TRUE LVDS_L_DATA_NTRUE LVDS_L_DATA_N

TRUE FSB_A_LTRUE FSB_ADS_LTRUE FSB_ADSTB_L

TRUE FSB_BREQ0_LTRUE FSB_BNR_L

TRUE FSB_D_LTRUE FSB_DBSY_LTRUE FSB_DINV_LTRUE FSB_DRDY_LTRUE FSB_DSTB_L_NTRUE FSB_DSTB_L_PTRUE FSB_HIT_LTRUE FSB_HITM_L

TRUE FSB_REQ_LTRUE FSB_LOCK_L

NB_CLK100M_DPLLSS_PTRUE

FSB_CLK_NB_NTRUEFSB_CLK_NB_PTRUE

NB_RESET_L

REMTHMSNS_DX_PTRUE

SMC_RESET_LTRUE

CPU_THERMTRIP_RTRUE

NB_CLK96M_DOT_NTRUE

SMC_RX_LTRUE

INT_SERIRQTRUE

DEBUG_RESET_LTRUESMC_TMSTRUE

PP5V_S0TRUE

FAN_RT_TACHTRUE

SMC_NMITRUE

LINDACARD_GPIOTRUE

LPC_FRAME_LTRUE

SMC_TRST_LTRUE

SMC_TX_LTRUE

PCI_CLK33M_LPCPLUSTRUELPC_ADTRUE

LPC_ADTRUE

PCI_FW_GNT_LTRUE

PPVCORE_S0_CPUTRUE

LPC_ADTRUE

FAN_LT_PWMTRUE

PP3V42_G3HTRUE

FAN_RT_PWMTRUE

CPU_PWRGDTRUE

CPU_DPSLP_LTRUEPM_LAN_ENABLETRUEPCI_RST_LTRUE

FSB_CPUSLP_LTRUEFSB_DPWR_LNB_SB_SYNC_LTRUE

PPVBATT_G3_RTCTRUE

PPBUS_G3HTRUE

PM_SLP_S5_LTRUE

IMVP_DPRSLPVRTRUEPM_SLP_S3_LTRUE

IMVP_VR_ONTRUE

FSB_CPURST_LTRUE

PM_RSMRST_LTRUE

PM_DPRSLPVRTRUECPU_DPSLP_LTRUE

CPUTHMSNS_D2_NTRUECPUTHMSNS_D2_PTRUEREMTHMSNS_DX_NTRUE

ALS_GAINTRUEPP3V3_S3TRUE

PM_SYSRST_LTRUESMC_ONOFF_LTRUE

USB_WWAN_PTRUE

PP5V_S3TRUEUSB_WWAN_NTRUE

USB_CAMERA_PTRUE

PP5V_S3TRUEUSB_CAMERA_NTRUE

PPVCORE_GPUTRUE

PP5V_S3TRUEPPVCORE_S0_NB_GFXTRUE

ISENSE_CAL_ENTRUE

PP5V_S0TRUE

SMC_TDOTRUE

FWH_INIT_LTRUE

FAN_LT_TACHTRUE

LPC_ADTRUE

SMC_TDITRUESMC_TCKTRUE

GND_BATTTRUE

SMC_MD1TRUE

SMBUS_SMC_BSA_SDATRUE

PLT_RST_LTRUE

GPU_RESET_LTRUESMC_LRESET_LTRUE

CPU_STPCLK_LTRUE

NB_CLK100M_PCIE_PTRUENB_CLKREQ_LTRUE

NB_CLK96M_DOT_PTRUE

IMVP6_VIDTRUECPU_DPRSTP_LTRUEP1V5P1V05S0_PGOODTRUE

PM_S4_STATE_LTRUE

PM_ENET_ENTRUE

PM_CLKRUN_LTRUE

PM_SUS_STAT_LTRUE

LTALS_OUTTRUE

SMBUS_SMC_BSA_SCLTRUESMC_BS_ALRT_LTRUE

TP_NB_NCNC_NB_NCTRUE

NB_CLK100M_DPLLSS_NTRUE

NB_CLK100M_PCIE_NTRUE

VR_PWRGOOD_DELAYTRUEVR_PWRGD_CLKENTRUEPM_STPPCI_LTRUEPM_STPCPU_LTRUESB_RTC_RST_LTRUEPM_SB_PWROKTRUE

GNDTRUE

GNDTRUE

GNDTRUE

GNDTRUE

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65

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65

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25

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10

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28

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45

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7

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52

23

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56

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24

28

28

10

16

16

84

12

10

61

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36

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25

53

45

45 16

16

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9

25

25

25

23

9

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONEYukon EC will not be supported

"ENET" Rails

MAX I = ?.??A

MAX I = 0.36A

1.8V-0.9V Rails3.3V-2.5V Rails

"GPU" Rails

5V Rails

"FW" (FireWire) Rails

Chipset "VCore" Rails

"G3Hot" (Always-Present) Rails

SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

8 88

10.0.0051-7225

Power Aliases

MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

PP3V3_S3MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP3V3_S3PP3V3_S3

PP3V3_S0PP3V3_S0

PP3V3_S0MIN_LINE_WIDTH=0.6 mmVOLTAGE=3.3VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mm

PPVCORE_GPUMIN_NECK_WIDTH=0.2 mm

PPVCORE_GPU

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmVOLTAGE=1.2V

PPVCORE_GPU

PPBUS_G3HMIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmVOLTAGE=12.6V

PP5V_S0PP5V_S0PP5V_S0

PP5V_S0

PP5V_S0VOLTAGE=5V

PP5V_S0MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUEVOLTAGE=5V

PP5V_S3

PP5V_S3

PPVCORE_S0_NB_GFXPPVCORE_S0_NB_GFX

PPVCORE_S0_CPUMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUEVOLTAGE=1.25VMIN_NECK_WIDTH=0.3 mm

PP3V42_G3H

PP5V_S5

PP5V_S5

VOLTAGE=5VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

PP5V_S5

PP5V_S0PP5V_S0

PP5V_S0PP5V_S0

PP5V_S0

PP5V_S0PP5V_S0

PP5V_S3

PP3V42_G3H

PPDCIN_G3H

PP1V25_S0

MIN_LINE_WIDTH=0.4 mmPP3V3_GPU


PP3V3_GPUPP3V3_GPU

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmMAKE_BASE=TRUEVOLTAGE=1.8V

PP1V8_GPU

PP1V8_GPU

PP1V8_GPU

PP5V_S5

MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3VMAKE_BASE=TRUE

PP3V3_GPU_TMDS

PP1V05_S0PP1V05_S0

PP1V05_S0

PP1V05_S0PP1V05_S0

PP1V05_S0PP1V05_S0

PP1V05_S0PP1V05_S0

PP1V05_S0

VOLTAGE=1.05VMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm

PP3V42_G3HPP3V42_G3H

PP3V3_GPUPP3V3_GPUPP3V3_GPUPP3V3_GPUPP3V3_GPUPP3V3_GPU

PP3V3_GPUPP3V3_GPU

PP1V25_S0

PP1V25_S0

PP3V3_GPU_TMDS

PP1V25_GPU

PP3V3_GPU_TMDS

PPBUS_G3HPPBUS_G3H

PP1V25_ENET_ISNS

PP1V25_S0MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.25VMAKE_BASE=TRUE

PP1V25_GPU

PP1V8_GPUPP1V8_GPU

PP1V8_GPU

PP1V8_GPU

PP1V25_GPUPP1V25_GPU

PP3V3_S5

PP3V3_S5

PPBUS_G3H

PP3V3_GPU_TMDS


PP3V3_S5

PP5V_S3

PP5V_S3

PP3V3_S5

PP3V3_GPU

PP3V3_GPU

PP3V42_G3H

PPDCIN_G3H

PP3V3_S5PP3V3_S5PP3V3_S5

PP3V3_S5

PP3V3_S5PP3V3_S5

PPVP_FW

VOLTAGE=33VMIN_NECK_WIDTH=0.3 mmMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.95VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mmPP1V95_FWMIN_LINE_WIDTH=0.4 mm

PP3V3_FW

MAKE_BASE=TRUEVOLTAGE=3.3VMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm

PPVP_FW

PPVP_FWPPVP_FWPPVP_FW

PPVP_FW_PORTA_UFPPVP_FW_PORTA_UFMAKE_BASE=TRUE

PPVP_FW_PORTB_UFPPVP_FW_PORTB_UFMAKE_BASE=TRUE

PP3V3_FW

PP3V3_FWPP3V3_FW

PP3V3_FWPP3V3_FW

PP1V95_FW

PP1V95_FW

PP1V95_FW

PP3V3_GPUPP3V3_GPU

PPBUS_FW_FWPWRSW_FPPBUS_FW_FWPWRSW_FMAKE_BASE=TRUE

PP5V_S5

PP5V_S5

PP5V_S5

PP5V_S5

PP5V_S3PP5V_S3

PP5V_S5

PP5V_S3

PP3V3_S5

PP3V3_S5

PP1V25_GPU

PP1V8_S3

PP1V8_S3PP1V8_S3

PP1V8_S3

PP1V8_S3_ISNSPP1V8_S3_ISNS

PP1V8_S3_ISNSPP1V8_S3_ISNS

PP1V8_S3_ISNS PP1V8_S3_ISNS

VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mmMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PP1V8_S3

VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mmMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmPP1V8_S3

PP5V_S5

PP0V9_S3_MEM_VREFMIN_LINE_WIDTH=0.4 mmVOLTAGE=0.9VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.9VMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmPP0V9_S0

PP1V5_S0

PP1V5_S0

PP1V5_S0PP1V5_S0

PP1V25_S0

PP1V25_S0PP1V25_S0

PP1V25_S0PP1V25_S0

PP1V05_S0

PP1V05_S0

PPVCORE_S0_NB_R

PP0V9_S3_MEM_VREF

PP0V9_S3_MEM_VREF

PP0V9_S3_MEM_VREFPP0V9_S3_MEM_VREFPP0V9_S3_MEM_VREF

PP0V9_S0

PP1V8_S0

PP1V8_S0PP1V8_S0

PP1V8_S0MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUEVOLTAGE=1.8V

PP3V3_ENET

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUEPP3V3_ENET

PP3V3_ENET

PP3V3_ENET

VOLTAGE=1.9V

PP1V9_ENETMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmMAKE_BASE=TRUEPP1V9_ENET

VOLTAGE=1.25VMIN_LINE_WIDTH=0.6 mmPP1V25_ENET_ISNS

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mm

PP1V25_ENET_ISNSPP1V25_ENET_ISNS

PPVCORE_S0_NB_GFXMIN_LINE_WIDTH=0.5 mm


PPVCORE_S0_CPU

PPVCORE_S0_CPU

PPVCORE_S0_NB_GFX


MIN_LINE_WIDTH=0.6 mmVOLTAGE=1.25VMAKE_BASE=TRUE

PP1V25_GPUMIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

PP5V_S5

PP5V_S5

PP5V_S5

PP5V_S5

MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0.9VMAKE_BASE=TRUE

PPVCORE_S0_NB_R

PPVCORE_S0_NB_R

PP1V05_S0

PP0V9_S0

PP1V25_ENETPP1V25_ENET

MIN_LINE_WIDTH=0.6 mmVOLTAGE=1.25VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mmPP1V25_ENET

PP1V9_ENET

GND

PPBUS_G3H

PP3V42_G3H


MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mmVOLTAGE=18.5V

PPDCIN_G3H

PPBUS_G3HPPBUS_G3HPPBUS_G3H

PPBUS_G3HPPBUS_G3H

PP3V3_S5

PP3V42_G3H

PP5V_S5

PP1V25_ENET

PP5V_S3

PP5V_S5

PP3V3_S5

PP3V3_S5PP3V3_S5

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUEVOLTAGE=1.5V

PP1V5_S0

PP1V5_S0PP1V5_S0PP1V5_S0PP1V5_S0

PP1V5_S0PP1V5_S0

PP1V5_S0

PPBUS_G3H

PPBUS_G3H

PPBUS_G3H

MIN_NECK_WIDTH=0.2 mmMAKE_BASE=TRUEVOLTAGE=3.42V

PP3V42_G3HMIN_LINE_WIDTH=0.3 mm

PP3V42_G3H

PP3V42_G3H

PP3V3_S3

PP3V3_S3PP3V3_S3PP3V3_S3PP3V3_S3PP3V3_S3PP3V3_S3

PP3V3_S3PP3V3_S3

PP3V3_S3

PP3V3_S0

PP3V3_S0

PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0

PP3V3_S0PP3V3_S0

PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0

PP3V3_S0PP3V3_S0

PP3V3_S0PP3V3_S0PP3V3_S0

PP3V3_S0PP3V3_S0

PP3V3_S0

PP3V3_S0PP3V3_S0

PP3V3_S5PP3V3_S5

VOLTAGE=3.3V

PP3V3_S5MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

87

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63

63

63

21

21

60

65

65

65

65

21

60

48

60

60

60

60

60

55

48

65

65

55

55

63

63

63

63

63

63

63

60

60

60

48

48

48

57

57

57

57

57

57

57

57

57

57

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

55

55

54

54

54

25

25

25

59

59

58

58

58

58

58

58

78

78

47

63

63

63

58

58

58

58

58

58

58

78

47

74

74

74

77

77

77

63

19

19

19

19

19

19

19

19 19

19

47

47

74

74

74

74

74

74

74

74

59

59

77

77

77

48

48

59

78

78

48

74

74

47

48

48

48

48

48

48

74

74

63

63

63

63

78

78

63

78

48

48

63

34

34

34

34

19

19

59

63

63

63

63

19

59

47

59

59

59

59

59

48

47

63

78

63

48

48

34

34

34

34

34

34

34

59

59

59

47

47

47

54

54

54

54

54

54

54

54

54

54

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

48

48

53

53

53

24

24

24

58

58

57

57

57

57

57

57

57

57

46

62

62

62

57

57

57

57

57

57

57

57

46

65

73

73

73

73

73

73

62

18

18

18

18

18

18

18

18 18

18

46

46

73

73

73

73

73

73

73

73

65

65

77

58

58

65

77

73

73

73

77

77

46

46

58

77

77

57

57

46

73

73

46

46

46

46

46

46

46

73

73

62

62

62

62

57

57

62

57

46

46

77

87

87 87

87

87

87

62

27

27

27

27

65

65

65

65

65

18

18

77

77

77

58

62

62

62

62

18

58

46

58

58

58

58

58

46

46

62

57

62

46

46

27

27

27

27

27

27

27

58

58

58

46

46

46

53

53

53

53

53

53

53

53

53

53

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

46

46

50

50

50

23

23

23

57 57

52

52

52

52

52

52

53

53

58

45

61

61

61

52

52

52

52

52

52

52

53

45

57

72

72

72

70

70

70

61

14

14

14

14

14

14

14

14

14

14

45

45

72

72

72

72

72

72

72

72

57

57

74

57

57

57

74

70

70

70

74

74

28

28

57

74

74

53

53

28

72

72

45

28

28

28

28

28

28

72

72

61

61

61

61

53

53

61

53

28

28

74

62

62 62

62

57 57

57 57

57

62

62

61

26

26

26

26

57

57

57

57

57

14

14

50

58

58

74

74

74

57

61

61

61

61

50

50

14

57

45

57

57

57

57

57

28

45

61

53

61

28

28

26

26

26

26

26

26

26

57

57

57

45

45

45

50

50

50

50

50

50

50

50

50

50

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

28

28

48

48

48

21

21

21

74 74

74

56 56

47

47

47

47

47

47

49

49

59

59

49

43

60

60

60

47

47

47

47

47

47

47

49

43

27

71

71

71

69

69

69

60

13

13

13

13

13

13

13

13

13

13

43

43

71

71

71

71

71

71

71

71

27

27

71

56

56

27

71

69

69

69

71

71

27

27

56

71

71

49

49

27

71

71

43

27

27

27

27

27

27 64 64

64

64

64

64

71

71

60

60

60

60

49

49

60

49

27

27

71

50

50 50

50

50 50

50 50

50

50

50

60

62

22

22

22

22

27

27

27

27

27

13

13

22

62

62

62

62

62

65

65

65

65

49

49

59

71

71

71

56

60

60

60

60

22

22

13

56

43

56

56

56

56

56

27

43

60

49

60

27

27

22

22

22

22

22

22

22

56

56

56

43

43

43

48

48

48

48

48

48

48

48

48

48

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21 21

21

21

21

27

27

38

38

38

19

19

19

67 67

67

49 49

42

42

42

42

42

42

46

46

22

22

12

34

57

57

57

42

42

42

42

42

42

42

46

34

26

65

65

65

68

68

68

57

76

12

12

12

12

12

12

12

12

12

12

34

34

65

65

65

65

65

65

65

65

26

26

76

68

76

49

49

26

68

68

68

68

68

68

26

26

49

76

68

68

46

46

26

65

65

34

26

26

26

26

26

26

64

41

64

64

64

64

41

41

41

41

41

65

65

57

57

57

57

46

46

57

46

26

26

68

38

38 38

38

21 21

21 21

21

38

38

57

32

19

19

19

19

26

26

26

26

26

12

12

21

32

32

32

32

32

57

57

57

57

12

12

22

68

68

68

49

57

57

57

57

21

21

12

61

61

61

49

34

49

49

49

49

49

26

34

57

61

46

57

26

26

19

19

19

19

19

19

19

49

49

49

34

34

34

38

38

38

38

38

38

38

38

38

38

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

26

26

36

36

36

16

16

16

49 49

49

40 40

27

27

27

27

27

27

44

44

18

18

11

28

43

43

43

27

27

27

27

27

27

27

44

28

65

21

57

57

57

67

67

67

43

73

11

11

11

11

11

11

11

11

11

11

28

28

57

57

57

57

57

57

57

57

21

21

73

66

73

40

40

57

21

66

67

67

67

66

66

25

25

40

73

66

66

44

44

25

57

57

28

65

25

25

25

25

25

25

40

64

40

40

40

40

40

41 41

41 41

40

40

40

40

40

64

64

64

57

57

64 64

43

43

43

43

44

44

43

44

25

25

66

32

32 32

32

18

18

18 18

18

32

32

43

31

62

12

12

12

12

21

21

21

21

21

11

11

18

31

31

31

31

31

62

22

22

22

22

36

36

36

36

36

36

57

57

57

11

11

18

66

66

66

40

43

43

43

43

18

18

11

62

50

50

50

36

40

28

65

40

40

40

40

40

25

28

43

50

44

43

25

25

12

12

12

12

12

12

12

40

40

40

28

28

28

36

36

36

36

36

36

36

36

36

36

16

16

16

16

16

16 16

16

16

16 16

16

16 16

16

16

16 16

16

16

16 16

16

16

16 16

16

16

16

25

25

8

8

8

13

13

13

8 8

8

8 8

8

8

8

8

8

8

8

8

8

8

8

8

27

27

27

8

8

8

8

8

8

8

8

8

34

19

48

48

48

57

57

57

27

72

10

10

10

10

10

10

10

10

10

10

8

8

48

48

48

48

48

48

48

48

19

19

72

57

72

8

8

50

19

57

57

57

57

57

57

24

24

8

72

57

57

8

8

24

48

48

8

34

24

24

24

24

24

24

39

39

39

39

39

39

39

40 40

40 40

39

39

39

39

39

39

39

39

48

48

40 40

27

27

27

27

8

8

27

8

24

24

57

31

31

31

31

16

16

16 16

16

31

31

27

16

33

11

11

11

11

19

19

19

19

19

10

10

16

16

16

16

16

16

33

19

19

19

19

35

35

35

35

35

35

50

50

50

8

8

8

57

57

57

8

27

27

27

27

16

16

10

33

35

35

35

35

8

8

34

8

8

8

8

8

24

8

27

35

8

27

24

24

11

11

11

11

11

11

11

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

24

24

7

7

7

8

8

8

7 7

7

7 7

7

7

7

7

7

7

7

7

7

7

7

7

8

8

8

7

7

7

7

7

7

7

7

7

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

7

7

8

8

8

8

8

8

8

8

8

8

8

8

8

7

7

8

8

8

8

8

8

8

8

8

8

7

8

8

8

7

7

8

8

8

7

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8 8

8 8

8

8

8

8

8

8

8

8

8

8

8 8

8

8

8

8

7

7

8

7

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

7

7

7

8

8

8

7

8

8

8

8

8

8

8

8

8

8

8

8

7

7

8

7

7

7

7

7

8

7

8

8

7

8

8

8

8

8

8

8

8

8

8

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

(Cant be PTH)

ToolingHoles

(Cant be PTH)

NotchesEdge

Chassis GNDs

Frame Holes

Top CPU TM Notch

Left CPU

Add 2 buried vias to GND

TM Hole

RAM Door (Torx) Holes

TM Hole

Top GPU Right

Bottom Left GPU

TM Hole

Digital Ground

TM HoleRight CPU

Thermal Module Holes

BoardZT0945

1HOLE-VIA-P5RP25

ZT09501

HOLE-VIA-P5RP25

R09101

2

OMIT

NONE

SHORTNONE

NONE402

SH09251

2

3OG-503040SHLD-SM-LF

ZT09701

5P75R2P7ZT0975

15P75R2P7

ZT09801

5P75R2P7

ZT09851

5P75R2P7

ZT09301

3P7R3P2

ZT09351

3P7R3P2

ZT09401

3P7R3P2

ZT09201

3P2R2P7

ZT09651

3P2R2P7

ZT09551

3P2R2P7

ZT09901

HOLE-VIA-P5RP25

ZT09601

HOLE-VIA-P5RP25

SYNC_DATE=08/23/2006

051-7225 10.0.0

889

SYNC_MASTER=(T9_MLB)Signal Aliases

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0VMAKE_BASE=TRUE

GND_CHASSIS_DVI_BOT

TP_USB_EXTCNTP_USB_EXTCNMAKE_BASE=TRUE

PEG_CLK100M_GPU_N

PEG_CLK100M_GPU_P

PEG_CLK100M_GPU_NMAKE_BASE=TRUE

MAKE_BASE=TRUEPEG_CLK100M_GPU_P

TP_USB_EXTCP

MAKE_BASE=TRUESMC_SMS_INT SMC_SMS_INT

PM_ALL_NBGFX_PGOODMAKE_BASE=TRUE

PM_ALL_NBGFX_PGOOD

MAKE_BASE=TRUEVR_PWRGOOD_DELAY VR_PWRGOOD_DELAY

PM_SB_PWROKMAKE_BASE=TRUE

PM_SB_PWROK

GFX_VR_EN

GFX_VID

GFX_VR_ENMAKE_BASE=TRUEGFXIMVP6_VID

MAKE_BASE=TRUE

TP_MEM_A_ATP_MEM_A_AMAKE_BASE=TRUE

TP_MEM_B_ATP_MEM_B_AMAKE_BASE=TRUE

MAKE_BASE=TRUETP_USB_EXTCP

VOLTAGE=0VMIN_NECK_WIDTH=0.25 mmMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mmGND_CHASSIS_DVI_TOP

GND_CHASSIS_ENETMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmVOLTAGE=0VMAKE_BASE=TRUE

GND_CHASSIS_RTUSB

VOLTAGE=0VMIN_NECK_WIDTH=0.25 mmMAKE_BASE=TRUE


MAKE_BASE=TRUEVOLTAGE=0VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmGND_CHASSIS_LEFTCLUTCH

GND

GND_CHASSIS_DVI_TOP

GND_CHASSIS_DVI_BOT

GND_CHASSIS_ENETGND_CHASSIS_ENET

GND_CHASSIS_ENET

GND_CHASSIS_RTUSBGND_CHASSIS_RTUSB

GND_CHASSIS_LEFTCLUTCH

GND

GND

GND

GND

GND

GND

GND

GND

GND_CHASSIS_DVI_TOP

MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0V

GND

84

84

84

84

58 58

66

66

66

66

28 28

28 28

82 82

30

30

30

30

82

54 54

77 77

16 16

25 25

59 59

82

43

41

41

41

43

43

76

24 24

29

29

29

29

24

45 45

59 59

9 9

9 9

16 16

31 31

32 32

24

76

41

44

76

76

37

37

37

41

41

44

76

9

9 9

9

9

9

9

9

9 9

9 9

7 7

7 7

9

16

9

59

9 9

9 9

9

9

9

9

9

9

9

9

9

9

9

9

9

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

OUT

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

BI

BI

BI

BI

LOCK*

INIT*

A20M*

A6*

A3*A4*

A14*

A16*

REQ0*REQ1*REQ2*REQ3*REQ4*

BCLK1BCLK0

THERMTRIP*

THERMDAPROCHOT*

DBR*

TRST*TMSTDOTDI

TCKPREQ*PRDY*

BPM3*BPM2*BPM1*BPM0*

HITM*HIT*

TRDY*

RS2*RS1*RS0*

RESET*

IERR*

BR0*

DBSY*DRDY*

DEFER*

BNR*

RSVD9RSVD8RSVD7RSVD6RSVD5RSVD4RSVD3RSVD2RSVD1RSVD0

SMI*LINT1LINT0STPCLK*

FERR*

ADSTB1*A35*A34*A33*A32*A31*A30*A29*A28*

A19*A18*A17*

ADSTB0*

A13*A12*

BPRI*

A20*A21*A22*A23*A24*

A26*A27*

A9*A8*A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

NC

1 OF 4

CONTROL

THERMAL

XDP/I

TP S

IGNA

LS

H CLK

RESERVED

ADDR GROUP0

ADDR GROUP1

ICH

DINV1*

D31*D30*

D25*

D11*D12*D13*D14*

DSTBP0*DINV0*

D9*D8*D7*D6*

D19*D18*

DATBP1*

D0* D32*D1*D2*

D5*

D16*

D20*D21*D22*D23*D24*

D26*D27*D28*D29*

DSTBN1*

GTLREFTEST1TEST2TEST3TEST4TEST5TEST6

BSEL0BSEL1BSEL2

D33*D34*D35*D36*D37*D38*D39*D40*D41*D42*D43*D44*D45*D46*D47*

DSTBN2*DSTBP2*DINV2*

D48*D49*D50*D51*D52*D53*D54*D55*D56*D57*D58*D59*D60*D61*D62*D63*

DSTBN3*DSTBP3*DINV3*

COMP0COMP1COMP2COMP3

DPRSTP*DPSLP*DPWR*

PWRGOODSLP*PSI*

D17*

D4*D3*

DSTBN0*D15*

D10*

2 OF 4

DATA GRP 3

DATA GRP 2

MISC

DATA GRP 0

DATA GRP 1

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

PIN. MAKE SURE CPU_TEST4 ISPLACE C1000 CLOSE TO CPU_TEST4

REFERENCED TO GND

0.5" MAX LENGTH FOR CPU_GTLREF

FSB_IERR_L WITH A GNDPLACE TESTPOINT ON

0.1" AWAY

GMCH WITHOUT T (NO STUB)SHOULD CONNECT TO ICH ANDPM_THRMTRIP#

COMP1,3 CONNECT WITH ZO=55OHM,MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM,MAKE TRACE LENGTH SHORTER THAN 0.5".

LAYOUT NOTE:

NC

R10021

2

1%1/16W54.9

MF-LF402

R10041

2

685%1/16W402MF-LF

R10051

2

1/16W1%

MF-LF

1K

402

R10061

2

1%MF-LF

2.0K1/16W

402

R1019

1%

MF-LF1/16W

54.9

402

R101827.4

1/16WMF-LF

1%

402

R1017

1%

MF-LF1/16W

54.9

402

R1016

1%

MF-LF1/16W

27.4

402

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 16 23 58 79

7 23 79

7 14 79

7 14 79

28 58

7 13 23 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

30 79

30 79

30 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

14 79

14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

13 79

13 79

13 79

13 79

13 79

13 79

10 13 79

13 28

46 58 79

51

16 23 46 79

23 47 79

7 13 14 79

14 79

14 79

14 79

14 79

10 13 79

10 13 79

10 13 79

10 13 79

51 87

29 30 84

29 30 84

23 79

23 79

23 79

23 79

7 23 79

23 79

23 79

R10300

1/16WMF-LF

5%

NOSTUFF

402 R10071

2

1/16W5%MF-LF

1K

NOSTUFF

402

R10031

2

1/16W1%MF-LF

54.9

402

R1020

1%

MF-LF1/16W

54.9

402R102154.9

1/16WMF-LF

1%

402

R102254.9

1/16WMF-LF

1%

402

14 79

14 79

14 79

14 79

R1023649

1/16WMF-LF

1%

402

R10121

2

1/16W5%1K

NOSTUFF

MF-LF402

C10001

2 X5R

NOSTUFF

0.1uF10%16V

402

U1000

N3P5P2L2P4P1R1

Y2U5R3W6

A6

U4Y5U1R4T5T3W2W5Y4

J4

U2V4W3AA4AB2AA3

L5L4K5M3N2J1

H1

M1

V1

A22A21

E2

AD4AD3AD1AC4

G5

F1

C20

E1

H5F21

A5

G6E4

D20

C4

B3

C6B4

H4

B1

AC2AC1

D21

K3H2K2J3L1

C1F3F4G3

M4N5T2V3B2C3D2D22D3F6

A3

D5

AC5AA6AB3

A24B25

C7

AB5

G2

AB6

OMIT

MEROMFCBGA

U1000

B22B23C21

R26U26AA1Y1

E22F24

J24J23H22F26K22H23

N22K25P26R23

E26

L23M24L22M23P25P23P22T24R24L25

G22

T25N25

Y22AB24V24V26V23T22U25U23

F23

Y25W22Y23W24W25AA23AA24AB25

AE24AD24

G25

AA21AB22AB21AC26AD20AE22AF23AC25AE21AD21

E25

AC22AD23AF22AC23

E23K24G24

M26

H25

N24

U22

AC20

E5B5D24

J26

L26

Y26

AE25

H26 AA26

AF24

AD26

AE6

D6D7

C23D25C24

AF26AF1A26

OMIT

MEROMFCBGA

R1024

1%

MF-LF1/16W

54.9

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)402

SYNC_DATE=01/17/2007SYNC_MASTER=T9_NOME

88

051-7225 10.0.0

10

CPU FSB

TP_CPU_TEST5

FSB_DINV_L

FSB_D_LFSB_D_L

FSB_D_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_DSTB_L_PFSB_DINV_L


FSB_D_LFSB_D_L

FSB_DSTB_L_P

FSB_D_L FSB_D_LFSB_D_LFSB_D_L

FSB_D_L

FSB_D_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L


FSB_DSTB_L_N

CPU_GTLREFCPU_TEST1CPU_TEST2TP_CPU_TEST3CPU_TEST4

TP_CPU_TEST6

CPU_BSELCPU_BSELCPU_BSEL

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_DSTB_L_NFSB_DSTB_L_PFSB_DINV_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_DSTB_L_NFSB_DSTB_L_PFSB_DINV_L

CPU_COMPCPU_COMPCPU_COMPCPU_COMP

CPU_DPRSTP_LCPU_DPSLP_LFSB_DPWR_LCPU_PWRGDFSB_CPUSLP_LCPU_PSI_L

FSB_D_L

FSB_D_LFSB_D_L

FSB_DSTB_L_NFSB_D_L

FSB_D_L

FSB_LOCK_L

CPU_INIT_L

CPU_A20M_L

FSB_A_L

FSB_A_LFSB_A_L

FSB_A_L

FSB_A_L

FSB_REQ_LFSB_REQ_LFSB_REQ_LFSB_REQ_LFSB_REQ_L

FSB_CLK_CPU_NFSB_CLK_CPU_P

PM_THRMTRIP_L

CPU_THERMD_PCPU_PROCHOT_L

XDP_DBRESET_LXDP_TRST_LXDP_TMSXDP_TDOXDP_TDI

XDP_BPM_LXDP_BPM_L

XDP_BPM_LXDP_BPM_L

FSB_HITM_LFSB_HIT_L

FSB_TRDY_LFSB_RS_LFSB_RS_LFSB_RS_LFSB_CPURST_L

CPU_IERR_L

FSB_BREQ0_L

FSB_DBSY_LFSB_DRDY_LFSB_DEFER_L

FSB_BNR_L

TP_CPU_RSVD9TP_CPU_RSVD8TP_CPU_RSVD7TP_CPU_RSVD6TP_CPU_RSVD5TP_CPU_RSVD4TP_CPU_RSVD3TP_CPU_RSVD2TP_CPU_RSVD1TP_CPU_RSVD0

CPU_SMI_LCPU_NMICPU_INTRCPU_STPCLK_L

CPU_FERR_L

FSB_ADSTB_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_L

FSB_A_LFSB_A_LFSB_A_L

FSB_ADSTB_L

FSB_A_LFSB_A_L

FSB_BPRI_L

FSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_L

FSB_A_LFSB_A_L

FSB_A_LFSB_A_LFSB_A_L

FSB_A_L

FSB_A_L

CPU_IGNNE_L

FSB_ADS_L

FSB_A_L

FSB_A_L

FSB_A_L

XDP_TCK

XDP_TDO

XDP_TMS

XDP_TDI

XDP_TRST_L

PP1V05_S0

PP1V05_S0

PP1V05_S0

PP1V05_S0

CPU_THERMD_N

XDP_TCKXDP_BPM_L

XDP_BPM_L

61

61

61

61

50

50

50

50

46

46

46

46

30

30

30

30

27

27

27

27

26

26

26

26

23

23

23

23

21

21

21

21

19

19

19

19

18

18

18

18

14

14

14

14

13

13

13

13

12

12

12

12

79

79

79

79

79

11

11

11

11

13

13

13

13

13

10

10

10

10

79 79

79

79

79

79

10

10

10

10

10

8

8

8

8

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

VCC

VSSSENSE

VCCSENSE

VID6VID5VID4VID3VID2VID1VID0

VCCA

VCCP

VCC

3 OF 4

VSS VSS

4 OF 4

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

11.5 A (Deeper Sleep)

25.0 A (Deep Sleep HFM)

27.4 A (Sleep HFM)17.0 A (Auto-Halt/Stop-Grant SuperLFM)27.4 A (Auto-Halt/Stop-Grant HFM)

30.4 A (LFM)25.5 A (SuperLFM)

9.4 A (Enhanced Deeper Sleep)

2500 mA (after VCC stable) 4500 mA (before VCC stable)

16.0 A (Deep Sleep SuperLFM)

16.8 A (Sleep SuperLFM)

41.0 A (HFM)44.0 A (Design Target)Standard Voltage:

(CPU CORE POWER)

130 mA

(CPU IO POWER 1.05V)

(CPU INTERNAL PLL POWER 1.5V)

Low Voltage: Ultra Low Voltage:17.0 A (Design Target)23.0 A (Design Target)

21.0 A (HFM)18.7 A (LFM)TBD A (SuperLFM)TBD A (Auto-Halt/Stop-Grant HFM)TBD A (Auto-Halt/Stop-Grant SuperLFM)TBD A (Sleep HFM)TBD A (Sleep SuperLFM)TBD A (Deep Sleep HFM)TBD A (Deep Sleep SuperLFM)TBD A (Deeper Sleep)TBD A (Enhanced Deeper Sleep) TBD A (Enhanced Deeper Sleep)

TBD A (Deeper Sleep)

TBD A (Deep Sleep HFM)

TBD A (Sleep HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (HFM)TBD A (LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (Auto-Halt/Stop-Grant LFM)

TBD A (Sleep LFM)

TBD A (Deep Sleep LFM)

12 79

12 79

12 79

12 79

12 79

12 79

R11011

2

1/16W1%100

402MF-LF

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

12 79

58 79

58 79

U1000

A7A9

B9B10B12B14B15B17B18B20C9C10

A10

C12C13C15C17C18D9D10D12D14D15

A12

D17D18E7E9E10E12E13E15E17E18

A13

E20F7F9F10F12F14F15F17F18F20

A15

AA7AA9

AA10AA12AA13AA15AA17AA18AA20AB9

A17

AC10AB10AB12AB14AB15AB17AB18

AB20AB7AC7

A18

AC9AC12AC13AC15AC17AC18AD7AD9AD10AD12

A20

AD14AD15AD17AD18AE9AE10AE12AE13AE15AE17

B7

AE18AE20AF9AF10AF12AF14AF15AF17AF18AF20

B26C26

G21V6

R21R6T21T6V21W21

J6K6M6J21K21M21N21N6

AF7

AD6AF5AE5AF4AE3AF3AE2

AE7

OMIT

MEROMFCBGA

U1000

A4A8

B11

W1W4W23W26Y3Y6Y21Y24AA2AA5

B13

AA8AA11AA14AA16AA19AA22AA25AB1AB4AB8

B16

AB11AB13AB16AB19AB23AB26AC3AC6AC8AC11

B19

AC14AC16AC19AC21AC24AD2AD5AD8AD11AD13

B21

AD16AD19AD22AD25AE1AE4AE8AE11AE14AE16

B24

AE19AE23AE26A2AF6AF8AF11AF13AF16AF19

C5

AF21A25AF25

C8C11C14

A11

C16C19C2C22C25D1D4D8D11D13

A14

D16D19D23D26E3E6E8E11E14E16

A16

E19E21E24F5F8F11F13F16F19F2

A19

F22F25G4G1G23G26H3H6H21H24

A23

J2J5J22J25K1K4K23K26L3L6

AF2

L21L24M2M5M22M25N1N4N23N26

B6

P3

P6P21P24R2R5R22R25T1T4

B8 T23T26U3U6U21U24V2V5V22V25

OMIT

MEROMFCBGA

R11001

2

1001%1/16W

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.402MF-LF

8811

10.0.0051-7225

CPU Power & GroundSYNC_MASTER=T9_NOME SYNC_DATE=01/17/2007

PP1V05_S0

PP1V5_S0

CPU_VID

CPU_VID

PPVCORE_S0_CPU

CPU_VIDCPU_VID

CPU_VCCSENSE_P

CPU_VCCSENSE_N

PPVCORE_S0_CPU

CPU_VID

CPU_VIDCPU_VID

61 50 46 30 27 26 23

87

21

63

19

34

18

27

58

58

14

26

49

49

13

22

12

12

12

19

11

11

10

12

8

8

8

8

7

7

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

WF: Consider sharing bulk cap with NB Vtt?

VCCA (CPU AVdd) DECOUPLING1x 10uF, 1x 0.01uF

VCCP (CPU I/O) DECOUPLING1x 470uF, 6x 0.1uF 0402

CPU VCORE HF AND BULK DECOUPLINGCPU VCORE VID CONNECTIONS4x 330uF, 20x 22uF 0805

C12061

2

22UF20%6.3V805CERM-X5R

C1235 1

2 3

470UF20%

D2TTANT2.5V

CRITICAL

C12041

2


C12161

2

22UF

CERM-X5R8056.3V20%

C12141

2

22UF

CERM-X5R8056.3V20%

C12081

2


C12031

2


C12071

2


C12021

2 6.3V22UF20%

805CERM-X5R

C12011

2


C12131

2

22UF

CERM-X5R8056.3V20%

C12121

2

22UF

CERM-X5R20%

8056.3V

C12111

2

22UF

CERM-X5R8056.3V20%

C12191

2

22UF

CERM-X5R20%6.3V805

C12001

220%

8056.3V22UF

CERM-X5R

C12101

2

22UF

CERM-X5R20%6.3V805

C12361

2 10V402CERM20%0.1UF

C12051

2


C12091

2


C12151

2

22UF

CERM-X5R8056.3V20%

C12171

2

22UF

CERM-X5R8056.3V20%

C12371

2 10V0.1UF

402CERM20%

C12381

2 10V0.1UF

402CERM20%

C12391

2 10V0.1UF

402CERM20%

C12401

2 10V0.1UF

402CERM20%

C12411

2 10V0.1UF

402CERM20%

C12181

2

22UF

CERM-X5R20%

8056.3V

C12811

2

0.01UF10%16V402CERM

PLACEMENT_NOTE=Place near CPU pin B26.

C1280 1

2603

10uF20%

6.3VX5R

C1250 1

2 3

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.D2T

TANT

330UF2.0V10%

C1251 1

2 3

PLACEMENT_NOTE=Place in CPU center cavity.

D2TTANT

CRITICAL

330UF2.0V10%

C1252 1

2 3


10%

D2TTANT

CRITICAL

330UF2.0V

C1253 1

2 3


CRITICAL

D2TTANT

10%330UF

2.0V

051-7225

SYNC_DATE=01/18/2007

10.0.0

12 88

SYNC_MASTER=M76_MLB

CPU Decoupling & VID

PPVCORE_S0_CPU

CPU_VIDMAKE_BASE=TRUE

IMVP6_VID

PP1V5_S0

PP1V05_S061 50 46 30 27

26

87

23

63

21

34

19

27

18

58

26

14

49

22

13

11

79

19

11

8

79 58

11

10

7

11 7

8

8

IN

BI

BI

OUT

OUT

IN

BI

IN

IN

IN

OUT

IN

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

IN

BI

IN

IN

IN

IN

IN

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NB CFG[0]NB CFG[1]

Use with 920-0451 adapter board to support CPU, NB & SB debugging.

Mini-XDP ConnectorNOTE: This is not the standard XDP pinout.

(VCC_OBS_CD)

OBSFN_C0

OBSDATA_D3

SB GPIO[8]NB CFG[8]

NB CFG[3]

NB CFG[7]NB CFG[6]

NB CFG[5]N

Documents

41df2 Apple MacBook Pro A1226-EVT