Computer Organization zA computer has no intelligence. It
follows the commands you specify in the program. zProgram: yA
sequence of instructions. yThe CPU executes them one-by-one.
Slide 3
Programming Language zMachine-Level: yused by the computer
ytrains of 0s and 1s yAssembly level source code -> assemble
-> object code zHigh-Level and Mid-Level yNearer to natural
language yNeed compilation ySource code -> compile -> object
code
Slide 4
Why Assembly Language? (1) zMachine program is difficult to
write, debug, understand and error-prone. zUse symbols or mnemonics
to replace the 0s and 1s. E.g.: yassembly: MOV A, 1 ymachine: 0011
0101 0001 yUsing machine language, one has to determine the address
of A manually.
Slide 5
Why Assembly Language? (2) zUsing Assembly Language, you need
an assembler to translate an assembly program to a machine program.
zAssembly Language y1-1 correspondence with the machine program.
yDirectly communicates with the computer yhas precise control of
the computer ymachine dependent
Slide 6
Computer Architecture Memory (RAM, ROM) ProcessorI/O Unit Disk
Modern CRT terminal Keyboard Control Data Address
Slide 7
Processor zALU (Arithmetic Logic Unit) zsystem clock zregisters
zInstruction register(IR) zInstruction decoder(ID) zinternal system
bus
Slide 8
Bus and register Control Data Address System Bus Controller
(System Clock) MDR (Data Buffer) MAR (Address Buffer) Registers
Program counter (PC) CCR ALU Internal Bus ID Instruction
Register(IR)
Slide 9
Basic Instruction Formats zAn instruction is divided into
different fields: zOpcode: Operation to perform, e.g. addition
zOperand 1 to Operand N: The data which the operation will act on.
Opcode | Operand 1 | | Operand N
Slide 10
Basic Instruction Formats zThe number of operands N varies for
different computers. In 8088, N can be 0, 1, or 2. zN=2: yE.g. ADD
AX, BX means AX0)else
Slide 14
Instruction execution cycle z2. Instruction Decode: yGenerate
the control signals to accomplish the tasks of the instruction. z3.
Data Fetch (for operands)
Slide 15
Instruction Fetch - Execution z4. Execution: yALU ySet the
condition codes (flags) to indicate the characteristics of last
executions result. yE.g. overflow, negative
Slide 16
Execution zNote: yCondition Code Register (CCR) is more
commonly known as the Processor Status Word (PSW) yBranch
instructions check the status of the PSW yA branch is either taken
or not taken. If it is taken, the branch address is loaded into the
PC. Effectively, the sequential flow of instruction (or control) is
interrupted.
Slide 17
E.g.1 Control Data Address System Bus Controller (System Clock)
MDR (Data Buffer) MAR (Address Buffer) Registers PC: 1003 CCR ALU
Internal Bus ID Instruction Register(IR)
Slide 18
E.g.1 Control Data Address System Bus Controller (System Clock)
MDR (Data Buffer) MAR 1003 Registers PC: 1007 CCR ALU Internal Bus
ID Instruction Register(IR)
Slide 19
E.g.1 Control Data Address System Bus Controller (System Clock)
MDR ADD AH, 2 MAR 1003 Registers PC: 1007 CCR ALU Internal Bus ID
Instruction Register(IR)
Slide 20
E.g.1 Control Data Address System Bus Controller (System Clock)
MDR ADD AH, 2 MAR 1003 Registers PC: 1007 CCR ALU Internal Bus ID
IR: ADD AH, 2
Slide 21
E.g.1 Control Data Address System Bus Controller (System Clock)
MDR ADD AH, 2 MAR 1003 Registers PC: 1007 CCR: -ve ALU Internal Bus
ID IR: ADD AH, 2
Slide 22
E.g.1 Control Data Address System Bus Controller (System Clock)
MDR ADD AH, 2 MAR 1007 Registers PC: 1009 CCR: -ve ALU Internal Bus
ID IR: ADD AH, 2
Slide 23
E.g.1 Control Data Address System Bus Controller (System Clock)
MDR: JL TARGET MAR 1007 Registers PC: 1009 CCR: -ve ALU Internal
Bus ID IR: ADD AH, 2
Slide 24
E.g.1 Control Data Address System Bus Controller (System Clock)
MDR: JL TARGET MAR 1007 Registers PC: 1009 CCR: -ve ALU Internal
Bus ID IR: JR TARGET
Slide 25
E.g.1 Control Data Address System Bus Controller (System Clock)
MDR: JL TARGET MAR 1007 Registers PC: 1033 CCR: -ve ALU Internal
Bus ID IR: JR TARGET
Slide 26
E.g.2
Slide 27
Control Data Address System Bus Controller (System Clock) MDR
MOV AH, SRC MAR 1003 Registers PC: 1007 CCR ALU Internal Bus ID
Instruction Register(IR)
Slide 28
E.g.2 Control Data Address System Bus Controller (System Clock)
MDR MOV AH, SRC MAR 1003 Registers PC: 1007 CCR ALU Internal Bus ID
IR: MOV AH, SRC
Slide 29
E.g.2 Control Data Address System Bus Controller (System Clock)
MDR MOV AH, SRC MAR 1063 Registers PC: 1007 CCR ALU Internal Bus ID
IR: MOV AH, SRC
Slide 30
E.g.2 Control Data Address System Bus Controller (System Clock)
MDR: 20 MAR 1063 Registers PC: 1007 CCR ALU Internal Bus ID IR: MOV
AH, SRC
