8085 Microprocessor Instruction Set Architecture

8/17/2019 8085 Microprocessor Instruction Set Architecture

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Relatively Simple CPU and 8085Relatively Simple CPU and 8085

microprocessor Instruction Setmicroprocessor Instruction Set

ArchitectureArchitecture

Presented by: Chi YanPresented by: Chi Yan

un!un!Class: Cs "#$ % sec & 'allClass: Cs "#$ % sec & 'all

&00"&00"

Pro(: Sin%)in *eePro(: Sin%)in *ee


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Topics to coverTo

pics to cover

• Relatively Simple Instruction Set ArchitectureRelatively Simple Instruction Set Architecture

• 8085 Microprocessor Instruction Set Architecture8085 Microprocessor Instruction Set Architecture

• Analyzing the 8085 Instruction Set ArchitectureAnalyzing the 8085 Instruction Set Architecture

• SummarySummary


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Relatively Simple microprocessors, or CPU

• Designed as an instructional aid and draws its

features from several real microprocessors

• Too limited to run anything as complex as

personal computer

• It has about the right level of complexity tocontrol a microwave oven or other consumer

appliance


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Instruction Set Architecture (ISA)• Memory Model

• Registers

• Instruction set


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Memory Moel• This microprocessor can access !" ( # $% )

bytes of memory

• &ach byte has ' bits therefore it can access

!" × ' bits of memory

• !" of memory is the maximum limit

sometimes a system based on this *+ can

have less memory

• +se memory to map I,-

.ame instructions to use for accessing I,-

devices and memory


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Registers• /ccumulator (/) is an '0bit general purpose

register

• Register R is an '0bit general purpose register1

It supplies the second operand and also it can be

use to store data that the / will soon need toaccess1

• 2lag 3 is an %0bit 4ero flag1 3 is set to % or 5

whenever an instruction is execute

• -ther registers that cannot be directly accessed

by programmer


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Instruction Set• Data movement instructions

• Data operation instructions

• *rogram control instructions


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• !ata movement instruction "or the

Relatively Simple CPU

Instruction #peration

6-* 6o operation

7D/ Γ / # M8Γ 9

.T/ Γ M8Γ 9 # /

M:/ R # /

M-:R / # R

/ ; accumulator register

R ; general purpose register

Γ ,M8Γ 9 ; %0bit memory address


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• 6-* 00 performs no operation

• 7D/ 00 loads data from memory and stores

it in the /

• .T/ 00 copies data from / to memorylocation

• M:/ 00 copies data in / to register R

• M-:R 00 copies data from R to /


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• !ata operation instruction "or the



/DD / # / < R If (/ < R # 5) Then 3 # % &lse 3 # 5

.+= / # / 0 R If (/ 0 R # 5) Then 3 # % &lse 3 # 5

I6/ / # / < % If (/ < % # 5) Then 3 # % &lse 3 # 57/ / # 5 3 # %

/6D / # / ∧ R If (/ ∧ R # 5) Then 3 # % &lse 3 # 5

-R / # / ∨ R If (/ ∨ R # 5) Then 3 # % &lse 3 # 5

>-R / # / ⊕ R If (/ ⊕ R # 5) Then 3 # % &lse 3 # 5

6-T / # /′ If (/′ # 5) Then 3 # % &lse 3 # 5

/ ; accumulator register R ; general purpose register

3 ; 4ero flag


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• Program control instruction "or the



?+M* Γ @-T- Γ

?M*3 Γ If (3 # %) Then @-T- Γ

?*63 Γ If (3 # 5) Then @-T- Γ

3 ; 4ero flag

Γ 00 %0bit memory address


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$oteA

• &ach instruction is having an '0bit instruction

code1

• 7D/ .T/ ?+M* ?+M*3 and ?*63instructions all reBuire a %0bit memory

address represented by %M&

'1 These

instructions each reBuire C bytes in

memory1


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Instruction formats for the RelativelyInstruction formats for the Relatively

Simple CPUSimple CPU

Instruction code7ow0order ' bits of Γ

igh0order ' bits of Γ

byte %

byte $

byte C

&xampleA

$EA ?+M* %$C!

instruction stored in memoryA

$Eth byte $EA 5555 5%5% (?+M*)

$th byte $A 55%% 5%55 (C!)

$Fth byte $FA 555% 55%5 (%$)

00 in hexadecimal format


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(he Algorithm o" the program

)* total # 5 i # 5

+* i # i < %* total # total < i

-* I2 i ≠ n T&6 @-T- +

Ghat exactly this algorithm doing isA %< $ < H < (n ; %) < n

• &xample program using Relatively .imple *+ coding


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(he Relatively Simple CPU coing o" the program

7/.T/ total

.T/ i

7oopA 7D/ i

I6/.T/ i

M:/

7D/ total

/DD

.T/ total

7D/ n

.+=

?*63 7oop

total # 5 i # 5

i # i


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Relatively Simple microprocessors, or CPU

• Designed as an instructional aid and draws its

features from several real microprocessors


personal computer

• It has about the right level of complexity tocontrol a microwave oven or other consumer

appliance


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Instruction Set Architecture (ISA)• Memory Model

• Registers .et

• Instruction .et


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Memory Moel• This microprocessor is a complete '0bit

parallel entral *rocessing +nit (*+)1

• &ach byte has ' bits

• Isolated I,- input and output devices are

treated as being separate from memory1

Different instructions access memory and I,-devices


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Register Set

• /ccumulator A is an '0bit register1• Register . C ! / and 1 are six '0bit

general purpose register1 These registers can be

accessed individually or can be accessed in

pairs1• *airs are not arbitrary .C are a pair (%0 bit)

as are !/ and 1 • Register 1 is used to point to a memory

location1• .tacJ pointer SP is an %0bit register which

contains the address of the top of the stacJ1


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• The sign flag S indicates the sign of a value

calculated by an arithmetic or logical

instruction1• The zero flag 2 is set to % if an arithmetic or

logical operation produces a result of 5

otherwise set to 51

• The parity flag P is set to % if the result of anarithmetic or logical operation has an even

number of %Ks otherwise it is set to 51

• The carry flag C3 is set when an arithmetic

operation generates a carry out1• The auxiliary carry flag AC very similar to

L but it denotes a carry from the lower half of

the result to the upper half1


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• The interrupt mask IM used to enable and

disable interrupts and to checJ for pendinginterrupts


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Instruction Set• Data movement instructions

• Data operation instructions

• *rogram control instructions


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!ata movement instruction "or the 8085 microprocessor


M-: r% r$ r% # r$

7D/ Γ / # M8Γ 9

.T/ Γ M8Γ 9 # /

*+. rp .tacJ # rp (rp ≠ .*)

*+. *.G .tacJ # / flag register

*-* rp rp # .tacJ (rp ≠ .*)

*-* *.G / flag register # .tacJ

I6 n / # input port n

-+T n -utput port n #/

r r% r$ ; any '0bits register Γ , M8Γ 9 ; memory location

rp ; register pair = D& 7 .*(.tacJ pointer)

n ; '0bit address or data value


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!ata operation instruction "or the 8085 microprocessor

Instruction #peration 4lags

/DD r / # / < r /ll

/DD M / # / < M879 /ll

I6R r r # r < % 6ot L

I6 M M879 # M879 < % 6ot LDR n r # r 0 % 6ot L

DR M M879 # M879 0 % 6ot L

>R/ M / # / ⊕ M879 /ll

M* r ompare / and r /ll

M/ / # /′ 6one

L ; carry flag


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Program control instruction "or the

8085 microprocessor


?+M* Γ @-T- Γ

?cond Γ If condition is true then @-T- Γ

/77 Γ all subroutine at Γ

cond Γ If condition is true then call subroutine at Γ

R&T Return from subroutine

Rcond If condition is true then return from subroutine

cond ; conditional instructions

63 (3 # 5) 3 (3 # %) * (. # 5) 6 (. # %)

*- (* # 5) *& (* # %) 6 (L # 5) (L # %)

3 ; 4ero flag . ; sign flag * ; parity flag ; carry flag


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$oteA

• &ach instruction is having an '0bit instruction

code1

• .ome instructions have fields to specify

registers while others are fixed1


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Instruction formats for the RelativelyInstruction formats for the Relatively

Simple CPUSimple CPU

Instruction code

value byte %

byte $

&xampleA$EA M:I r n


$Eth byte $EA 55xxx%%5 (M:I r)

$th byte $A xxxx xxxx (low0order memory)

(o67yte

.pecifies r


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&xampleA$EA M-: r% r$


$Eth byte $EA 5555 555% (M-:)

$th byte $A xxxx xxxx (specifies r%)

$Fth byte $FA yyyy yyyy (specifies r$)

Instruction code

7ow0order ' bits

Digh0order ' bits

byte % byte $

byte C

(hree67yte

&xampleA$EA 7>I rp Γ


$Eth byte $EA 55rp 555% (7>I rp)


$Fth byte $FA yyyy yyyy (high0ordermemory)

&xampleA$EA 7>I rp Γ


$Eth byte $EA 55rp 555% (7>I rp)


$Fth byte $FA yyyy yyyy (high0ordermemory)

.pecifies rp


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(he Algorithm o" the program

)* total # 5 i # 5+* i # i < %

* total # total < i

-* I2 i ≠ n T&6 @-T- +

n < (n 0 %) < H < %

(he 8085 coing o" the program

7D/ n

M-: = /

>R/ /

7oopA /DD =

DR =

?63 7oop

.T/ total

• &xample program using '5'E microprocessor coding

i # n

sum # / ⊕ / # 5

sum # sum < i

i # i 0 %

I2 i ≠ 5 T&6 @-T- 7oop

total # sum


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Analyzing the 8085 ISA

• The '5'E *+Ks instruction set is more

complete than that of the Relatively.imple *+1 More suitable for consumer

appliance1


personal computer


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Avantages o" the 8085s ISA vs9

Relative Simple CPU

• It has the ability to use subroutines

• It can incorporate interrupts and it haseverything the programmer needs in

order to process interrupts1

• The register set for the '5'E is mostly

sufficient thus less coding apply which

will improve tasJ completion1


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• The instruction set is fairly orthogonal1

&1g1 no clear accumulator instruction

!isavantages o" the 8085s ISA• 7iJe the Relatively .imple *+ it

cannot easily process floating point data1


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Summary o" ISA

1. The I./ specifies

a1 an instruction set that the *+ can process

b1 its user accessible registers

c1 how it interacts with memory

$1 The I./ does not specify how the *+ is designed but

it specifies what it must be able to do1

C1 The I./ is concerned only with the machine languageof a microprocessor because *+ only executes

machine language program not any Jind of high0level

program1


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4. Ghen designing an I./ an important goal is

completenessAa1 instruction set should include the instructions

needed to program all desired tasJs1

b1 instruction should be orthogonal minimi4ing

overlap reducing the digital logic without

reducing its capabilities within the *+1

c1 *+ should includes enough registers to

minimi4e memory accesses and improve

performance1

E1 /n I./ should specifies the types of data the

instruction set to process1


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1 /n I./ should specifies the addressing modes each

instruction can use

F1 /n I./ should specifies the format for each instruction


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+, ,-. +, ,-.

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8085 Microprocessor Instruction Set Architecture