8086 Features - 8086 ARCHITECTURE MICROPROCESSORS &INTERFACING The address refers to a byte in memory

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  • 8086 ARCHITECTURE MICROPROCESSORS &INTERFACING

    8086 ARCHITECTURE 8086 Features

     16-bit Arithmetic Logic Unit  16-bit data bus  20-bit address bus – 1,048,576 = 1 meg  16 I/O lines so it can access 64K I/O ports  16 bit flag  It has 14 -16 bit registers  Clock frequency range is 5-10 MHZ  Designed by Intel  Rich set of instructions  40 Pin DIP, Operates in two modes

  • 8086 ARCHITECTURE MICROPROCESSORS &INTERFACING

    The address refers to a byte in memory. In the 8086, bytes at even addresses come in

    on the low half of the data bus (bits 0-7) and bytes at odd addresses come in on the upper

    half of the data bus (bits 8-15).The 8086 can read a 16-bit word at an even address in one

    operation and at an odd address in two operations. The least significant byte of a word on

    an 8086 family microprocessor is at the lower address.

    The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit

    (EU).The BIU fetches instructions, reads and writes data, and computes the 20-bit

    address. The EU decodes and executes the instructions using the 16-bit ALU.

    The BIU contains the following registers:

     IP - the Instruction Pointer

     CS - the Code Segment Register

     DS - the Data Segment Register

     SS - the Stack Segment Register

     ES - the Extra Segment Register

    The BIU fetches instructions using the CS and IP, written CS: IP, to construct the 20-

    bit address. Data is fetched using a segment register (usually the DS) and an effective

    address (EA) computed by the EU depending on the addressing mode.

    The EU contains the following 16-bit registers:

     AX - the Accumulator

     BX - the Base Register

     CX - the Count Register

     DX - the Data Register

     SP - the Stack Pointer

     BP - the Base Pointer

     SI - the Source Index Register

     DI - the Destination Register

  • 8086 ARCHITECTURE MICROPROCESSORS &INTERFACING

    These are referred to as general-purpose registers, although, as seen by their names,

    they often have a special-purpose use for some instructions. The AX, BX, CX, and DX

    registers can be considered as two 8-bit registers, a High byte and a Low byte. This

    allows byte operations and compatibility with the previous generation of 8-bit processors,

    the 8080 and 8085. The 8-bit registers are:

     AX --> AH,AL

     BX --> BH,BL

     CX --> CH,CL

     DX --> DH,DL

    The ALU performs all basic computational operations: arithmetic, logical, and

    comparisons. The control unit orchestrates the operation of the other units. It fetches

    instructions from the on-chip cache, decodes them, and then executes them. Each

    instruction has the control unit direct the other function units through a sequence of steps

    that carry out the instruction's intent. The execution path taken by the control unit can

    depend upon status bits produced by the arithmetic logic unit or the floating-point unit

    (FPU) after the instruction sequence completes. This capability implements conditional

    execution control flow, which is a critical element for general-purpose computation.

    ES

    CS

    SS

    DS

    IP

    AH

    BH

    CH

    DH

    AL

    BL

    CL

    DL

    SP

    BP

    SI

    DI

    FLAGS

    AX

    BX

    CX

    DX

    Extra Segment

    Code Segment

    Stack Segment

    Data Segment

    Instruction Pointer

    Accumulator

    Base Register

    Count Register

    Data Register

    Stack Pointer

    Base Pointer

    Source Index Register

    Destination Index Register

    BIU registers (20 bit adder)

    EU registers 16 bit arithmetic

    ES

    CS

    SS

    DS

    IP

    AH

    BH

    CH

    DH

    AL

    BL

    CL

    DL

    SP

    BP

    SI

    DI

    FLAGS

    AX

    BX

    CX

    DX

    Extra Segment

    Code Segment

    Stack Segment

    Data Segment

    Instruction Pointer

    Accumulator

    Base Register

    Count Register

    Data Register

    Stack Pointer

    Base Pointer

    Source Index Register

    Destination Index Register

    BIU registers (20 bit adder)

    EU registers 16 bit arithmetic

    http://www.answers.com/topic/florida-public-utilities-co

  • 8086 ARCHITECTURE MICROPROCESSORS &INTERFACING

    Most of the registers contain data/instruction offsets within 64 KB memory segment.

    There are four different 64 KB segments for instructions, stack, data and extra data. To

    specify where in 1 MB of processor memory these 4 segments are located the processor

    uses four segment registers:

    Code segment (CS) is a 16-bit register containing address of 64 KB segment with

    processor instructions. The processor uses CS segment for all accesses to instructions

    referenced by instruction pointer (IP) register. CS register cannot be changed directly.

    The CS register is automatically updated during far jump, far call and far return

    instructions.

    Stack segment (SS) is a 16-bit register containing address of 64KB segment with

    program stack. By default, the processor assumes that all data referenced by the stack

    pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register

    can be changed directly using POP instruction.

    Data segment (DS) is a 16-bit register containing address of 64KB segment with

    program data. By default, the processor assumes that all data referenced by general

    registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment.

    DS register can be changed directly using POP and LDS instructions.

    Accumulator register consists of two 8-bit registers AL and AH, which can be combined

    together and used as a 16-bit register AX. AL in this case contains the low order byte of

    the word, and AH contains the high-order byte. Accumulator can be used for I/O

    operations and string manipulation.

    Base register consists of two 8-bit registers BL and BH, which can be combined together

    and used as a 16-bit register BX. BL in this case contains the low-order byte of the word,

    and BH contains the high-order byte. BX register usually contains a data pointer used for

    based, based indexed or register indirect addressing.

    Count register consists of two 8-bit registers CL and CH, which can be combined

    together and used as a 16-bit register CX. When combined, CL register contains the low

    order byte of the word, and CH contains the high-order byte. Count register can be used

    in Loop, shift/rotate instructions and as a counter in string manipulation.

    Data register consists of two 8-bit registers DL and DH, which can be combined together

    and used as a 16-bit register DX. When combined, DL register contains the low order

  • 8086 ARCHITECTURE MICROPROCESSORS &INTERFACING

    byte of the word, and DH contains the high-order byte. Data register can be used as a port

    number in I/O operations. In integer 32-bit multiply and divide instruction the DX

    register contains high-order word of the initial or resulting number.

    The EU also contains the Flag Register which is a collection of condition bits and

    control bits. The condition bits are set or cleared by the execution of an instruction. The

    control bits are set by instructions to control some operation of the CPU.

     Bit 0 - CF Carry Flag - Set by carry out of MSB

     Bit 2 - PF Parity Flag - Set if result has even parity

     Bit 4 - AF Auxiliary Flag - for BCD arithmetic

     Bit 6 - ZF Zero Flag - Set if result is zero

     Bit 7 - SF Sign Flag = MSB of result

     Bit 8 - TF Single Step Trap Flag

     Bit 9 - IF Interrupt Enable Flag

     Bit 10 - DF String Instruction Direction Flag

     Bit 11 - OF Overflow Flag

     Bits 1, 3, 5, 12-15 are undefined

  • SEGMENT REGISTERS MICROPROCESSORS & INTERFACING

    SEGMENT REGISTERS

    It is used to store the memory addresses of instructions and data. Memory

    Organization. Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1 Meg

    of addressable memory. Addresses are expressed as 5 hex digits from 00000 – FFFFF.

    1. Problem: But 20 bit addresses are TOO BIG to fit in 16 bit registers?

    Solution: Memory Segment.

    Block of 64K (65,536) consecutive memory bytes. A segment number is a 16 bit

    number. Segment numbers range from 0000 to FFFF. Within a segment, a particular

    memory location is specified with an offset. An offset also ranges from 0000 to FFFF

    Memory Model for 20-bit Address Space

    Question: how to generate memory address?

    Ans: Physical address = segment address*10+offset address

  • SEGMENT REGISTERS MICROPROCESSORS & INTERFACING

    Example: we have segment no 6020h and offset is 4267h then 60200+4267=64467h

    physical address.

    Memory:

    Program, data and stack memor