A 2.4-GHz Radio Front End in RF System-on-Package Technology

S. Chakraborty, K. Lim, A. Sutono, E. Chen, S. Yoo, A. Obatoyinbo, S.-W. Yoon, M. Maeng, M.F. Davis, S. Pinel, J. Laskar

In recent years, there has been a great deal of interest in re-alizing low-power, low-cost, compact RF front end mod-ules for Bluetooth technology in the 2.4-GHz industrial,

scientific, and medical (ISM) band. Low-temperature cofiredceramic (LTCC) technology is well suited for compact wire-less transceiver module realization and is becoming increas-ingly popular for wireless local area network (WLAN)applications. However, it is quite challenging to integrate theantenna with modules for WLAN applications at 2.4-GHzdue to their large size and isolation constraints at higher out-put powers. Commercial implementations of Bluetooth usingsystem-on-chip (SOC) technology [1], [2] provide outputpower levels of 0 and 4 dBm, respectively. The system-on-package (SOP) approach allows the development ofhigh-quality passive components on ceramic substrates,thereby providing much higher output power levels (20dBm). The choice of proper radio architecture and sharing ofground plane among LTCC passive components enables com-pact implementation of the RF front end (Figure 1).

Most of today’s wireless LAN solutions aim for very lowintermediate frequency (VLIF) [4] RF architectures forbetter integration of integrated circuits (ICs) in commonlyavailable semiconductor processes. For an IF frequency athalf the channel bandwidth (500 kHz), the image becomesan adjacent channel according to Bluetooth specifications[3], thus leading to a looser image rejection specification. Inthis article we present the development of complimentarymetal-oxide-semiconductor (CMOS) monolithic micro-wave integrated circuits (MMICs) and LTCC multilayerpassive components. These building blocks are then inte-grated in an LTCC substrate, and an antenna is imple-mented in the same package.

TechnologiesA 0.24-µm CMOS technology has been used in conjunctionwith commercially available LTCC technology for the com-plete SOP solution.

0.24-µm CMOS TechnologyThe 0.24-µm p-substrate twin-well CMOS technology is simi-lar to most commercially available deep-submicron CMOStechnologies. The sheet resistance of the silicon substrate isapproximately 10 Ω-cm. It is a five-metal-layer process, andthe gate is salicided to reduce gate resistance and transistor

noise. In addition to the gate poly, a second poly layer isavailable for implementation of poly-oxide-poly capacitors.

LTCC TechnologyThere are several potential technologies available for the devel-opment of wireless SOP architecture. Multilayer LTCC andhigh temperature cofired ceramics (HTCC) technologies canconsist of as many as 50-60 stacked ceramic tapes and are excel-lent candidates due to the availability of large number of layersand reasonable loss performance. They are currently the mostsuitable technologies to implement RF-SOP architecture.

The LTCC process offers screen-printing and low-lossstacked via processes as well as high conductivity metalizationuseful for high frequency applications [5]. Table 1 provides asummary of some widely used LTCC and HTCC materialsand their properties supplied by the manufacturers. Tradi-tionally developed for low-frequency analog mixed-signalpackaging schemes, the LTCC process has been adopted asone of the high-volume SOP technologies for emerging wire-less applications [5].

MMIC DesignPower AmplifierDue to the constant envelope nature of the Gaussian-fre-quency shift keying (GFSK) modulation scheme, theBluetooth power amplifier does not have strict linearity re-quirements. The power amplifier uses a compact three-stagecascade topology. The load-impedance design is based on theload-pull measurement on the power transistor [6]. Thispower amplifier utilizes on-chip input matching. The outputmatching is realized in LTCC multilayer high-Q passive ele-ments. Measurement results of the power amplifier show anoutput power of 20 dBm and a power-added efficiency of20%. The power amplifier is biased at class-AB and exhibitsan output 1-dB compression point of 16.8 dBm. It utilizes a2.4-mm (40 fingers with 60-µm gate width) device size. Figure2 shows the output power as a function of the input power ofthe power amplifier (PA).

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S. Chakraborty, K. Lim, S.-W. Yoon, M. Maeng, M.F. Davis, S.Pinel, and J. Laskar are with Georgia Institute of Technology in At-lanta, Georgia, USA. A. Sutono and S. Yoo are with RF Solutions inAtlanta, Georgia, USA. E. Chen is with National SemiconductorCorp. in Atlanta, Georgia, USA. A. Obatoyinbo is with Hughes Re-search Lab in Malibu, California, USA.

CMOS MMICs

From IF

To IF

Passives (LTCC)180°

Figure 1. Front-end transceiver architecture.

Low-Noise AmpliferThe low-noise amplifier (LNA) has been designed using acascode topology. Use of a cascode topology helps in separateoptimization of input and output networks, better stability,and better high-frequency operation due to minimization ofthe Miller capacitor effect. It uses n-channel metal-oxide-semiconductor (NMOS) transistors of 250-µm width toachieve low-noise performance. Output matching was opti-mized to achieve high gain and high third-order input inter-cept point (IIP3) simultaneously. The LNA has a noise figureof 3 dB, gain of 11 dB, and IIP3 of −1 dBm at 2.45 GHz.

Up/Down Converting MixerDoubly balanced Gilbert cell topology has been chosen for theup/down conversion mixer. Biasing the mixer core field-ef-fect transistors (FETs) near threshold allows reduced local-os-cillator (LO) power for driving the FETs like ideal switches.Two such balanced mixers, with their LO in quadrature, gen-erate a polyphase signal that can be used for image rejection.It uses NMOS transistors of 250-µm width for achieving thedesired gain from the mixer. It provides a gain of 2 dB and aIIP3 of 0 dBm at −5 dBm of LO power. The LO to IF isolation isgreater than 40 dB. Figure 3 shows a picture of the fabricatedchipset used in the module.

Design of Passives and Module IntegrationBandpass FilterA significant portion of the total development cost of a trans-ceiver module is expended on this front-end filter, which istypically realized by discrete components. Integrating the fil-ter-on-package is an attractive option, especially with theavailability of multi-level dielectric systems, such as that of-fered by the LTCC process. There are two potential advan-tages: first, miniaturization is possible by the verticaldeployment of filter elements since there are a large numberof dielectric layers available; and second, integration essen-tially eliminates the need for a discrete filter and, therefore, re-duces the component and assembly cost.

An LTCC-integrated pre-select two-resonator bandpassfilter has been designed, developed, and characterized [7].The filter utilizes a stripline lumped element topology to -

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30

20

10

0

–10

–20

–30

–40

Out

put P

ower

(dB

m)

–20 –15 –10 –5 0 5 10 15Input Power (dBm)

Figure 2. Typical measured output power versus input power ofa power amplifier fabricated using CMOS/LTCC technologies.

Table 1. Summary of LTCC/HTCC materials and their properties.

MaterialDielectricConstant

LossTangent

ThermalConductivity(W/m ⋅ K)at 293 K

CTE (1/°C)at 25-200 °C

Tapethickness(mils)

Metalization

HTCC9.6(1 MHz)

0.0015(1 MHz)

23 7.2 × 10-6 4-20 Tungsten

Dupont951 AT

7.8(1 MHz)

0.0015(1 MHz)

3 5.8 × 10-6 5-8.3 Silver/Gold

Dupont943 AT

7.5(1 MHz)

0.0005(1 MHz)

3 5.3 × 10-6 5-8.3 Silver/Gold

Ferro A6-M5.9(10 MHz)

< 0.002(10 MHz)

3 7 × 10-6 3.7-7.4 Silver/Gold

(a)

(c) (d)

(b)

Figure 3. Die photographs of chipset used in the module: (a) PA(0.75 × 0.75 mm), (b) filter (3.8 × 2.4 × 0.5 mm), (c) LNA (1.5 × 1mm), and (d) mixer (1.5 × 1.5 mm).

allow compact implementation. The schematic is shown in [7],and the circuit was implemented with six layers of LTCC tapein a stripline configuration whose three-dimensional (3-D)view is illustrated in Figure 4(a). To help visualize how the fil-ter is deployed, a cross-sectional view along AA’ in Figure 4(a)is drawn in Figure 4(b). Layers 6 and 0 are the top and bottommetalizations that serve as the top and bottom ground planes.The shunt inductors L1 and L2 were realized by the U-shaped

strips fabricated on layers 4 and 3 that are located two- andthree-layers underneath the top ground plane, respectively.The end of the strips are connected to both grounds throughvias. There is no metalization between layers 4 and 6, there-fore, the top inductor strip on layer 4 is 7.2-mils (two layers)away from the top ground plane while the bottom strip is10.8-mils (three layers) away from the bottom ground plane.The required mutual inductive coupling is achieved by over-lapping the L1 and L2 strips that are one-layer (3.6-mils) apart.Metal-insulator-metal (MIM) capacitors, with electrodes onlayers 4 and 3 laid out beside the inductor strips, were utilizedto implement CI and CO [Figure 4(a)]. The rectangular plateson layers 4 and 3 serve as the top and bottom plates, respec-tively, of CI and CO. The vertically interdigitated capacitor(VIC) topology was utilized to implement CS, which is real-ized by two series capacitors of capacitance 2 CS. Each of thesecapacitors is implemented in VIC topology as a parallel com-bination of two capacitors with a value of CS. This is depictedmore clearly in the cross-sectional view [Figure 4(b)], showingVICs deployed on layers 3, 2, and 1 right underneath CI andCO. Such implementation ensures the symmetry of the struc-ture desirable for high-frequency circuits. If CS were imple-mented in MIM topology, the entire structure would not havebeen symmetrical. The bottom plates of CI and CO are used asthe top plates of the VIC extended to layer 2 through via con-nections. The dumbbell-shaped trace is inserted on layer 2,between layers 3 and 1, as the bottom plates of the VIC. Theplates on layer 4, connected to layer 2 and the plates on layer3, implements CS’ [Figure 4(b)]. The extended top plates of theVIC on layer 1 are used as the top MIM electrodes for theshunt capacitor CR with the bottom ground on layer 0 as thebottom electrode. The filter has a size of 3.8 × 2.4 × 0.5 mm.This filter exhibits a measured insertion loss of 3 dB at 2.4GHz, 3-dB bandwidth of 270 MHz, and return loss of 22 dB. It

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Layer 6

Layer 4

Layer 3

Layer 2

Layer 1

Layer 0

A A′

Port 1Port 2

Layer 6

Layer 4

Layer 3

Layer 2

Layer 1

Layer 0

Ground Plane

Port 1 Port 2

(a)

(b)

L1

L2MCI

CR CR

CO

ViaCS′

CS′ CS′

CS′

Figure 4. (a) A 3-D layer-by-layer view of a lumped-elementmultilayer image reject filter structure. (b) A cross-sectional viewalong AA’ in (a) indicating how each element in the filter sche-matic is deployed.

Layer 0

Layer 1

Layer 2

Layer 3

Layer 4

Port 2Port 1

Port 3

(A)

(C)

(B)

Figure 5. Exploded view of multilayer LTCC balun.

also exhibits a constant group delay characteristic over the en-tire Bluetooth band.

BalunThe balun has been implemented using a multilayer couplingstructure, occupying a total of five dielectric layers (Figure 5).Two shorted transmission lines (A and B) are placed next to anopen-circuited line (C) such that they couple energy from theopen circuited line that has a length of half a wavelength atthe desired frequency. This being the case, a standing wavewill form a short circuit at the center of the open-circuited line.Here, the current will be at its maximum value. At equal dis-tances away from the center and on either side of it, the volt-age will be equal in magnitude but in opposite phases. Thetwo short-circuited line sections are coupled from both endsof the open-circuited line. Therefore, a signal incident at port 1induces signals at port 2 and port 3 with equal amplitudes butopposite phases. The short-circuited lines have to be approxi-mately a quarter-wavelength long in order to achieve the de-sired characteristics.

Shown in Figure 5, two ground planes (layers 0 and 4) areconnected by vias to ensure that they are at the same poten-tial, and the two output-coupling sections are on layers 1 and3 for effective isolation. It exhibits a return loss of better than22 dB at 2.4 GHz and insertion loss of 3.75 dB at 2.4 GHz. Am-plitude imbalance is less than 0.1 dB, and phase imbalance isless than 3° over the 2.1-3-GHz range. The measured charac-teristics of the balun are shown in Figure 6.

Antenna with Integrated ModuleThe antenna utilizes a 3-D loop structure with a vertically em-bedded loop radiator in 20 LTCC layers for compactness andintegration in the same package. A microstrip-transmissionline is used for the antenna feed. To minimize the interference

between the antenna and other components inside thepackage, a vertical ground wall using a row of vias has beeninserted between the radiator and transceiver. The groundplane of the microstrip transmission-line feed is implementedon layer 18 of the LTCC substrate. The antenna has a size of 31× 14 × 1.8 mm but can be further optimized by meandering thevertical loop radiator. The measured input-return loss of theantenna is shown in Figure 7 and is 20 dB at 2.3 GHz. It showsa return loss of −20 dB at 2.3 GHz. This drift from the desiredfrequency can be caused by a finite dielectric effect that wasnot considered in this method of moment simulation.

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0

–5

–10

–15

–20

–25

–30

S11

(dB

)

0 1 2 3 4 5

Frequency (GHz)

dbS11dbS21dbS31

Figure 6. Measured insertion loss and return loss of balun.

S11

(dB

)

0

–5

–10

–15

–20

–252 2.2 2.4 2.6 2.8 3

Frequency (GHz)

Figure 7. Measurement result of antenna return loss.

PA

SwitchMixer

LNA

LoopAntenna

Embedded FilterEmbedded Balun

Figure 8. 3-D view of developed module: CMOS transceiverMMICs (LNA, PA, mixer) are on the top layer connected by viastructures to embedded passives in LTCC. Loop antenna is sepa-rated by ground plane.

Table 2. Summary of specifications of building blocks.

RF Building Blocks Performance

Filter

Topology: bandpassCenter frequency: 2.4 GHzInsertion loss: 3 dBReturn loss: 22 dBAttenuation at image frequency: 22 dBSize: 3.8 × 2.4 × 0.5 mm

Balun

Topology: coupling, merchand balunInsertion loss: 3.75 dB at 2.4 GHzReturn loss: 22 dB at 2.4 GHzAmplitude imbalance: < 0.1 dB between 2.1- 3 GHzPhase imbalance: <3° between 2.1-3 GHz

AntennaTopology: vertical-loop radiatorReturn loss: 20 dB at 2.3 GHz

Power amplifier

Topology: class ABFrequency: 2.4 GHzOutput P1-dB compression: 16.8 dBmOutput power: 20 dBmPower-added efficiency: 20%

Low-noise amplifier

Topology: cascodeGain: 11 dBNoise figure (with respect to 50Ω): 3 dBIIP3: −1 dBm

MixerTopology: Gilbert cellGain: 2 dBIIP3: 0 dBm at LO power of −5 dBm

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An exploded 3-D view of the developed module is shown inFigure 8. The same filter has been used in transmit and receivepaths to save space. Table 2 shows the specifications of each ofthe building blocks in detail. The MMICs are connected to theembedded passive structures by via interconnections.

ConclusionWe have demonstrated the development of an integrated20-dBm 2.4-GHz transceiver module using 0.24-µm CMOSMMICs and multilayer LTCC technology. The developmentof compact high-performance passive components has beendemonstrated in a multilayer SOP approach. The choice ofproper filter position and antenna integration in the samemodule helps to reduce size and cost and improves perfor-mance. This approach can be extended further towards thedevelopment of multi-mode receivers in the 2.4-GHz ISMband that would potentially be able to support the coexis-tence of different wireless standards of interest.

AcknowledgmentsThe authors acknowledge the support of National Semicon-ductor Corp., Yamacraw Design Center, and the Packaging

Research Center for assistance in fabricating the developedICs. Special thanks go to William O. Keese and MichaelSchwartz for their technical assistance.

References

[1] PBA 313 04, Bluetooth radio. Available: http://www.ericsson.com

[2] BlueCore 01., Single chip Bluetooth system. Available:http://www.cambridgesiliconradio.com

[3] B.SIG, Specification of the Bluetooth system, core. Available:http://www.bluetooth.com

[4] J. Glib, “Bluetooth radio architectures,” in 2000 IEEE Radio Frequency Inte-grated Circuits Symp. Dig., , pp. 3-6.

[5] D.I. Amey, S.J. Horowitz, and R.L. Keusseyan, “High frequency electricalcharacterization of electronic packaging materials: Environmental andprocess considerations,” in 4th Int. Symp. and Exhibition Adv. PackagingMaterial Dig., Braselton, GA, 1998, pp.123-128.

[6] E. Chen, D. Heo, M. Hamai, J. Laskar, and D. Bien, “0.24-µm CMOS Tech-nology for Bluetooth Power Applications,” in Proc. IEEE Radio and Wire-less Conf., 2000, pp. 163-166.

[7] A. Sutono, J. Laskar, and W. R. Smith, “Development of integratedthree-dimensional Bluetooth image reject filter,” in 2000 IEEE MTT-S Int.Microwave Symp. Dig., vol. 1, pp. 339-342.

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