AC Boundary-scan Specification for IEEEgrouper.ieee.org/groups/1149/6/doc/IEEE_ACJTAG_B5a.pdfAC Boundary-scan Specification for IEEE Document EDCS-134568 Rev B5 Page 3 of 22 Cisco

AC Boundary-scan Specification for IEEE Document EDCS-134568 Rev B5 Page 1 of 22

Cisco Systems, Inc. For AC Boundary-Scan Standard Activity A printed copy of this document is considered uncontrolled. Refer to the online version for the latest revision.

Document Number: EDCS-134568 Revision: Rev B5 Originator: Sung Chung Sang Baeg Department: GSM ASIC DFT Group Contact information www.acextest.org

[email protected]

AC Boundary-scan Specification for IEEE

Approvals

Department Name Approval Date

Mfg Technology Pandu Sharma Signed 00/00/00

ASIC Technology Paul Ruddy Signed 00/00/00

Test Technology Greg Jordan Signed 00/00/00

Modification History

Rev RCN #

Date Originator Comments

B 0-B2 10/16/00 Sung Chung, Sang Baeg Initial Release and added clarification

B 3 4/16/01 Sung Chung, Sang Baeg Add examples and clarifications

B 4 5/10/01 Sung Chung, Sang Baeg, Pandu Sharma, Ted Eaton

Add test coverage and certification section

B5 3/27/02 Sung Chung Add Input Test Buffer examples, AC_Sync signal generation circuit, and minimum TCK in BSDL



AC Boundary-scan Specification for MSA

1. Introduction This document outlines AC boundary-scan design specification for the Multi-Source Agreement

(MSA) partners for parallel optics based transmit and receive modules and associated component vendors.

2. Overview of technology AC boundary-scan has two parts: the “AC_EXTEST” instruction and “AC Boundary-scan cell”. When

there is a coupling capacitor within the given net, the AC_EXTEST instruction and a properly equipped AC boundary-scan cell allows for the testing of such a net.

As in the mandatory EXTEST instruction defined in the IEEE 1149.1 Standard, data would typically be loaded onto the latched parallel outputs of boundary-scan shift-register stages using the PRELOAD instruction. The AC boundary-scan register cells located at system output pins (2-state, 3-state, or bi-directional) generate AC patterns in the Run-Test/Idle controller state with the AC_EXTEST instruction selected. The AC pattern’s logic state is sampled at the system input pins in the Run-Test/Idle controller state within a predefined sample interval. The sampled value within the input AC Boundary-scan cell is loaded onto the boundary-scan Capture register cell on the rising edge of TCK in the Capture-DR controller state. Typical ways of evaluating the test result are identical to the current EXTEST instruction.

3. The AC_EXTEST Instruction The public AC_EXTEST instruction allows testing of AC coupled or DC de-coupled board level

interconnects. The AC_EXTEST instruction is a super set of the mandated EXTEST instruction and the AC boundary-scan cell is backward compatible with the mandated EXTEST instruction. When the AC_EXTEST instruction is selected, the boundary-scan register cells determine the state of all system output pins. 3.1 Specification 3.1.1. Rules

a) Each component implementing the AC_EXTEST instruction shall provide the EXTEST instruction.

NOTE – This implies the component with the AC_EXTEST instruction shall work with

currently available IEEE 1149.1 Standard compliant components when the test uses only the EXTEST instruction. However, the component running the AC_EXTEST instruction may not work properly with legacy component running the EXTEST instruction during test.



b) Each component implementing the AC_EXTEST instruction shall meet all the Rules of the EXTEST instruction “Specifications” in the IEEE 1149.1 Standard the EXTEST with instruction selected.

c) When the AC_EXTEST instruction is selected, the AC patterns generated and driven from the system output pins shall be executed only in the Run-Test/Idle controller state.

d) The AC Pattern applied by the AC boundary-scan cell shall have a continuous stream of alternating logic patterns, and a repeating 1010 (or 0101) pattern shall be used as logic 1 (or logic 0).

NOTE – The AC pattern generated shall toggle its value on every rising edge of TCK. e) When the AC_EXTEST instruction is selected, the AC patterns received at the system

input pins shall be sampled only in the Run-Test/Idle controller state. f) The AC pattern shall be sampled at the system input pins every 16th AC pattern cycle on

the falling edge of TCK. The sampled value shall be the same value as the data being held in the driving AC boundary-scan register cell at the system output pins.

NOTE – The “AC pattern cycle” changes on every rising edge of TCK. NOTE – Every 16th AC pattern cycle is referred to as the “AC pattern sample interval”.

g) When the AC_EXTEST instruction is selected, the value of the AC patterns sampled at

the system input pins in the Run-Test/Idle controller state shall be loaded into the boundary-scan capture register cell on the rising edge of TCK in the Capture-DR controller state.

NOTE – The sampled value of the AC pattern is stored in the AC pattern hold register cell,

located in the system input pins.

h) The system output pins running the AC_EXTEST instruction shall operate as the EXTEST instruction if the TAP controller is not in the Run-Test/Idle controller state.

i) Duration of time in the Run-Test/Idle controller state shall be specified for the test executed in response to the AC_EXTEST instruction (e.g., a number of rising edges).

NOTE - The usage of the AC patterns during the INTEST instruction in not defined.

3.1.2 Recommendation

a) Each component implementing the AC_EXTEST instruction should meet all the recommendations of the EXTEST instruction specified in the IEEE 1149.1 standard when the TAP controller goes directly to the Capture-DR controller state without passing through the Run-Test/Idle controller state after each Update-DR or Update-IR with the AC_EXTEST instruction selected.

b) The AC patterns being applied at the system output pins during the first AC pattern cycle after TAP controller has entered into the Run-Test/Idle controller should be the



complement of the data held in the boundary-scan register cell at the system output pins. Thus every 16th cycle of the AC pattern shall produce the pattern that matches with logic value of the data held in the boundary-scan register cell at the system output pins.

3.1.3 Permissions

a) The component designer may select the binary value(s) for the AC_EXTEST instruction. b) The AC pattern generation circuit may take more than one AC pattern cycle to begin

generation of the AC patterns after the TAP controller has entered into the Run-Test/Idle controller state, but it may not take more than one AC pattern sample interval.

c) A special control cell may be added to disable the AC pattern generation function of an AC Boundary-scan cell when the AC_EXTEST instruction is selected. Once the cell is in the AC_EXTEST instruction disabled state, it shall operate as the EXTEST instruction.

3.1.4 Description

The EXTEST instruction allows circuitry external to the component package - typically the

board interconnect or substrate interconnect – to be tested. The boundary-scan register cells at the output pins apply test stimuli, while those at input pins capture test results. The AC_EXTEST instruction allows boundary-scan cells at the output pins to apply AC test stimuli in the Run-Test/Idle controller state. At the same time, the input pins sample a single bit from the incoming AC test stimuli at predetermined TCK cycles in the Run-Test/Idle controller state. The AC pattern sample interval repeats every 16th cycle of the AC pattern cycle. The sampled value of the AC pattern is stored in the AC pattern hold register cell located at the system input pins. The data is transferred to the boundary-scan capture register cell on the rising edge of TCK in the Capture-DR controller state. The duration of time in the Run-Test/Idle controller state determines how many times the incoming AC patterns will be sampled at the system input pins during AC_EXTEST.

The steps required to complete the execution of the AC_EXTEST instruction are outlined in the

following example. a) Preload stimulus: shift test stimulus into the boundary-scan registers using the PRELOAD

instruction. The description section of the EXTEST instruction in the IEEE 1149.1 Standard provides typical methods of applying test stimulus to the boundary-scan register using the PRELOAD instruction.

b) Initiate the AC_EXTEST instruction: scan the AC_EXTEST instruction into the instruction register.

c) Execute the AC_EXTEST instruction: cause the TAP controller to remain in the Run-Test/Idle controller state for the duration required to complete execution of the AC_EXTEST instruction. The AC patterns are being generated and applied from the system output pins and the AC pattern signals are being sampled at the system input pins every 16th cycle of AC pattern cycles on the falling edge of TCK. The sampling continues as long as the TAP controller remains in the Run-Test/Idle controller state. The sampled value of the AC pattern is stored in the AC pattern hold register cell located at the system input pins.



d) Transfer the AC_EXTEST instruction results: upon passing through the Capture-DR controller state, the AC patterns sampled at the system input pins in the Run-Test/Idle controller state will be loaded into the boundary-scan capture register cell on the rising edge of TCK.

e) Evaluate the AC_EXTEST results: bring the TAP controller to the Shift-DR controller state and scan out the test results from the boundary-scan registers. The “Description” section of the EXTEST instruction in the IEEE 1149.1 Standard provides typical methods of evaluating the test result.

NOTE - Upon exiting the AC EXTEST instruction, the state of the update registers held by the

last Update-DR controller state should be restored. When the AC_EXTEST instruction is selected, the system output pins follow rules set by the

EXTEST instruction, except for the system output pins with the AC boundary-scan cells. Pins equipped with an AC boundary-scan cell apply an AC pattern in the Run-Test/Idle controller state, instead of a steady state logic level as in the EXTEST instruction.

When both the EXTEST and the AC_EXTEST instruction are used during the boundary-scan

test, the AC_EXTEST instruction shall provide the following cases of interoperability. a) Both the system output pins and the system input pins are interconnected and are under the

AC_EXTEST instruction. The test shall work properly regardless of AC coupling between the interconnection.

b) If there is no AC coupling between the two devices, the system output pins under the EXTEST instruction shall operate with the system input pins under the AC_EXTEST instruction.

c) The system output pins under the AC_EXTEST instruction shall operate as the EXTEST instruction if the TAP controller is not in the Run-Test/Idle controller state.

NOTE - It is possible to perform the EXTEST operation if the TAP controller goes directly to

the Capture-DR controller state without passing through the Run-Test/Idle controller state after each Update-DR or Update-IR with the AC_EXTEST instruction selected.

The system input pins under the EXTEST instruction may not perform the test properly with the system output pins under the AC_EXTEST instruction and should be avoided.



3.1.5 Timing Diagrams

TCK =AC Pattern

Clock

AC Pattern

Run-Test/IdleTAP State

AC_Sync

AC Pattern Clock Cycle

AC Pattern Cycle

Run/Test Idle Duration

AC Pattern Sample Interval = Every 16th AC Pattern Cycle

1st AC Pattern Cycle 16th AC Pattern Cycle

Next AC PatternSample Interval

Figure 1: Example timing diagram of critical signals

Figure 1 provides the relative relationship between various signals and clocks used in this

Specification. An example view of a more complete set of timing diagrams using the same naming convention is given in Figure 2.

AC_Sync

TCK

AC Pattern = 1

Run-Test / Idle

AC Pattern = 0

Figure 2: Example timing diagram of critical signals

Figure 2 shows relationship between “TCK”, “AC Pattern”, and “AC_Sync” in an ideal situation. The

“TCK” in the Figure is the AC pattern clock and produces “AC Pattern”. The “AC_Sync” signal is derived from “TCK” and “TCK” is a boundary-scan TCK clock.



4. Boundary-scan cell examples The AC boundary-scan cell can have a predefined function of BC_0 to BC_10 as specified in the IEEE

1149.1 Standard. The AC boundary-scan cells and AC boundary-scan capable TAP controller allow the AC pattern generation and sampling capability. 4.1 Boundary-scan Cell examples

Figures 3 to 11 show examples of AC capable boundary-scan cells and various mode signals. The

“AC_Test” mode signal is a function of the AC_EXTEST instruction and the Run-Test/Idle controller state. It becomes active when TAP controller is in the Run-Test/Idle controller state with the AC_EXTEST instruction selected. The AC pattern generation and pattern sample logic use a common clock known as “AC pattern clock”, shown here as “AC_Pattern_Clock”, to synchronize pattern generation and sample operations. The TCK is used as the AC pattern clock. The “AC_Test_Marker” is a single one and a half AC pattern clock cycle positive going pulse used to mark the beginning of the AC pattern generation sequences.

Clk

D

Q

Q

Clk

D Q

AC_Test

AC_Pattern_Clock AC_Test_Marker

Clk

D Q

Figure 3: Example signal – AC_Test_Marker marks start of the AC_EXTEST

The “AC_Test_Marker” is used to set the pattern generation flip-flop with a known value. Subsequent patterns generated by “AC_Pattern_Clock” become the “AC_Pattern_Source”. The “AC_Pattern_Source” is combined with each boundary-scan Update register cell to generate the appropriate pattern sequences.

Clk

D

Q

QS

AC_Test_Marker

AC_Pattern_Source

AC_Pattern_Clock

Figure 4: Example signal – AC_Pattern_Source is an alternating test pattern source

The “AC_Test_Marker” is also used to set the AC_EXTEST history flip-flop to a known value. Setting

it to logic “1” signifies the AC_EXTEST has been executed at the Run-Test/Idle controller state. It clears status to logic “0” with “UpdateDR” or “Reset” to signify that the AC_EXTEST instruction has



completed operation with Capture-DR and subsequent Update-DR, or that the AC_EXTEST instruction has not been executed in the Run-Test/Idle controller state. The “Reset” is TAP controller TRST signal. The “AC_Test_Ran” signal is used to control the input AC boundary-scan register cells to capture directly from the system input pins instead of capturing from the AC pattern hold register cells. In special cases where the AC_EXTEST instruction is executed without going to the Run-Test/Idle controller state, the “AC_Test_Ran” signal will force the input AC boundary-scan register cells to act like a DC scan cells.

Clk

D

Q

QS

AC_Test_Marker

AC_Test_Ran

UpdateDRR

Reset

Logic Low

Figure 5: Example signal – AC_Test_Ran flags run status of the AC_EXTEST

Figure 6 shows one of the ways to generate the AC_Sync signal from the AC_Test and the AC_Pattern_Clock.

Clk

D Q

AC_Test

AC_Pattern_Clock Clock

Reset

Divide by 32

AC_Sync

Figure 6: AC_Sync signal generation example

Figure 7 shows how to feed a parallel pattern, the “AC_Pattern_Source”, to the output AC boundary-scan register cell. The “AC_Pattern_Source” is further conditioned by the Update boundary-scan register cell. The value is inverted if the Update scan cell has EXTEST value of logic “0” otherwise it is fed directly to the system output pin without change.

AC_Pattern_Clock

1

0

1

0

Clk

D

Q

Q

Data fromsystem logicFrom last cell

ShiftDR

UpdateDR

AC_TestDC_Mode

To next cell To systempin

Clk

D Q1

0

AC_Pattern_Source

Capture Cell Update Cell

Figure 7: Example output AC boundary-scan cell BC_1



Figure 8 shows an AC scan cell with built-in AC pattern generator that generates AC patterns with “AC_Pattern_Clock” using a boundary-scan Capture register cell. First, the EXTEST value from the Update scan cell is copied into boundary-scan Capture register cell with “AC_Test_Marker” and “AC_Pattern_Clock”. Subsequently, “AC_Pattern_Clock” starts the AC pattern generation and the patterns are fed into the system pin. “AC_Pattern_Clock” or “ClockDR” in this design is a shared clock signal for both AC pattern generation and the capturing and shifting of boundary-scan test signals.

AC_Pattern_Clockor ClockDR

1

0

1

0

Clk

D

Q

Q1

01

0

Data fromsystem logic

From last cell

ShiftDR

UpdateDR

AC_Test

DC_Mode

To next cell To system pin

1

0

Clk

D Q

AC_Test_Marker

AC_Test


Figure 9 provides similar methodology as the one shown in Figure 8, but it uses “AC_Test_Marker” to

set the Capture scan cell to a known state before AC pattern generation. Once the pattern is generated, the circuit uses a method similar to that in Figure 7 to drive the pattern to the system output pin. “AC_Pattern_Clock” or “ClockDR” in this design is a shared clock signal for both AC pattern generation and the capturing and shifting of boundary-scan test signals.

AC_Pattern_Clockor ClockDR

1

0

1

0

Clk

D

Q

Q

Clk

D

Q

Q1

01

0S

AC_Test_Marker

Data fromsystem logicFrom last cell

ShiftDRAC_Test

UpdateDRAC_Test

DC_Mode

To next cellTo system pin


The examples shown from Figure 7 to Figure 9 are boundary-scan register cell type BC_1 and maintain compatibility with existing EXTEST. These AC boundary-scan register cells can be mixed in a design with any IEEE 1149.1 Standard compatible device.



Figure 10 shows an example input scan cell with AC_EXTEST capability. There is an extra AC pattern

hold register cell and “AC_Sync” signal. When the “AC_Test_Ran” signal becomes active, signifying AC_EXTEST has been executed under the Run-Test/Idle controller state, the Capture scan cell captures the value of the AC pattern hold register cell; otherwise it captures value from the system input pin. The capture source selection is controlled by the signal “AC_Test_Ran”.

When repeating 1010 or 0101 pattern is used as logic “1” or logic “0” respectively and the AC pattern

is sampled at every 16th cycle of the AC pattern cycle as defined by this Specification, the AC pattern generation and the AC pattern sampling are controlled by TCK. As specified in this Specification, the sampled patterns are always the same as the expected value of the current EXTEST.

Clk

D Q 1

0

1

0

1

0

Clk

D Q

Clk

D Q

AC_Test_Ran

Data tosystemlogic

From last cell

To next cellFrom

systempin

AC_Sync

DC_ModeUpdateDR

ClockDRShiftDR

Capture Cell Update CellAC PatternHold Cell

Figure 10: Example input AC boundary-scan cell BC_1

The Figure 11 shows a simplified observe only version of the input AC boundary-scan cell in Figure 10.

Clk

D Q 1

0

1

0

Clk

D Q

AC_Test_Ran

Data tosystemlogic

From last cell

To next cellFrom

systempin

AC_Sync

ClockDRShiftDR

Figure 11: Example input AC boundary-scan cell BC_4

Figure 12 shows an output AC boundary-scan cell with the optional AC_EXTEST disable control feature. The “AC_EXTEST Control Cell” is of the cell type “internal” in the BSDL description, and has both Capture and Update boundary-scan register cells. If the “AC_EXTEST Control” Update cell has a



logic value of “1” during AC_EXTEST, the output AC boundary-scan cell will perform AC_EXTEST. However, if the cell has a logic value of “0” during AC_EXTEST, the output AC boundary-scan cell will function as if the EXTEST instruction is selected by suppressing the AC_EXTEST function from the output AC boundary-scan cell. In this example, logic value “0” for the “AC_EXTEST Control Cell” will be the disable value for the AC_EXTEST function, and logic value “1” will be the safe value for the AC_EXTEST function since it enables the intended AC_EXTEST function. An additional reset signal to the Update cell of the “AC_EXTEST Control” may be added to ensure default functionality of either the AC_EXTEST or EXTEST after TAP controller reset.

AC_Pattern_Clock

1

0

1

0

Clk

D

Q

QOutput Data

ShiftDR

UpdateDR

AC_Test

Mode

Tosystem

pin

1

0

AC_Pattern_Source

BC_1Output Cell

BC_1

ClockDR

UpdateDR

To next cell

Clk

D Q

Clk

D Q

AC_EXTEST Control Cell

From last cell

Clk

D Q

Figure 12: Example output AC boundary-scan cell with AC_EXTEST control cell

The “AC_Test” and “DC_Mode” signal generation for each instruction is listed below. Note that the “AC_Test” is only active during the Run-Test/Idle controller state under the AC_EXTEST instruction. The “DC_Mode” signal is a boundary-scan cell BC_1 Mode signal described in the Standard.

Instruction AC_Test (at Run-Test/Idle state) DC_Mode

AC_EXTEST 1 1

EXTEST 0 1

SAMPLE/PRELOAD 0 0

INTEST 0 1

RUNBIST 0 1

CLAMP 0 1

Table 1: Mode signal generation for example AC boundary-scan cell BC_1



5. BSDL Syntax and examples

The AC_EXTEST instruction is defined as a public instruction. The wait duration and default

AC_EXTEST instruction are defined within the body of the BSDL extension. When the AC_EXTEST instruction is present it shall supersede operations of the EXTEST instruction by traversing the TAP controller to the Run-Test/Idle controller state after each Update-DR unless otherwise the EXTEST instruction is chosen for the component interconnect test by ATE test software. However, the test can be performed as conventional EXTEST instruction if the TAP controller goes to the Capture-DR controller state without passing through the Run-Test/Idle controller state after each Update-DR or Update-IR with the AC_EXTEST instruction selected.

The syntax of the AC_EXTEST BSDL extension is presented in Backus-Naur Form (BNF) as

described in Supplement to IEEE Std 1149.1 Addition to BSDL Reserved words for AC_EXTEST instruction are:

There are two additions to the BSDL Reserved words for AC_EXTEST instruction:

AC_EXTEST DC

NOTE – Multiple AC_EXTEST instruction support and AC_EXTEST instruction disable syntax are

given in this example. These features are not part of the Specification but are introduced as possible optional extensions.

5.1 AC_EXTEST BSDL extension syntax

The AC_EXTEST BSDL extension shall have the following structure to describe complete behavior of AC_EXTEST instruction.

<BSDL Description>::= entity <component name> is : : many lines deleted : {<BSDL extension><AC_EXTEST BSDL extension>} : : many lines deleted : end <component name> Within the <bsdl extension>, the AC_EXTEST instruction extensions shall have following

syntax:

<AC_EXTEST BSDL extension>::= <ac_extest_name description> <ac_extest_run description> <ac_extest_minimum_scan_clock description> <ac_extest boundary-scan length description> <ac_extest boundary-scan register description>



5.2 BSDL extension syntax

<BSDL extensions>::= <BSDL extension> {<BSDL extension>} <BSDL extension>::= <extension declaration> | <extension definition> <extension declaration>::= attribute <extension name>: BSDL_EXTENSION; <extension definition>::= attribute <extension name> of <component name>: entity is <extension parameter string>; <extension name>::= <entity defined name>|<VHDL package defined name> <entity defined name>::= <VHDL identifier> <VHDL package defined name>::= <VHDL identifier> <extension parameter string>::= <string>

Example 1: : : many lines deleted : attribute AC_EXTEST_INSTRUCTION : BSDL_EXTENSION; attribute AC_EXTEST_INSTRUCTION of ac_extest_asic: entity is "AC_EXTEST, My_AC_EXTEST, AX_EXTEST_SYSCLK"; attribute AC_EXTEST_EXECUTION : BSDL_EXTENSION; attribute AC_EXTEST_EXECUTION of ac_extest_asic: entity is "AC_EXTEST, Wait_Duration (TCK 240), "& "My_AC_EXTEST, Wait_Duration (TCK 480), "& "AX_EXTEST_SYSCLK, Wait_Duration (SYSCLOCK 12000)"; attribute AC_BOUNDARY_LENGTH : BSDL_EXTENSION; attribute AC_BOUNDARY_LENGTH of ac_extest_asic: entity is “20”; attribute AC_BOUNDARY_REGISTER : BSDL_EXTENSION; attribute AC_BOUNDARY_REGISTER of ac_extest_asic: entity is

-- num cell port/* function safe(ccell disal rslt) acsafe(ccell disal rslt) "487 (BDO_AC, mt3_cs_l, OUTPUT2, X: 0, 852, 0, DC)," & "488 (BDO_AC, mt3_ras_l, OUTPUT2, X: 0, 853, 0, DC)," & "489 (BDO_AC, mt3_cas_l, OUTPUT2, X: 0, 854, 0, DC)," & : : many lines deleted : "837 (BD_AC, sp_io(2), BIDIR, 0, 849, 0, Z: 0, 851, 0, DC)," & "838 (BD_AC, sp_io(1), BIDIR, 0, 849, 0, Z: 0, 851, 0, DC)," & "839 (BD_AC, sp_io(0), BIDIR, 0, 850, 0, Z: 0, 851, 0, DC)," & -- "854 (ENA_AC, *, INTERNAL, 0)," & -- safe value enable AC "855 (ENA_AC, *, INTERNAL, 0)" ; -- safe value enable AC

end ac_extest_asic;

5.3 AC_EXTEST instruction syntax

<ac_extest_name description>::= attribute AC_EXTEST_INSTRUCTION of <component name>:entity is <ac_extest_name spec>; <ac_extest_name spec>::=<instruction list string> <instruction list string>::="<instruction list>" <instruction list>::=<instruction name>{,<instruction name>} NOTE: <instruction name>::= BYPASS|CLAMP|EXTEST|HIGHZ|IDCODE|INTEST |PRELOAD|RUNBIST|SAMPLE|USERCODE|<VHDL identifier>



Example 1: attribute AC_EXTEST_INSTRUCTION : BSDL_EXTENSION; attribute AC_EXTEST_INSTRUCTION of AC_EXTEST_CHIP: entity is "AC_EXTEST" ; or "AC_EXTEST, AC_EXTEST_FAST"; or "AC_EXTEST_SYS_CLK, AC_EXTEST, " & "AC_EXTEST_2xTCK, AC_EXTEST_4xTCK," ;

Example 2: attribute AC_EXTEST_INSTRUCTION : BSDL_EXTENSION; attribute AC_EXTEST_EXECUTION : BSDL_EXTENSION; attribute AC_EXTEST_INSTRUCTION of AC_EXTEST_CHIP: entity is "AC_EXTEST, My_AC_EXTEST"; attribute AC_EXTEST_EXECUTION of AC_EXTEST_CHIP: entity is "AC_EXTEST: Waite_Duration (SYSCLOCK, 23000),"& "My_AC_EXTEST: Waite_Duration (1.0e-3)" ;

5.4 AC_EXTEST execution syntax <ac_extest_run description>::= attribute AC_EXTEST_EXECUTION of <component name>: entity is "<ac_extest_run spec list>"; <ac_extest_run spec list>::=<ac_extest_run spec>{,<ac_extest_run spec>} <ac_extest_run spec>::=<instruction name>:<wait spec> <wait spec>::=WAIT_DURATION(<duration spec>) <duration spec>::=<clock cycles list>|<time>[,<clock cycles list>] <clock cycles list>::=<clock cycles>{,<clock cycles>} <time>::=<real number> <clock cycles>::=<port ID><integer>

NOTE: A <real number> is any valid VHDL real number of the form

<integer>.<integer>E<integer> all written contiguously without spaces or format effectors. Note 1E3 is not real because it does not contain a decimal point. The number 20.0E6 is real, as is 20000000.0.

NOTE: <instruction name>::= BYPASS|CLAMP|EXTEST|HIGHZ|IDCODE|INTEST |PRELOAD|RUNBIST|SAMPLE|USERCODE|<VHDL identifier>

Example 1: attribute AC_EXTEST_EXECUTION : BSDL_EXTENSION; attribute AC_EXTEST_EXECUTION of AC_EXTEST_CHIP: entity is "AC_EXTEST, Waite_Duration (TCK 23000)," & "AC_EXTEST_SYSCLK, Waite_Duration (1.0e-3)" ;

Example 2:



attribute AC_EXTEST_EXECUTION : BSDL_EXTENSION; attribute AC_EXTEST_EXECUTION of AC_EXTEST_CHIP: entity is "AC_EXTEST: Waite_Duration (1.0e-3, TCK 23000)"; or entity is "AC_EXTEST: Waite_Duration (1.0e-3)"; or entity is "AC_EXTEST: Waite_Duration (TCK 23000)"; or entity is "AC_EXTEST: Waite_Duration (TCK 100000, SYSCLK 240000)";

5.5 AC_EXTEST minimum clock syntax

<ac_extest_minimum_scan_clock description>::= attribute AC_EXTEST_MIN_TCK of <component name>:entity is <ac_extest_min_tck spec>; <ac_extest_min_tck spec>::=<clock speed> <clock speed>::="<real number>"

Example 1: attribute AC_EXTEST_MIN_TCK : BSDL_EXTENSION; attribute AC_EXTEST_MIN_T of ac_extest_asic: entity is “2.50e6”;

5.6 AC_EXTEST boundary-scan length description syntax

<ac_extest boundary-scan length description>::=<ac_boundary length stmt> <ac_boundary length stmt>::= attribute AC_BOUNDARY_LENGTH of <component name> : entity is "<integer>";

Example 1: attribute AC_BOUNDARY_LENGTH : BSDL_EXTENSION; attribute AC_BOUNDARY_LENGTH of ac_extest_asic: entity is “20”;

5.7 AC_EXTEST boundary-scan register description syntax <ac_extest boundary-scan register description>::=<ac_boundary register stmt> <ac_boundary register stmt>::= attribute AC_BOUNDARY_REGISTER of <component name>: entity is<ac_cell table string>; <ac_cell table string>::="<ac_cell table>" <ac_cell table>::=<ac_cell entry>{,<ac_cell entry>} <ac_cell entry>::=<ac_cell number>(<ac_cell info>) <ac_cell number>::=<integer> <ac_cell info>::=<ac_cell spec>,<dc_disable spec>[:<ac_disable spec>] <ac_cell spec>::=<cell name>,<port ID or null>,<function> <cell name>::=<VHDL identifier>



<port ID or null>::=<port ID>|* <function>::=INPUT|OUTPUT2|OUTPUT3|CONTROL|CONTROLR|INTERNAL|CLOCK |BIDIR|OBSERVE_ONLY <dc_disable spec>::=<dc_safe bit>[,<dc_ccell>,<dc_disable value>, <dc_disable result>] <dc_safe bit>::=0|1|X <dc_ccell>::=<integer> <dc_disable value>::=0|1 <dc_disable result>::=Z|WEAK0|WEAK1|PULL0|PULL1|KEEPER <ac_disable spec>::=<ac_safe bit>,<ac_ccell>,<ac_disable value>, <ac_disable result> <ac_safe bit>::=0|1 <ac_ccell>::=<integer> <ac_disable value>::=0|1 <ac_disable result>::=DC

Example 1:

This example shows features defined by the specification as well as options that were not disclosed. .The undefined features described below are multiple AC_EXTEST instructions and AC_EXTEST execution support.

entity ac_extest_asic is : : many deleted lines : "487 (BDO_AC, mt3_cs_l, OUTPUT2, X)," & "488 (BDO_AC, mt3_ras_l, OUTPUT2, X)," & "489 (BDO_AC, mt3_cas_l, OUTPUT2, X)," & "490 (BDO_AC, mt3_we_l, OUTPUT2, X)," & : : many deleted lines : "829 (BD_AC, sp_io(10), BIDIR, 0, 840, 0, Z)," & "830 (BD_AC, sp_io(9), BIDIR, 0, 841, 0, Z)," & "831 (BD_AC, sp_io(8), BIDIR, 0, 842, 0, Z)," & "832 (BD_AC, sp_io(7), BIDIR, 0, 843, 0, Z)," & "833 (BD_AC, sp_io(6), BIDIR, 0, 844, 0, Z)," & "834 (BD_AC, sp_io(5), BIDIR, 0, 845, 0, Z)," & "835 (BD_AC, sp_io(4), BIDIR, 0, 846, 0, Z)," & "836 (BD_AC, sp_io(3), BIDIR, 0, 847, 0, Z)," & "837 (BD_AC, sp_io(2), BIDIR, 0, 848, 0, Z)," & "838 (BD_AC, sp_io(1), BIDIR, 0, 849, 0, Z)," & "839 (BD_AC, sp_io(0), BIDIR, 0, 850, 0, Z)," & "840 (BSR_ENA, *, CONTROL, 0)," & "841 (BSR_ENA, *, CONTROL, 0)," & "842 (BSR_ENA, *, CONTROL, 0)," & "843 (BSR_ENA, *, CONTROL, 0)," & "844 (BSR_ENA, *, CONTROL, 0)," & "845 (BSR_ENA, *, CONTROL, 0)," & "846 (BSR_ENA, *, CONTROL, 0)," & "847 (BSR_ENA, *, CONTROL, 0)," & "848 (BSR_ENA, *, CONTROL, 0)," & "849 (BSR_ENA, *, CONTROL, 0)," & "850 (BSR_ENA, *, CONTROL, 0)," & "851 (ENA_AC, *, INTERNAL, 0)," & -- safe value enable AC "852 (ENA_AC, *, INTERNAL, 0)," & -- safe value enable AC "853 (ENA_AC, *, INTERNAL, 0)," & -- safe value enable AC "854 (ENA_AC, *, INTERNAL, 0)," & -- safe value enable AC



"855 (ENA_AC, *, INTERNAL, 0)" ; -- safe value enable AC

attribute AC_EXTEST_INSTRUCTION : BSDL_EXTENSION; attribute AC_EXTEST_INSTRUCTION of ac_extest_asic: entity is "AC_EXTEST, My_AC_EXTEST, AX_EXTEST_SYSCLK"; attribute AC_EXTEST_EXECUTION : BSDL_EXTENSION; attribute AC_EXTEST_EXECUTION of ac_extest_asic: entity is "AC_EXTEST, Wait_Duration (TCK 240), "& "My_AC_EXTEST, Wait_Duration (TCK 480), "& "AX_EXTEST_SYSCLK, Wait_Duration (SYSCLOCK 12000)"; attribute AC_BOUNDARY_LENGTH : BSDL_EXTENSION; attribute AC_BOUNDARY_LENGTH of ac_extest_asic: entity is “20”; attribute AC_BOUNDARY_REGISTER : BSDL_EXTENSION; attribute AC_BOUNDARY_REGISTER of ac_extest_asic: entity is

-- num cell port/* function safe(ccell disal rslt) acsafe(ccell disal rslt) "487 (BDO_AC, mt3_cs_l, OUTPUT2, X: 0, 852, 0, DC)," & "488 (BDO_AC, mt3_ras_l, OUTPUT2, X: 0, 853, 0, DC)," & "489 (BDO_AC, mt3_cas_l, OUTPUT2, X: 0, 854, 0, DC)," & "490 (BDO_AC, mt3_we_l, OUTPUT2, X: 0, 855, 0, DC)," & -- "829 (BD_AC, sp_io(10), BIDIR, 0, 840, 0, Z: 0, 851, 0, DC)," & "830 (BD_AC, sp_io(9), BIDIR, 0, 841, 0, Z: 0, 851, 0, DC)," & "831 (BD_AC, sp_io(8), BIDIR, 0, 842, 0, Z: 0, 851, 0, DC)," & "832 (BD_AC, sp_io(7), BIDIR, 0, 843, 0, Z: 0, 851, 0, DC)," & "833 (BD_AC, sp_io(6), BIDIR, 0, 844, 0, Z: 0, 851, 0, DC)," & "834 (BD_AC, sp_io(5), BIDIR, 0, 845, 0, Z: 0, 851, 0, DC)," & "835 (BD_AC, sp_io(4), BIDIR, 0, 846, 0, Z: 0, 851, 0, DC)," & "836 (BD_AC, sp_io(3), BIDIR, 0, 847, 0, Z: 0, 851, 0, DC)," & "837 (BD_AC, sp_io(2), BIDIR, 0, 849, 0, Z: 0, 851, 0, DC)," & "838 (BD_AC, sp_io(1), BIDIR, 0, 849, 0, Z: 0, 851, 0, DC)," & "839 (BD_AC, sp_io(0), BIDIR, 0, 850, 0, Z: 0, 851, 0, DC)," & -- "851 (ENA_AC, *, INTERNAL, 0)," & -- safe value enable AC "852 (ENA_AC, *, INTERNAL, 0)," & -- safe value enable AC "853 (ENA_AC, *, INTERNAL, 0)," & -- safe value enable AC "854 (ENA_AC, *, INTERNAL, 0)," & -- safe value enable AC "855 (ENA_AC, *, INTERNAL, 0)" ; -- safe value enable AC end ac_extest_asic;



6. Fault Coverage Consideration Actual boundary-scan test coverage for AC_EXTEST will vary widely depending on how the test input

buffer is designed. It is important to note that the test coverage for the given AC coupled net is not dependent on the type or speed of AC patterns applied as long as the given AC pattern is adequate for proper signal transmission. In many cases, the test speed for the AC coupled net is not as high as the actual functional speed of the given net. For up to 5 GHz data rate signal line with 0.01 µf AC coupled line, an AC pattern speed of less than 5 MHz will be adequate for proper AC_EXTEST execution. In this Chapter, an example block diagram of a typical differential input test buffer is given along with a logical view of fault coverage for the ideal implementation. 6.1 Test Coverage with current implementation

The AC Boundary-scan Specification specifies only the logical rules of circuit design, but it does not provide information on any specific AC boundary-scan input test buffer design implementations.

6.2 Input Test buffer design consideration

By designing an AC boundary-scan "Input Test Buffer" with the following functions, it can help detect many faults that are undetectable with IEEE 1149.1 based differential line testing. In the case of parallel optics module design, the “Input Test Buffer” has been designed with minimum gate overhead. The following figure shows an example block diagram of a preferred implementation of the test input buffer for parallel optics based transmit and receive devices.

AC Status Detection

TerminationNetwork

Highspeed signal path

Null Detection

Short Detection

Test Buffer

Figure 13: Example AC_EXTEST Input Test Buffer

6.2.1. AC status detection This block detects a peak or edge of an incoming signal or state of two consecutive incoming

signals to determine status of AC signal in the differential line pairs. During AC_EXTEST, two consecutive bits have exclusive OR relationship.

6.2.2. Null detection



This block detects float, null, and/or common mode voltage signals in the differential line or line pairs.

6.2.3. Short detection

This block detects shorts between the differential line pairs or shorts between differential line and power or ground rails.

From the above capabilities, the truth table below is built to show the types of faults detected. The

truth table assumes all signals are active high and differential inputs are driven with proper differential signal values during normal operation. Signal A is designated as the non-inverting side of a differential input and Signal B represents the inverting side of a differential input. The truth table shows the ideal expected behavior rather than demonstrated results. Careful implementation of the test buffer can easily achieve the coverage detailed in the Table.

Fault detection criteria

Null or Float Status

Short Status

AC Status

Resulting Error Status

0 0 0

No float, no short, no AC status. Coupling component open or noise below common mode voltage, technology dependent behavior but result in error condition. No Error Condition for DC mode

0 0 1 No float, no short, AC status. No Error Condition, normal operation in AC mode

0 1 0 No float, short, no AC status. Both A and B short, or shorted with power or ground rail

0 1 1 No null, short, AC status. A and B short.

1 0 0 Null or float with no short, no AC status. A and B open, no short between A and B.

1 0 1 Null or float with no short, AC status. A or B open.

1 1 0 Null or float, short, no AC status. A and B open at driver, or short at receiver, technology dependent behavior but result in error.

1 1 1 Null or float, short, AC status. Condition is not feasible by structural fault.

Table 2: Fault coverage Truth Table

The “001” status above shows no error condition for the AC_EXTEST instruction and the “000” condition shows no error condition for the EXTEST instruction. All other status indicates error condition(s) with one or more of the fault status listed.

With these capabilities one can greatly improve test coverage beyond the current IEEE 1149.1 standard. Many Parallel Optics modules use these functions to turn off LASER and high speed sections



of logic to save power and enhance safety.

6.3 Input Test Buffer design and boundary-scan interface examples

Figure 14 shows the physical connection of differential input and output buffers and building blocks used in the MSA input test buffer. Note that an analog input signal interface to the boundary-scan domain is assumed. Six different building blocks are used in the buffer and listed below. Each component in the buffer plays either unique or multiple roles in detecting and identifying various faulty input signal conditions.

• Null Receiver • Technology Mapper • Signal Recover • Short and Null Detector • AC detector • Integrator

_

+

_

+Set

ResetQ

Q

AC CouplingCapacitor

Null ReceiverTechnology

MapperShort / Null

Detector AC Detector Integrator

MSAinput ACScan Cell

AC Pattern Clock

DC ShortDetect

AC Short /Null Detect

ScanInterface

Reset

Set

Q

Q

D

Clk

Lo

gic

al L

ink

TransmissionLayer

Dif

fere

nti

alD

rive

r

LogicalLinkInput Test Buffer / Detectors / Integrator : Physical LinkPhysical

Link

SignalRecover

Detectors

DC Test

AC Test

Input Test BufferDC_Short

DC_Test_Data

No_AC_Detect

AC_Test_Data

AC_Short

DC_Data

AC_Data

Figure 14: Example input test buffer and boundary-scan interface logic 6.3.1 Design and interface examples

Three complete examples showing input test buffer design and boundary-scan cell interface are give in this section. Each figure has unique input test buffer with different boundary-scan cell interface circuit.

_

+

_

+

50

50

1 K

1 K

2 K

2 K

IN_P

IN_N

Reset

Set

Vicm

A

B

VaOptional

Vcom

R1

R2

R3

R4

Vicm - A >= Window

Vicm - B >= Window

Input Test Buffer

DC Short DetectDC_Short

DC_Test_Data

Set

Rst

QQ

D

Clk

Q

Q No_

AC

_Det

ect

AC Short Null / Detect

AC Detector

AC_Test_Data

AC_Short

DC_Data

AC_DataD

Clk

Q

Q

D

Clk

Q

Q

01 0

1

to nextcell

AC_SyncAC_Test_Ran

from last cell

ClockDRShiftDR

AC Pattern Clock

Detectors

Integrator

Scan CellBC_4

SignalRecover

Figure 15: Example differential input test buffer with single boundary-scan cell interface



Each example input test buffer uses comparator with 1/3 window of input differential voltage Va to determine active signal level from null signal level.

Figure 15 has differential input test buffer with single scan cell interface. The detector section has has

level more detection circuit than the rest of examples in order to support single boundary-scan cell without sacrificing the AC boundary-scan test coverage.

_

+

_

+

50

50

1 K

1 K

2 K

2 K

IN_P

IN_N

Reset

Set

Vicm

A

B

VaOptional

Vcom

R1

R2

R3

R4

Vicm - A >= Window

Vicm - B >= Window

Input Test Buffer

DC_Data_P

AC_Data_PD

Clk

Q

Q

D

Clk

Q

Q

01 0

1

to nextcell

AC_SyncAC_Test_Ran

ClockDRShiftDR

AC Pattern Clock

Integrator

Scan CellBC_4

DC_Data_N

AC_Data_ND

Clk

Q

Q

D

Clk

Q

Q

01 0

1

from last cell

Integrator

Scan CellBC_4

Set

Rst

QQ

D

Clk

Q

Q No_AC_Detect

AC Detector

Detectors

SignalRecover

Figure 16: Example differential input test buffer with two boundary-scan cell interface

Figure 16 has two boundary-scan cell interfaces from differential input test buffer. The input test buffer shown in this figure may not provide good diagnostic information even with two boundary-scan cell interface.

DC_Data_P

AC_Data_PD

Clk

Q

Q

D

Clk

Q

Q

01 0

1

to nextcell

AC_SyncAC_Test_Ran

ClockDRShiftDR

AC Pattern Clock

Integrator

Scan CellBC_4

DC_Data_N

AC_Data_NDClk

QQ

DClk

QQ

01 0

1

from last cell

IntegratorScan Cell

BC_4

Set

Rst

Q

Q

D

Clk

Q

Q

No_

AC

_Det

ect

AC Detector

Detectors

SignalRecover

Set

Rst

Q

Q

SignalRecover

_

+

_

+

50

50

1 K

1 K

1 K

1 K

IN_P

IN_N

Vref

Reset

Set

A

BVa

_

+Reset

_

+Set

R1

R2

R3

R4

Comp1

Comp2

Comp3

Comp4

IN_N - C >= Window

C

D

B - D >= Window

C - A >= Window

IN_P - B >= Window

R5

R6

2 K

2 K

OptionalVcom

Input Test Buffer

Figure 17: Example hybrid input test buffer with two boundary-scan cell interface

Figure 17 has much better diagnostic capability without sacrificing the AC boundary-scan test coverage. The internal common mode voltage reference Vref is from low impedance voltage source.



7. Terms

AC: Alternating Current AC Boundary-Scan: general term to describe AC coupled net test capable boundary-scan struc-

ture. It consists of pattern generator and pattern capture with optional synchronizing pulse, and pattern mapping mechanism if necessary to map captured AC signals back to expected DC value.

AC Coupling: steady state value at the receiving end of the net is no longer the same value as in driving end, then the net is so call AC coupled. The net has serial coupling with capacitive component. DC de-coupled net is AC coupled net.

AC pattern: consist of serial bit stream with certain clock speed. The pattern has fixed length and repeats itself continually. As a simplest form, it can be a LFSR with single feedback, which has polynomial form of f(x) = 1+Xn. Other known coding sequences also can be used.

BC_1: boundary-scan cell type that can be used in both input and out signal lines. It has Capture and Drive capability for both EXTEST and INTEST.

BSDL: Boundary-Scan Description Language DC pattern: test pattern with the constant driving value during the entire duration of given test

cycle. The IEEE 1149.1 standard performs DC test based component interconnect test with DC patterns.

IEEE 1149.1: A standard for a test circuitry bus, developed by the Institute of Electrical and Electronic Engineers (IEEE). It defines a serial bus with control lines and control circuitry, which allow ASICs and other VLSI devices to be tested in their system boards (if the boards are also designed to the standard).

JTAG: Joint Test Action Group, the grandfather of the IEEE 1149.1 standard. MSA: Multi Source Agreement (specification), Cisco’s effort to standardize device package and

interface characteristics of the VCSEL devices for alternate source. TAP: Test Access Port defined in IEEE 1149.1 standard for the boundary-scan interface. VCSEL: Vertical Cavity Surface Emitting LASER

Documents

AC Boundary-scan Specification for IEEEgrouper.ieee.org/groups/1149/6/doc/IEEE_ACJTAG_B5a.pdfAC Boundary-scan Specification for IEEE Document EDCS-134568 Rev B5 Page 3 of 22 Cisco