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A/D Flash MCU with EEPROM HT66F488/HT66F489 Revision: V1.21 Date: �ove�e� 2�1�ove�e� 2�1

A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

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Page 1: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

A/D Flash MCU with EEPROM

HT66F488/HT66F489

Revision: V1.21 Date: �ove��e� ��� 2�1��ove��e� ��� 2�1�

Page 2: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 2 �ove��e� ��� 2�1� Rev. 1.21 3 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Table of Contents

Features ............................................................................................................ 7CPU Featu�es ......................................................................................................................... �Pe�iphe�al Featu�es ................................................................................................................. �

General Description ........................................................................................ 8Selection Table ................................................................................................. 8Block Diagram .................................................................................................. 9Pin Assignment ................................................................................................ 9Pin Descriptions ............................................................................................ 10Absolute Maximum Ratings .......................................................................... 13D.C. Characteristics ....................................................................................... 13A.C. Characteristics ....................................................................................... 15LVR & LVD Characteristics ........................................................................... 16A/D Converter Electrical Characteristics ..................................................... 17Power on Reset Electrical Characteristics .................................................. 17System Architecture ...................................................................................... 18

Clocking and Pipelining ......................................................................................................... 18P�og�a� Counte� ................................................................................................................... 1�Stack ..................................................................................................................................... 2�A�ith�etic and Logic Unit – ALU ........................................................................................... 2�

Flash Program Memory ................................................................................. 21St�uctu�e ................................................................................................................................ 21Special Vecto�s ..................................................................................................................... 21Look-up Ta�le ........................................................................................................................ 22Ta�le P�og�a� Exa�ple ........................................................................................................ 22In Ci�cuit P�og�a��ing ......................................................................................................... 23On-Chip De�ug Suppo�t – OCDS ......................................................................................... 24

RAM Data Memory ......................................................................................... 25St�uctu�e ................................................................................................................................ 25Gene�al Pu�pose Data Me�o�y ........................................................................................... 25Special Pu�pose Data Me�o�y ............................................................................................ 26

Special Function Register Description ........................................................ 27Indi�ect Add�essing Registe� – IAR�� IAR1� IAR2 ................................................................. 2�Me�o�y Pointe�s – MP�� MP1L� MP1H� MP2L� MP2H ......................................................... 2�Accu�ulato� – ACC ............................................................................................................... 2�P�og�a� Counte� Low Registe� – PCL .................................................................................. 2�Look-up Ta�le Registe�s – TBLP� TBHP� TBLH ..................................................................... 2�Status Registe� – STATUS ................................................................................................... 2�

Page 3: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 2 �ove��e� ��� 2�1� Rev. 1.21 3 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

EEPROM Data Memory .................................................................................. 31EEPROM Data Me�o�y St�uctu�e ........................................................................................ 31EEPROM Registe�s .............................................................................................................. 31Reading Data f�o� the EEPROM ........................................................................................ 33W�iting Data to the EEPROM ................................................................................................ 33W�ite P�otection ..................................................................................................................... 33EEPROM Inte��upt ................................................................................................................ 33P�og�a��ing Conside�ations ................................................................................................ 34

Oscillator ........................................................................................................ 35Oscillato� Ove�view ............................................................................................................... 35System Clock Configurations ................................................................................................ 35Exte�nal C�ystal/Ce�a�ic Oscillato� – HXT ........................................................................... 36Inte�nal RC Oscillato� – HIRC ............................................................................................... 3�Exte�nal 32.�68kHz C�ystal Oscillato� – LXT ........................................................................ 3�Inte�nal 32kHz Oscillato� – LIRC ........................................................................................... 38Supple�enta�y Oscillato� ...................................................................................................... 38

Operating Modes and System Clocks ......................................................... 39Syste� Clocks ...................................................................................................................... 3�Syste� Ope�ation Modes ...................................................................................................... 4�Cont�ol Registe� .................................................................................................................... 41Fast Wake-up ........................................................................................................................ 42Ope�ating Mode Switching ................................................................................................... 43Stand�y Cu��ent Conside�ations ........................................................................................... 45Wake-up ................................................................................................................................ 45P�og�a��ing Conside�ations ................................................................................................ 46

Watchdog Timer ............................................................................................. 46Watchdog Ti�e� Clock Sou�ce .............................................................................................. 46Watchdog Ti�e� Cont�ol Registe� ......................................................................................... 46Watchdog Ti�e� Ope�ation ................................................................................................... 48

Reset and Initialisation .................................................................................. 49Reset Functions .................................................................................................................... 4�Reset Initial Conditions ......................................................................................................... 51

Input/Output Ports ......................................................................................... 54Pull-high Resisto�s ................................................................................................................ 55Po�t A Wake-up ..................................................................................................................... 55I/O Po�t Cont�ol Registe�s ..................................................................................................... 55Pin-sha�ed Functions ............................................................................................................ 55I/O Pin St�uctu�es .................................................................................................................. 55I/O Po�t sou�ce cu��ent selection ........................................................................................... 5�P�og�a��ing Conside�ations ................................................................................................ 5�

Page 4: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 4 �ove��e� ��� 2�1� Rev. 1.21 5 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Timer Modules – TM ...................................................................................... 59Int�oduction ........................................................................................................................... 5�TM Ope�ation ........................................................................................................................ 6�TM Clock Sou�ce ................................................................................................................... 6�TM Inte��upts ......................................................................................................................... 6�TM Exte�nal Pins ................................................................................................................... 6�TM Input/Output Pin Cont�ol Registe� ................................................................................... 61P�og�a��ing Conside�ations ................................................................................................ 63

Compact Type TM – CTM .............................................................................. 64Co�pact TM Ope�ation ......................................................................................................... 64Co�pact Type TM Registe� Desc�iption................................................................................ 65Co�pact Type TM Ope�ating Modes .................................................................................... 6�

Standard Type TM – STM .............................................................................. 75Standa�d TM Ope�ation ......................................................................................................... �5Standa�d Type TM Registe� Desc�iption ............................................................................... �6Standa�d Type TM Ope�ating Modes .................................................................................... 8�

Periodic Type TM – PTM0, PTM1 .................................................................. 90Pe�iodic TM Ope�ation .......................................................................................................... ��PTM �egiste� desc�iption ....................................................................................................... �1Pe�iodic Type TM Ope�ating Modes ...................................................................................... �5

Analog to Digital Converter ........................................................................ 104A/D Ove�view ...................................................................................................................... 1�4A/D Conve�te� Registe� Desc�iption .................................................................................... 1�4A/D Conve�te� Data Registe�s – ADRL� ADRH ................................................................... 1�5A/D Conve�te� Cont�ol Registe�s – ADCR�� ADCR1� ACERL ............................................. 1�5A/D Ope�ation ..................................................................................................................... 1�8A/D Input Pins ......................................................................................................................11�Su��a�y of A/D Conve�sion Steps ......................................................................................11�P�og�a��ing Conside�ations ...............................................................................................112A/D T�ansfe� Function ..........................................................................................................112A/D P�og�a��ing Exa�ples ................................................................................................113

Serial Interface Module – SIM ......................................................................115SPI Inte�face ........................................................................................................................115SPI Registe� .........................................................................................................................116SPI Co��unication .............................................................................................................11�I2C Inte�face ........................................................................................................................ 121I2C Registe� ......................................................................................................................... 122I2C Bus Co��unication ...................................................................................................... 126I2C Bus Sta�t Signal ............................................................................................................. 12�Slave Add�ess ..................................................................................................................... 12�I2C Bus Read/W�ite Signal .................................................................................................. 12�I2C Bus Slave Add�ess Acknowledge Signal ....................................................................... 12�I2C Bus Data and Acknowledge Signal ............................................................................... 128I2C Ti�e-out Cont�ol ............................................................................................................ 12�

Page 5: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 4 �ove��e� ��� 2�1� Rev. 1.21 5 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

UART Module Serial Interface .................................................................... 131UART Exte�nal Inte�face ..................................................................................................... 131UART Data T�ansfe� Sche�e.............................................................................................. 132UART Status and Cont�ol Registe�s.................................................................................... 132Baud Rate Gene�ato� .......................................................................................................... 138Calculating the �egiste� and e��o� values ............................................................................ 138UART Setup and Cont�ol..................................................................................................... 13�Managing �eceive� e��o�s .................................................................................................... 143UART Module Inte��upt St�uctu�e ........................................................................................ 144Add�ess detect �ode .......................................................................................................... 145UART Module Powe� Down and Wake-up .......................................................................... 146

Interrupts ...................................................................................................... 146Inte��upt Registe�s ............................................................................................................... 146Inte��upt Ope�ation .............................................................................................................. 154Exte�nal Inte��upt ................................................................................................................. 155Multi-function Inte��upt ........................................................................................................ 156A/D Conve�te� Inte��upt ....................................................................................................... 156Ti�e Base Inte��upts ........................................................................................................... 156Se�ial Inte�face Module Inte��upts ....................................................................................... 15�EEPROM Inte��upt .............................................................................................................. 158TM Inte��upts ....................................................................................................................... 158LVD Inte��upt ...................................................................................................................... 158UART Inte��upt .................................................................................................................... 158Inte��upt Wake-up Function ................................................................................................. 15�P�og�a��ing Conside�ations .............................................................................................. 15�

Software LCD Driver .................................................................................... 160LCD ope�ation ..................................................................................................................... 16�LCD Cont�ol Registe�s ........................................................................................................ 16�LCD wavefo�� .................................................................................................................... 165

Low Voltage Detector – LVD ....................................................................... 167LVD Registe� ....................................................................................................................... 16�LVD Ope�ation ..................................................................................................................... 168

Configuration Option ................................................................................... 169Application Circuit ....................................................................................... 169Instruction Set .............................................................................................. 170

Int�oduction ......................................................................................................................... 1��Inst�uction Ti�ing ................................................................................................................ 1��Moving and T�ansfe��ing Data ............................................................................................. 1��A�ith�etic Ope�ations .......................................................................................................... 1��Logical and Rotate Ope�ation ............................................................................................. 1�1B�anches and Cont�ol T�ansfe� ........................................................................................... 1�1Bit Ope�ations ..................................................................................................................... 1�1Ta�le Read Ope�ations ....................................................................................................... 1�1Othe� Ope�ations ................................................................................................................. 1�1

Page 6: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 6 �ove��e� ��� 2�1� Rev. 1.21 � �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Instruction Set Summary ............................................................................ 172Ta�le Conventions ............................................................................................................... 1�2Extended Inst�uction Set ..................................................................................................... 1�4

Instruction Definition ................................................................................... 176Extended Instruction Definition ........................................................................................... 185

Package Information ................................................................................... 19228-pin SOP (3���il) Outline Di�ensions ........................................................................... 1�328-pin SSOP (15��il) Outline Di�ensions ......................................................................... 1�4

Page 7: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 6 �ove��e� ��� 2�1� Rev. 1.21 � �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Features

CPU Features• OperatingVoltage

♦ fSYS=8MHz:2.2V~5.5V♦ fSYS=10MHz:2.7V~5.5V♦ fSYS=12MHz:3.3V~5.5V♦ fSYS=16MHz:4.5V~5.5V

• Upto0.25μsinstructioncyclewith16MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• FourOscillators:

• ExternalHighFrequencyCrystal–HXT

• External32.768kHzCrystal--LXT

• InternalHighFrequencyRC--HIRC

• Internal32kHz--LIRC

• Fullyintergratedinternal8MHzoscillatorrequiresnoexternalcomponents

• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP

• Allinstructionsexecutedinonetothreeinstructioncycles

• Tablereadinstructions

• 115powerfulinstructions

• 8-levelsubroutinenesting

• Bitmanipulationinstruction

Peripheral Features• FlashProgramMemory:8K×16(HT66F489)/4K×16(HT66F488)

• RAMDataMemory:384×8

• TrueEEPROMMemory:64×8

• WatchdogTimerfunction

• 30bidirectionalI/Olines

• LEDdriver

• 1/3BiasSoftwareLCD

• SerialInterfaceModule–SIMforSPIorI2C

• UARTFunction

• Sixpin-sharedexternalinterrupts

• MultipleTimerModulefor timemeasure, inputcapture,comparematchoutput,PWMoutputfunctionorsinglepulseoutputfunction

• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals

• 8-channel12-bitresolutionA/Dconverter

• Lowvoltageresetfunction

• Lowvoltagedetectorfunction

• Package:28-pinSOP/SSOP

Page 8: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 8 �ove��e� ��� 2�1� Rev. 1.21 � �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

General Description Thedevicesare8-bithighperformanceRISCarchitecturemicrocontroller,designedespeciallyforapplicationsthatinterfacedirectlytoanalogsignals,suchasthosefromsensor.OfferinguserstheconvenienceofFlashMemorymulti-programmingfeatures,thisdevicealsoincludesawiderangeoffunctionsandfeatures.OthermemoryincludesanareaofRAMDataMemoryaswellasanareaoftrueEEPROMmemoryforstorageofnon-volatiledatasuchasserialnumbers,calibrationdataetc.

Analogfeaturesincludeamulti-channel12-bitA/Dconverter.MultipleandextremelyflexibleTimerModulesprovidetiming,pulsegenerationandPWMgenerationfunctions.CommunicationwiththeoutsideworldcateredforbyincludingfullyintegratedSPI,I2CandUARTinterfacefunctions,threepopularinterfaceswhichprovidedesignerswithameansofeasycommunicationwithexternalperipheralhardware.ProtectivefeaturessuchasaninternalWatchdogTimer,LowVoltageResetandLowVoltageDetectorcoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.

AfullchoiceofHXT,LXT,HIRCandLIRCoscillatorfunctionsareprovidedincludingafullyintegratedsystemoscillatorwhichrequiresnoexternalcomponents for its implementation.Theability tooperateandswitchdynamicallybetweena rangeofoperatingmodesusingdifferentclocksourcesgivesusers theability tooptimisemicrocontrolleroperationandminimizepowerconsumption.

The inclusionof flexible I/Oprogramming features,Time-Base functions alongwithmanyotherfeaturesensure that thedevicewillfindexcellentuseinapplicationssuchassensorsignalprocessing,chargers,motordriving,industrialcontrol,consumerproduct,subsystemcontroller,etc.

Selection TableMostfeaturesarecommontoalldevices,themainfeaturedistinguishingthemareMemorycapacityandwhetherEEPROMornot.Thefollowingtablesummarisesthemainfeaturesofeachdevice.

Part No. Program Memory

Data Memory

Data EEPROM I/O R-type LCD

(1/3 Bias)High Current LED Output

HT66F488 4K×16384×8 64×8 26 6(SCOM/SSEG)

+2�SSEG 26HT66F48� 8K×16

Part No. Timer Module RTC A/D Interface Stack Package

HT66F488 1�-�it CTM×1 16-�it STM×1 1�-�it PTM×2

√ 12-�it×8 SPI/I2C� UART 8 28SOP/SSOPHT66F48�

Page 9: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 8 �ove��e� ��� 2�1� Rev. 1.21 � �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Block Diagram

8-bitRISCMCUCore

Flash Program Memory

EEPROMData

Memory

Flash/EEPROM Programming Circuitry

(ICP)/OCDS

TimeBases

I/O

Low Voltage Reset

Watchdog Timer

Low Voltage Detect

InterruptController

ResetCircuit

HXT/ LXTOscillators

12-bit A/DConverter

RAM Data Memory

Internal RCOscillators

UART

SIM

SoftwareLCD

CTM STM PTMs

Pin Assignment

PC4/AN4/SSEG22 PC5/AN5/INT3/SSEG21PC3/AN3/SSEG23PC0/AN2/SSEG26

PB7/STP/RX/AN1/SSEG27PB6/STCK/TX/AN0/SSEG28

PB5/SSEG29VSS/AVSS

PD0/ICPDA/SCOM0/SSEG0PA6/PTCK1/SCS/SSEG12PA5/PTP1/SCK/SCL/SSEG11PA4/SDI/SDA/SSEG10PA3/SDO/SSEG9PA2/OCDSCK/SSEG8PA1/SSEG7

PC6/AN6/VREF/INT2/SSEG20PB1/PTCK0/INT1/AN7/SSEG17PB2/CTP/INT0/SSEG16PB3/OSC2/XT2/SSEG15PB4/OSC1/XT1/ICPCK/SSEG14VDD/AVDDPA7/CTCK/SSEG13

PD1/SCOM1/SSEG1PD2/SCOM2/SSEG2PD3/SCOM3/SSEG3PD4/SCOM4/SSEG4PD5/SCOM5/SSEG5PA0/OCDSDA/SSEG6

HT66F488/489HT66V488/489

28 SOP-A/SSOP-A

2827262524232221201918171615

1234567891011121314

Note:1.Ifthepin-sharedpinfunctionshavemultipleoutputssimultaneously,thefunctionusedisdeterminedbythecorrespondingsoftwarecontrolbitorconfigurationoption.

2.AVDD&VDDmeans theVDDandAVDDare thedoublebonding.VSS&AVSSmeans theVSSandAVSSarethedoublebonding.

3.HT66V488/489istheEVchip,andtheOCDSDA,OCDSCKpinsareforEVchiponly.

Page 10: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 1� �ove��e� ��� 2�1� Rev. 1.21 11 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Pin DescriptionsPin Name Function OPT I/T O/T Description

PA�/OCDSDA/SSEG6

PA� PAWUPAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up and wake-up

OCDSDA — ST CMOS OCDS Data/Add�ess pin� fo� EV chip onlySSEG6 SLCDC2 — CMOS Softwa�e LCD SEG output

PA1/SSEG�PA1 PAWU

PAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up and wake-up

SSEG� SLCDC2 — CMOS Softwa�e LCD SEG output

PA2/OCDSCK/SSEG8

PA2 PAWUPAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up and wake-up

OCDSCK — ST — OCDS Clock pin� fo� EV chip only.SSEG8 SLCDC2 — CMOS Softwa�e LCD SEG output

PA3/SDO/SSEG�PA3 PAWU

PAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up and wake-up

SDO — — CMOS SPI Data outputSSEG� SLCDC2 — CMOS Softwa�e LCD SEG output

PA4/SDI/SDA/SSEG1�

PA4 PAWUPAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up and wake-up

SDI — ST — SPI Data inputSDA — ST �MOS I2C Data

SSEG1� SLCDC2 — CMOS Softwa�e LCD SEG output

PA5/PTP1/SCK/SCL/SSEG11

PA5 PAWUPAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up and wake-up

PTP1 TMPC� ST CMOS PTM1 input/outputSCK — ST CMOS SPI Se�ial ClockSCL — ST �MOS I2C Clock

SSEG11 SLCDC2 — CMOS Softwa�e LCD SEG output

PA6/PTCK1/SCS/SSEG12

PA6 PAWUPAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up and wake-up

PTCK1 — ST — PTM1 inputSCS — ST CMOS SPI slave� selection

SSEG12 SLCDC2 — CMOS Softwa�e LCD SEG output

PA�/CTCK/SSEG13

PA� PAWUPAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up and wake-up

CTCK — ST — CTM inputSSEG13 SLCDC2 — CMOS Softwa�e LCD SEG output

PB�/PTP�/I�T4/SSEG18

PB� PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.PTP� TMPC� ST CMOS PTM� outputI�T4 — ST — Exte�nal inte��upt input

SSEG18 SLCDC3 — CMOS Softwa�e LCD SEG output

PB1/PTCK�/I�T1/A��/SSEG1�

PB1 PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.PTCK� — ST — PTM� inputI�T1 — ST — Exte�nal inte��upt inputA�� ACERL A� — ADC input

SSEG1� SLCDC3 — CMOS Softwa�e LCD SEG output

PB2/CTP/I�T�/SSEG16

PB2 PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.CTP TMPC� ST CMOS CTM outputI�T� — ST — Exte�nal inte��upt input

SSEG16 SLCDC3 — CMOS Softwa�e LCD SEG output

Page 11: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 1� �ove��e� ��� 2�1� Rev. 1.21 11 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Pin Name Function OPT I/T O/T Description

PB3/OSC2/XT2/SSEG15

PB3 PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.OSC2 CO — HXT HXT pinXT2 CO — LXT LXT pin

SSEG15 SLCDC3 — CMOS Softwa�e LCD SEG output

PB4/OSC1/XT1/ICPCK/SSEG14

PB4 PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.OSC1 CO HXT — HXT pinXT1 CO LXT — LXT pin

ICPCK — ST — ICP Clock pinSSEG14 SLCDC3 — CMOS Softwa�e LCD SEG output

PB5/SSEG2�PB5 PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.

SSEG2� SLCDC4 — CMOS Softwa�e LCD SEG output

PB6/STCK/TX/A��/SSEG28

PB6 PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.STCK — ST — STM input

TX — — CMOS UART data t�ans�ission outputA�� ACERL A� — ADC input

SSEG28 SLCDC4 — CMOS Softwa�e LCD SEG output

PB�/STP/RX/A�1/SSEG2�

PB� PBPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.STP TMPC� ST CMOS STM input/outputRX — ST — UART data �eceived input

A�1 ACERL A� — ADC inputSSEG2� SLCDC4 — CMOS Softwa�e LCD SEG output

PC�/A�2/SSEG26

PC� PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.A�2 ACERL A� — ADC input

SSEG26 SLCDC4 — CMOS Softwa�e LCD SEG output

PC1/SSEG25PC1 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.

SSEG25 SLCDC4 — CMOS Softwa�e LCD SEG output

PC2/SSEG24PC2 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.

SSEG24 SLCDC4 — CMOS Softwa�e LCD SEG output

PC3/A�3/SSEG23

PC3 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.A�3 ACERL A� — ADC input

SSEG23 SLCDC4 — CMOS Softwa�e LCD SEG output

PC4/A�4/SSEG22

PC4 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.A�4 ACERL A� — ADC input

SSEG22 SLCDC4 — CMOS Softwa�e LCD SEG output

PC5/A�5/I�T3/SSEG21

PC5 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.A�5 ACERL A� — ADC inputI�T3 — ST — Exte�nal inte��upt input

SSEG21 SLCDC3 — CMOS Softwa�e LCD SEG output

PC6/A�6/VREF/I�T2/SSEG2�

PC6 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.A�6 ACERL A� — ADC input

VREF ADCR1 A� — ADC Refe�ence voltage inputI�T2 — ST — Exte�nal inte��upt input

SSEG2� SLCDC3 — CMOS Softwa�e LCD SEG output

PC�/I�T5/SSEG1�

PC� PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.I�T5 — ST — Exte�nal inte��upt input

SSEG1� SLCDC3 — CMOS Softwa�e LCD SEG output

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Rev. 1.21 12 �ove��e� ��� 2�1� Rev. 1.21 13 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Pin Name Function OPT I/T O/T Description

PD�/ICPDA/SCOM�/SSEG�

PD� PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.ICPDA — ST CMOS ICP Data/Add�ess pin

SCOM� SLCDC�SLCDC1 — CMOS Softwa�e LCD COM output

SSEG� SLCDC�SLCDC1 — CMOS Softwa�e LCD SEG output

PD1/SCOM1/SSEG1

PD1 PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.

SCOM1 SLCDC�SLCDC1 — CMOS Softwa�e LCD COM output

SSEG1 SLCDC�SLCDC1 — CMOS Softwa�e LCD SEG output

PD2/SCOM2/SSEG2

PD2 PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.

SCOM2 SLCDC�SLCDC1 — CMOS Softwa�e LCD COM output

SSEG2 SLCDC�SLCDC1 — CMOS Softwa�e LCD SEG output

PD3/SCOM3/SSEG3

PD3 PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.

SCOM3 SLCDC�SLCDC1 — CMOS Softwa�e LCD COM output

SSEG3 SLCDC�SLCDC1 — CMOS Softwa�e LCD SEG output

PD4/SCOM4/SSEG4

PD4 PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.SCOM4 SLCDC1 — CMOS Softwa�e LCD COM outputSSEG4 SLCDC1 — CMOS Softwa�e LCD SEG output

PD5/SCOM5/SSEG5

PD5 PDPU ST CMOS Gene�al pu�pose I/O. Registe� ena�le pull-up.SCOM5 SLCDC1 — CMOS Softwa�e LCD COM outputSSEG5 SLCDC1 — CMOS Softwa�e LCD SEG output

VDD/AVDDVDD — PWR — Positive Powe� Supply

AVDD — PWR — Analog Positive Powe� Supply

VSS/AVSSVSS — PWR — �egative Powe� Supply. G�ound

AVSS — PWR — Analog �egative Powe� Supply

Note:I/T:Inputtype; O/T:OutputtypeOP:Optionalbyconfigurationoption(CO)orregisteroptionPWR:Power; CO:Configurationoption; ST:SchmittTriggerinputCMOS:CMOSoutput; AN:AnaloginputpinHXT:HighfrequencycrystaloscillatorLXT:Lowfrequencycrystaloscillator*:VDDis thedevicepowersupplywhileAVDDis theADCpowersupply.TheAVDDpin isbondedtogetherinternallywithVDD.

**:VSSisthedevicegroundpinwhileAVSSistheADCgroundpin.TheAVSSpinisbondedtogetherinternallywithVSS.

Note:1.ThisPinDescriptionSummarytabledescribesallresourceswhichmaynotbeconnectedtoexternalpins.2.For28-SKDIP/SOPpackagePB0,PC1,PC2andPC7arenotbondedtoexternalpinsandshouldbeproperlyconfiguredtoavoidafloatingconditionwhichwillresultinadditionalcurrentleakage.

Page 13: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 12 �ove��e� ��� 2�1� Rev. 1.21 13 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Absolute Maximum RatingsSupplyVoltage.................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage...................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature.....................................................................................................-50˚Cto125˚COperatingTemperature...................................................................................................-40˚Cto85˚CIOHTotal................................................................................................................................... -150mAIOLTotal.................................................................................................................................... 100mATotalPowerDissipation.......................................................................................................... 500mW

Note:These are stress ratingsonly.Stresses exceeding the range specifiedunder “AbsoluteMaximumRatings”maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnot impliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.

D.C. CharacteristicsTa=25°C

Symbol ParameterTest Conditons

Min. Typ. Max. UnitVDD Conditons

VDD

Ope�ating Voltage(HXT) —

fSYS=8MHz 2.2 — 5.5 VfSYS=1�MHz 2.� — 5.5 VfSYS=12MHz 3.3 — 5.5 VfSYS=16MHz 4.5 — 5.5 V

Ope�ating Voltage (HIRC) — fSYS=8MHz 2.2 — 5.5 V

IDD

Ope�ating Cu��ent� �o��al Mode�fSYS =fH (HXT)� fS =fLIRC

3V �o load� fSYS= fH =8MHz ADC off� WDT ena�le

— 1.� 1.5 �A5V — 2.5 4.� �A3V �o load� fSYS= fH =1�MHz

ADC off� WDT ena�le— 1.2 2.� �A

5V — 2.8 4.5 �A

5V �o load� fSYS= fH =12MHz ADC off� WDT ena�le — 3.5 5.5 �A

5V �o load� fSYS= fH =16MHz ADC off� WDT ena�le — 4.5 �.� �A

Ope�ating Cu��ent� �o��al Mode�fSYS=fH(HIRC)� fS=fLXT o� fLIRC

3V �o load� fSYS= fH =8MHz ADC off� WDT ena�le

— 1.2 2.� �A5V — 2.8 4.5 �A

Ope�ating Cu��ent� Slow Mode 1fH =12MHz (HXT)� fS =fLIRC

5V �o load� fSYS= fH/2�ADC off� WDT ena�le — 2.1 3.3 �A

5V �o load� fSYS= fH/4�ADC off� WDT ena�le — 1.6 2.5 �A

5V �o load� fSYS= fH/8�ADC off� WDT ena�le — 1.2 2.5 �A

5V �o load� fSYS= fH/16ADC off� WDT ena�le — 1.1 2.� �A

5V �o load� fSYS= fH/32�ADC off� WDT ena�le — 1.� 2.� �A

5V �o load� fSYS= fH/64�ADC off� WDT ena�le — 1.� 2.� �A

Page 14: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 14 �ove��e� ��� 2�1� Rev. 1.21 15 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Symbol ParameterTest Conditons

Min. Typ. Max. UnitVDD Conditons

IDD

Ope�ating Cu��ent� Slow Mode �fSYS=fS=fLXT

3V �o load� ADC off�WDT ena�le� LXTLP=�

— 15 25 μA5V — 3� 5� μA3V �o load� ADC off�

WDT ena�le� LXTLP=1— 1� 2� μA

5V — 25 45 μA

Ope�ating Cu��ent� Slow Mode �fSYS=fS=fLIRC

3V �o load� ADC off�WDT ena�le

— 1� 2� μA5V — 2� 4� μA

ISTB

Stand�y Cu��ent� IDLE Mode (fSYS=off� fS=fSUB= fLIRC)

3V �o load� syste� HALT�IDLE�=1� WDT ena�le

— 1.3 3.� μA5V — 2.2 5.� μA

Stand�y Cu��ent� SLEEP Mode(fSYS=off� fS=fSUB= fLIRC)

3V �o load� syste� HALT�IDLE�=�� WDT ena�le

— 1.3 3.� μA5V — 2.2 5.� μA

Stand�y Cu��ent� SLEEP ModefSYS=12MHz (HXT)� fSYS =off� fS=fSUB= fLIRC

— �o load� syste� HALT� ADC off� WDT ena�le — 65 �5 μA

VIL Input Low Voltage fo� I/O Po�ts5V — � — 1.5 V— — � — �.2VDD V

VIH Input High Voltage fo� I/O Po�ts 5V — 3.5 — 5 V— — �.8VDD — VDD V

IOL

I/O Po�t Sink Cu��entLa�ge Sink I/O (PD)

5V VOL=1.5V 12� 2�� — �A3V VOH=�.1VDD 15 3� — �A5V VOH=�.1VDD 3� 6� — �A

I/O Po�t Sink Cu��ent(PA� PB� PC)

3V VOL=�.1VDD 15 3� — �A5V VOL=�.1VDD 3� 6� — �A

IOHI/O Po�t Sou�ce Cu��ent(PA� PB� PC� PD)

3V

VOH=�.�VDD� select full sou�ce cu��ent option -3.� -6.� — �A

VOH=�.�VDD� select 1�/22 full sou�ce cu��ent option -1.5 -3.� — �A

VOH=�.�VDD� select �/22 full sou�ce cu��ent option -1.� -2.� — �A

VOH=�.�VDD� select 4/22 full sou�ce cu��ent option -�.8 -1.5 — �A

5V

VOH=�.�VDD� select full sou�ce cu��ent option -�.� -18.� — �A

VOH=�.�VDD� select 1�/22 full sou�ce cu��ent option -4.� -8.� — �A

VOH=�.�VDD� select �/22 full sou�ce cu��ent option -3.� -6.� — �A

VOH=�.�VDD� select 4/22 full sou�ce cu��ent option -2.� -3.6 — �A

RPH Pull-high Resistance3V

—2� 6� 1�� kΩ

5V 1� 3� 5� kΩ

IBIAS Bias cu��ent fo� LCD 5V

ISEL[1:�]=�� 4.2 8.3 13 μAISEL[1:�]=�1 8.3 16.� 25 μAISEL[1:�]=1� 25 5� �5 μAISEL[1:�]=11 5� 1�� 15� μA

VSEG_H 1/3 �ias LCD SEG output (SEG_H) 2.2~5.5V �o load �.645 �.6� �.6�5 VDD

VSEG_L 1/3 �ias LCD SEG output (SEG_L) 2.2~5.5V �o load �.3�5 �.33 �.355 VDD

Page 15: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 14 �ove��e� ��� 2�1� Rev. 1.21 15 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

A.C. CharacteristicsTa=25°C

Symbol ParameterTest Conditons

Min. Typ. Max. UnitVDD Conditions

fSYS

Syste� clock (HXT)

2.2V~5.5V

�.4 — 8 MHz2.�V~5.5V �.4 — 1� MHz3.3V~5.5V �.4 — 12 MHz4.5V~5.5V �.4 — 16 MHz

Syste� clock (HIRC) 5V Ta=�°C~��°C -2% 8 2% MHzSyste� clock (LXT) — — — 32�68 — Hz

Syste� clock (LIRC)5V Ta=25°C -1�% 32 +1�% kHz

2.2V~5.5V Ta=-4�°C~85°C -5�% 32 +6�% kHztTIMER xTCKn Input Pin Mini�un Pulse width — — �.�6 �.15 �.3 μs

tSST

Syste� Sta�t-up Ti�e� Pe�iod (wake up f�o� HALT) —

fSYS=HXT 128 — — tSYS

fSYS=LXT 128 — — tSYS

fSYS=HIRC 16 — — tSYS

fSYS=LIRC 2 — — tSYS

Syste� Sta�t-up Ti�e� Pe�iod (wake up f�o� HALT� fSYS on at HALT) — — 2 — — tSYS

tRSTD

Syste� Reset Delay Ti�e(POR� LVR� LVR S/W� WDT S/W �eset) — — 25 5� 1�� �s

Syste� Reset Delay Ti�e(WDT �eset) — — 8.3 16.� 33.3 �s

tI�T Inte��upt Mini�u� Pulse Width — — 1 3.3 5 μstLVR Low Voltage width to �eset — — 12� 24� 48� μstSRESET Softwa�e Reset width to �eset — — 45 �� 12� μstEERD EEPROM Read Ti�e — — 1 2 4 tSYS

tEEWR EEPROM W�ite Ti�e — — 1 2 4 �s

Note:tSYS=1/fSYS

Page 16: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 16 �ove��e� ��� 2�1� Rev. 1.21 1� �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

LVR & LVD CharacteristicsTa=25°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VLVR Low Voltage Reset Voltage —

LVR Ena�le� 2.1�V option

-5%

2.1�

+5%

VLVR Ena�le� 2.55V option 2.55 VLVR Ena�le� 3.15V option 3.15 VLVR Ena�le� 3.8�V option 3.8� V

VLVD Low Voltage Detecto� Voltage —

LVDE� = 1� VLVD = 2.�V

-5%

2.�

+5%

VLVDE� = 1� VLVD = 2.2V 2.2 VLVDE� = 1� VLVD = 2.4V 2.4 VLVDE� = 1� VLVD = 2.�V 2.� VLVDE� = 1� VLVD = 3.�V 3.� VLVDE� = 1� VLVD = 3.3V 3.3 VLVDE� = 1� VLVD = 3.6V 3.6 VLVDE� = 1� VLVD = 4.�V 4.� V

ILVRAdditional Powe� Consu�ption if LVR is Used

3VLVR disa�le→LVR ena�le

— 3� 45 μA5V — 6� �� μA

ILVDAdditional Powe� Consu�ption if LVD is Used

3V LVD disa�le→LVD ena�le(LVR disa�le)

─ 4� 6� μA5V ─ �5 115 μA3V LVD disa�le→LVD ena�le

(LVR ena�le)─ 3� 45 μA

5V ─ 6� �� μAtLVR Low Voltage Width to Reset — — 12� 24� 48� μstLVD Low Voltage Width to Inte��upt — — 65 125 25� μs

tLVDS LVDO sta�le ti�e— LVD disa�le→LVD ena�le

(LVR ena�le) — — 15 μs

— LVD disa�le→LVD ena�le(LVR disa�le) — — 2�� μs

Page 17: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 16 �ove��e� ��� 2�1� Rev. 1.21 1� �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

A/D Converter Electrical CharacteristicsTa=25°C

Symbol ParameterTest Conditons

Min. Typ. Max. UnitVDD Conditons

AVDD A/D Conve�te� Ope�ating Voltage — — 2.2 — 5.5 VVAD ADC Input Voltage — — � — AVDD/VREF VVREF ADC Refe�ence Voltage — — 2 — AVDD+�.1 VtADC A/D Conve�sion Ti�e — 12-�it ADC — 16 — tAD

tAD A/D Clock Pe�iod2.2V~2.�V — 8 — 1� μs2.�V~5.5V — �.5 — 1� μs

tO�2ST A/D Conve�te� On-to-Sta�t Ti�e — — 2 — — μs

D�L1 A/D Diffe�ential �on-linea�ity2.2V~2.�V VREF=VDD� tAD=8μs

Ta=25°C — ±15 — LSB

2.�V~5.5V VREF=VDD� tAD=0.5μs Ta=25°C -3 — +3 LSB

D�L2 A/D Diffe�ential �on-linea�ity 3V/5V VREF=VDD� tAD=0.5μs Ta=-4�°C ~ 85°C -4 — +4 LSB

I�L1 A/D Integ�al �on-linea�ity2.2V~2.�V VREF=VDD� tAD=8μs

Ta=25°C — ±16 — LSB

2.�V~5.5V VREF=VDD� tAD=0.5μs Ta=25°C -4 — +4 LSB

I�L2 A/D Integ�al �on-linea�ity 3V/5V VREF=VDD� tAD=0.5μs Ta=-4�°C ~ 85°C -6 — +6 LSB

IADCAdditonal Powe� consu�ption if A/D Conve�te� is used

3V�o load� tAD=0.5μs

— 1.� 2.� �A5V — 1.5 3.� �A

tBGS VBG tu�n on sta�le ti�e — — 1� — — �sVBG Bandgap �efe�ence with �uffe� voltage — — -5% 1.25 +5% V

IBGAdditional powe� consu�ption if �efe�ence with �uffe� is used — — — 2�� 3�� μA

Power on Reset Electrical CharacteristicsTa = 25°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VPOR VDD Sta�t Voltage to Ensu�e Powe�-on Reset ─ ─ ─ ─ 1�� �VRRVDD VDD Rising Rate to Ensu�e Powe�-on Reset ─ ─ �.�35 ─ ─ V/�s

tPORMini�u� ti�e fo� VDD Stays at VPOR to ensu�e Powe�-on Reset ─ ─ 1� ─ ─ �s

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� � � �

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Page 18: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 18 �ove��e� ��� 2�1� Rev. 1.21 1� �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.ThedevicetakesadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersproviding increasedspeedofoperationandPeriodicperformance.Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,whichcarriesoutarithmeticoperations, logicoperations,rotation, increment,decrement,branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyorindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditionalarchitecturalfeaturesensurethataminimumofexternalcomponents isrequiredtoprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityand flexibility.Thismakes thedevicesuitable for low-cost,high-volumeproductionforcontrollerapplications.

Clocking and PipeliningThemainsystemclock,derivedfromeitheraHXT,LXT,HIRCorLIRCoscillatorissubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedat thebeginningof theT1clockduringwhichtimeanewinstruction isfetched.TheremainingT2~T4clockscarryout thedecodingandexecution functions. In thisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutive instructioncycles, thepipeliningstructureof themicrocontrollerensures thatinstructionsareeffectivelyexecutedinoneinstructioncycle.TheexceptiontothisareinstructionswherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

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System Clock and Pipelining

Page 19: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 18 �ove��e� ��� 2�1� Rev. 1.21 1� �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

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Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas“JMP”or“CALL” thatdemanda jump toanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

DeviceProgram Counter

Program Counter High byte PCL RegisterHT66F488 PC11~PC8 PCL�~PCL�HT66F48� PC12~PC8 PCL�~PCL�

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly,however,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.

Page 20: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 2� �ove��e� ��� 2�1� Rev. 1.21 21 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.TheactivatedlevelisindexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointer isdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresult inastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

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Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA,LADD,LADDM,LADC,LADCM,LSUB,LSUBM,LSBC,LSBCM,LDAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA,LAND,LANDM,LOR,LORM,LXOR,LXORM,LCPL,LCPLA

• Rotation:RRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC,LRR,LRRA,LRRCA,LRRC,LRLA,LRLCA,LRLC

• IncrementandDecrement:INCA,INC,DECA,DEC,LINCA,LINC,LDECA,LDEC

• Branchdecision:JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI,LSNZ,LSZ,LSZA,LSIZ,LSDZ,LSIZA,LSDZA

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthisdevicetheProgramMemoryisFlashtype,whichmeansitcanbeprogrammedandre-programmeda largenumberof times,allowing theuser theconvenienceofcodemodificationon thesamedevice.Byusing theappropriateprogramming tools, thisFlashdeviceoffersusers the flexibility toconvenientlydebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof4K×16bits to8K×16bits.TheProgramMemory isaddressedbytheProgramCounterandalsocontainsdata, tableinformationandinterruptentries.Tabledata,whichcanbesetup inany locationwithin theProgramMemory, isaddressedbyaseparatetablepointerregister.

Device CapacityHT66F488 4K×16HT66F48� 8K×16

0000H Reset

Interrupt Vector

0004H

003CH

0FFFH 16 bits

HT66F488

0000H Reset

Interrupt Vector

0004H

003CH

1FFFH 16 bits

HT66F489

Program Memory Structure

Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000His reserved foruseby thedevice reset forprograminitialisation.Afteradevice reset isinitiated,theprogramwilljumptothislocationandbeginexecution.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressof thelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe“TABRD[m]”or“TABRDL[m]”instructionsrespectivelywhenthememory[m]is locatedinsector0.Ifthememory[m]islocatedinothersectors,thetabledatacanberetrievedfromtheProgramMemoryusingthe“LTABRD[m]”or“LTABRDL[m]”instructionsrespectively.Whentheinstructionisexecuted,thelowerordertablebytefromtheProgramMemorywillbetransferredtotheuserdefinedDataMemoryregister[m]asspecifiedintheinstruction.ThehigherordertabledatabytefromtheProgramMemorywillbetransferredtotheTBLHspecialregister.Anyunusedbitsinthistransferredhigherorderbytewillbereadas0.

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

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Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis“F00H”whichreferstothestartaddressofthelastpagewithinthe4KwordsProgramMemoryoftheHT66F488device.Thetablepointerissetupheretohaveaninitialvalueof“06H”.ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress“F06H”or6locationsafterthestartofthepresentpage.Notethatthevalueforthetablepointerisreferencedtothefirstaddressofthelastpageifthe“TABRDL[m]”or“LTABRDL[m]”instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRDL[m]”or“LTABRDL[m]”instructionisexecuted.

BecausetheTBLHregisteraread/writeregisterandcanberestored,careshouldbetakentoensureitsprotectionifboththemainroutineandInterruptServiceRoutineusetablereadinstructions.Ifusingthetablereadinstructions,theInterruptServiceRoutinesmaychangethevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleit isrecommendedthatsimultaneoususeof thetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatall tablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2::mov a,06h ; initialise low table pointer - note that this address is referencedmov tblp,a ; to the last page ::tabrdl tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address “F06H” transferred to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrdl tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address “F05H” transferred to ; tempreg2 and TBLH ; in this example the data “1AH” is transferred to tempreg1 and data “0FH” ; to register tempreg2::org F00h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh::

In Circuit ProgrammingTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

TheHoltekFlashMCUtoWriterProgrammingPincorrespondencetableisasfollows:

Holtek Write Pins MCU Programming Pins FunctionICPDA PD� P�og�a��ing Se�ial DataICPCK PB4 P�og�a��ing Se�ial ClockVDD VDD Powe� SupplyVSS VSS G�ound

TheProgramMemoryandEEPROMdatamemorycanbothbeprogrammedseriallyin-circuitusingthis4-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefortheclock.Twoadditionallinesarerequiredforthepowersupplyandground.Thetechnicaldetailsregardingthein-circuitprogrammingofthedevicearebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.

During theprogrammingprocess, theusermust takecare toensure thatnootheroutputsareconnectedtothePD0andPB4pins.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

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Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1korthecapacitanceof*mustbelessthan1nF.

On-Chip Debug Support – OCDSThereisanEVchip,HT66V488/489,whichisusedtoemulatetheHT66F488/HT66F489device.ThisEVchipdevicealsoprovidesan“On-ChipDebug”functiontodebugthedeviceduringthedevelopmentprocess.TheEVchipandtheactualMCUdevicesarealmostfunctionallycompatibleexceptforthe“On-ChipDebug”function.UserscanusetheEVchipdevicetoemulatetherealchipdevicebehaviorbyconnectingtheOCDSDAandOCDSCKpinstotheHoltekHT-IDEdevelopmenttools.TheOCDSDApinistheOCDSData/Addressinput/outputpinwhiletheOCDSCKpinistheOCDSclockinputpin.WhenusersusetheEVchipfordebugging,otherfunctionswhicharesharedwiththeOCDSDAandOCDSCKpinsintheactualMCUdevicewillhavenoeffectintheEVchip.ForamoredetailedOCDSdescription,refertothecorrespondingdocumentnamed“Holteke-Linkfor8-bitMCUOCDSUser’sGuide”.

Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSDA OCDSDA OCDS Data/Add�ess input/outputOCDSCK OCDSCK OCDS Clock input

VDD VDD Powe� SupplyG�D VSS G�ound

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

RAM Data MemoryTheDataMemoryisan8-bitwideRAMinternalmemoryandis the locationwhere temporaryinformationisstored.

Dividedintotwotypes,thefirstofDataMemoryisanareaofRAMwherespecialfunctionregistersare located.Theseregistershavefixed locationsandarenecessary forcorrectoperationof thedevice.Manyof theseregisterscanbereadfromandwritten todirectlyunderprogramcontrol,however, someremainprotected fromusermanipulation.ThesecondareaofDataMemory isreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.

StructureTheDataMemory isdivided intoseveral sectors,allofwhichare implemented in8-bitwideMemory.EachoftheDataMemorysectorsiscategorizedintotwotypes,theSpecialPurposeDataMemoryandtheGeneralPurposeDataMemory.

ThestartaddressoftheSpecialPurposeDataMemoryforalldevicesistheaddress00HwhilethestartaddressoftheGeneralPurposeDataMemoryistheaddress80H.TheSpecialPurposeDataMemoryregistersareaccessible inallsectors,withtheexceptionof theEECregisterataddress40H,whichisonlyaccessibleinSector1.

Device Capacity Sectors

HT66F488HT66F48� Gene�al Pu�pose: 384×8

�: 8�H~FFH1: 8�H~FFH 2: 8�H~FFH

Special PurposeData Memory

General PurposeData Memory

00H

7FH80H

FFH

Sector 0

40H in sector 1

Sector 0Sector 1

Sector 2

Data Memory Structure

General Purpose Data Memory Thereare384bytesofgeneralpurposememorywhicharearrangedin80H~FFHofSector0~Sector2.Allmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.Thegeneralpurposedatamemoryisfullyaccessiblebytheuserprogramforbothreadandwritingoperations.Byusing the"SET[m].i"and"CLR[m].i" instructions individualbitscanbesetorresetunderprogramcontrolgivingtheusera largerangeofflexibilityforbitmanipulationintheDataMemory.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Special Purpose Data Memory This area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller, are stored.Theyareoverlapped inanysector.Mostof the registersarebothreadableandwritablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunusedbefore80H,anyreadinstructiontotheseaddresseswillreturnthevalue"00H".

Unused

Unused

��H IAR��1H MP��2H IAR1�3H MP1L�4H�5H ACC�6H PCL��H TBLP�8H TBLH��H TBHP�AH STATUS�BH

STMRP

�CH

SIMC1

�DH

STMAH

�EH

SIMD

�FH1�H

CTMDL

11H

CTMDH

12H

1�H

I�TC1

18H

I�TC�

1BH1AH

1DH1CH

1FH

I�TC2I�TC3

1EH

SMOD

13H14H

STMC�

15H

STMC1

16H1�H

STMDL

Secto� �~2

SIMC2/SIMA

SIMC�

PAWU

MFI1MFI2

PAPUPA

PAC

PBPBC

PCPU

PCCPDPU

PD

IOHR�IOHR1

ADRHADCR�ADCR1

TMPC�CTMC�CTMC1

2�H21H22H

2�H28H

2BH2AH

2DH2CH

2FH2EH

23H24H25H26H2�H

3�H31H32H

3�H38H

3BH3AH

3DH3CH

3FH3EH

33H34H35H36H3�H

4�H EEC41H EEA42H EED43H

PTM1RPL

4�H

PTM1RPH

48H

PTM�RPH4�H

I�TEG�

4AH

I�TEG1

4BH

WDTC

4CH

TBC

4DH

PTM1AL4EH

PTM1AH4FH5�H51H52H

58H

53H54H55H56H5�H

Secto� �� 2 Secto� 1Unused

PTM�AHPTM�RPL

PTM1C�PTM1C1PTM1DLPTM1DH

CTRL

6�H61H

MP1H

IAR2MP2LMP2H

Unused

MFI�

PBPU

PC

PDC

ADRLUnused

CTMALCTMAH

STMDHSTMAL

SIMTOC

44H45H46H

5�H5AH5BH5CH5DH5EH5FH

LVRCLVDC

USRUCR1UCR2BRG

TXR/RXRSLCDC�SLCDC1SLCDC2SLCDC3

62H63H64H65H66H6�H68H6�H

SLCDC4

IOHR2IOHR3

6AH6BH

6DH6CH

6EH6FH

PTM�ALPTM�DH

��H�1H�2H�3H�4H�5H�6H��H�8H��H�AH�BH

�DH�CH

�EH�FH

: Unused� �ead as ��H

PTM�C�PTM�C1

ACERL

UnusedUnusedUnused

UnusedUnusedUnusedUnusedUnusedUnusedUnusedUnusedUnusedUnusedUnused

UnusedUnused

UnusedUnusedUnusedUnusedUnusedUnusedUnusedUnusedUnused

PTM�DL

Special Purpose Data Memory

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsections,howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Register – IAR0, IAR1, IAR2TheIndirectAddressingRegisters,IAR0,IAR1andIAR2,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.Themethodof indirectaddressing forRAMdatamanipulationuses these IndirectAddressingRegistersandMemoryPointers, incontrast todirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0,IAR1andIAR2registerswillresult innoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0,MP1L/MP1HorMP2L/MP2H.Actingasapair, IAR0andMP0cantogetheraccessdataonlyfromSector0while theIAR1register togetherwithMP1L/MP1HregisterpairandIAR2registertogetherwithMP2L/MP2HregisterpaircanaccessdatafromanyDataMemorysector.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1L, MP1H, MP2L, MP2HFiveMemoryPointers,knownasMP0,MP1L,MP1H,MP2LandMP2H,areprovided.TheseMemoryPointersarephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister, IAR0,areused toaccessdata fromSector0,whileMP1L/MP1HtogetherwithIAR1andMP2L/MP2HtogetherwithIAR2areusedtoaccessdatafromalldatasectorsaccordingtothecorrespondingMP1HorMP2Hregister.DirectAddressingcanbeusedinalldatasectorsusingthecorrespondinginstructionwhichcanaddressallavailabledatamemoryspace.

ThefollowingexampleshowshowtoclearasectoroffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Indirect Addressing Program Example 1data .section ‘data’adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 codeorg 00hstart:mov a, 04h ; setup size of blockmov block, amov a, offset adres1 ; Accumulator loaded with first RAM addressmov mp0, a ; setup memory pointer with first RAM addressloop: clr IAR0 ; clear the data at address defined by MP0inc mp0 ; increment memory pointersdz block ; check if last memory location has been clearedjmp loopcontinue:

Indirect Addressing Program Example 2data .section at 01F0H ´data´adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 code´org00hstart: mov a,04h ; setup size of block mov block,a mov a, 01h ; setup the memory sector mov mp1h, a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp1l,a ; setup memory pointer with first RAM addressloop: clr IAR1 ; clear the data at address defined by MP1L inc mp1l ; increment memory pointer MP1L sdz block ; check if last memory location has been cleared jmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuser-definedregisterandanother, it isnecessary todo thisbypassing thedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-up Table Registers – TBLP, TBHP, TBLHThesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointersandindicate thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

Status Register – STATUS This8-bitregistercontainstheSCflag,CZflag,zeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe“CLRWDT”or“HALT”instruction.ThePDFflagisaffectedonlybyexecutingthe“HALT”or“CLRWDT”instructionorduringasystempower-up.

TheZ,OV,AC,C,SCandCZflagsgenerallyreflectthestatusofthelatestoperations.

• SCistheresultofthe“XOR”operationwhichisperformedbytheOVflagandtheMSBofthecurrentinstructionoperationresult.

• CZistheoperationalresultofdifferentflagsfordifferentinstuctions.Refertoregisterdefinitionsformoredetails.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OVisset ifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDFisclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.

• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

STATUS Register

Bit 7 6 5 4 3 2 1 0�a�e SC CZ TO PDF OV Z AC CR/W R/W R/W R R R/W R/W R/W R/WPOR x x � � x x x x

“x” unknownBit7 SC:Theresultofthe“XOR”operationwhichisperformedbytheOVflagandthe

MSBoftheinstructionoperationresult.Bit6 CZ:Thetheoperationalresultofdifferentflagsfordifferentinstructions.

ForSUB/SUBM/LSUB/LSUBMinstructions,theCZflagisequaltotheZflag.ForSBC/SBCM/LSBC/LSBCMinstructions, theCZflag is the“AND”operationresultwhichisperformedbythepreviousoperationCZflagandcurrentoperationzeroflag.Forotherinstructions,theCZflagwillnotbeaffected.

Bit5 TO:WatchdogTime-Outflag0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe“CLRWDT”instruction1:Byexecutingthe“HALT”instruction

Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

EEPROM Data MemoryOneofthespecialfeaturesinthedeviceisitsinternalEEPROMDataMemory.EEPROM,whichstandsforElectricallyErasableProgrammableReadOnlyMemory,isbyitsnatureanon-volatileformofmemory,withdataretentionevenwhenitspowersupply is removed.Byincorporatingthiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproduct identificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproductinformationtobestoreddirectlywithintheproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.

EEPROM Data Memory StructureTheEEPROMDataMemorycapacity is64×8bitsfor thedevice.Unlike theProgramMemoryandRAMDataMemory, theEEPROMDataMemoryisnotdirectlymappedintomemoryspaceandisthereforenotdirectlyaddressableinthesamewayastheothertypesofmemory.ReadandWriteoperationstotheEEPROMarecarriedoutinsinglebyteoperationsusinganaddressanddataregisterinSector0andasinglecontrolregisterinSector1.

EEPROM RegistersThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregister,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinallsectors, theycanbedirectlyaccessedinthesamewasasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinSector1,cannotbedirectlyaddresseddirectlyandcanonlybereadfromorwrittentoindirectlyusingtheMP1L/MP1HorMP2L/MP2HMemoryPointerandIndirectAddressingRegister, IAR1orIAR2.BecausetheEECcontrolregisterislocatedataddress40HinSector1,theMP1LorMP2LMemoryPointerlowbytemustfirstbesettothevalue40HandtheMP1HorMP2HMemoryPointerhighbytesettothevalue01HbeforeanyoperationsontheEECregisterareexecuted.

RegisterName

Bit

7 6 5 4 3 2 1 0EEA — — D5 D4 D3 D2 D1 D�EED D� D6 D5 D4 D3 D2 D1 D�EEC — — — — WRE� WR RDE� RD

EEPROM Control Registers List

EEA Register

Bit 7 6 5 4 3 2 1 0�a�e — — D5 D4 D3 D2 D1 D�R/W — — R/W R/W R/W R/W R/W R/WPOR — — � � � � � �

Bit7~6 Unimplemented,readas“0”Bit5~0 D5~D0:DataEEPROMaddress

DataEEPROMaddressbit5~bit0

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

EED Register

Bit 7 6 5 4 3 2 1 0�a�e D� D6 D5 D4 D3 D2 D1 D�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~0 D7~D0:DataEEPROMdataDataEEPROMdatabit7~bit0

EEC Register

Bit 7 6 5 4 3 2 1 0�a�e — — — — WRE� WR RDE� RDR/W — — — — R/W R/W R/W R/WPOR — — — — � � � �

Bit7~4 Unimplemented,readas“0”Bit3 WREN:DataEEPROMWriteEnable

0:Disable1:Enable

This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.

Bit2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle

This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.

Bit1 RDEN:DataEEPROMReadEnable0:Disable1:Enable

This is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.

Bit0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle

This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENhasnotfirstbeensethigh.

Note:TheWREN,WR,RDENandRDcannotbesetto“1”atthesametimeinoneinstruction.TheWRandRDcannotbesetto“1”atthesametime.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Reading Data from the EEPROM ToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbit todeterminewhenthedataisvalidforreading.

Writing Data to the EEPROMTheEEPROMaddressofthedatatobewrittenmustfirstbeplacedintheEEAregisterandthedataplacedintheEEDregister.TowritedatatotheEEPROM,thewriteenablebit,WREN,intheEECregistermustfirstbesethightoenablethewritefunction.Afterthis,theWRbitintheEECregistermustbe immediatelysethighto initiateawritecycle.These twoinstructionsmustbeexecutedconsecutively.Theglobal interruptbitEMIshouldalsofirstbeclearedbefore implementinganywriteoperations,andthensetagainafterthewritecyclehasstarted.SettingtheWRbithighwillnotinitiateawritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycleiscontrolledusinganinternaltimerwhoseoperationisasynchronoustomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallyclearedtozerobythemicrocontroller,informingtheuserthatthedatahasbeenwrittentotheEEPROM.TheapplicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.

Write ProtectionProtectionagainst inadvertentwriteoperation isprovided inseveralways.After thedevice ispowered-on theWriteEnablebit in thecontrol registerwillbeclearedpreventinganywriteoperations.Alsoatpower-onMP1L/MP1HandMP2L/MP2Hwillbereset tozero,whichmeansthatDataMemorySector0willbeselected.AstheEEPROMcontrolregisterislocatedinSector1,thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.

EEPROM InterruptTheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheDEEbit in therelevant interruptregister.WhenanEEPROMwritecycleends,theDEFrequestflagwillbeset.IftheglobalandEEPROMinterruptsareenabledandthestackisnotfull,ajumptotheassociatedInterruptvectorwilltakeplace.WhentheinterruptisservicedtheEEPROMinterruptflagwillbeautomaticallyreset.MoredetailscanbeobtainedintheInterruptsection.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Programming ConsiderationsCaremustbetakenthatdataisnotinadvertentlywrittentotheEEPROM.ProtectioncanbePeriodicbyensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheBankPointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROMcontrol register exist.Althoughcertainlynotnecessary, considerationmightbegiven in theapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.Theglobal interruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.Notethatthedeviceshouldnotenter theIDLEorSLEEPmodeuntil theEEPROMreadorwriteoperationis totallycomplete.Otherwise,theEEPROMreadorwriteoperationwillfail.

Programming Examples

Reading data from the EEPROM - polling methodMOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, 040H ; setup memory pointer MP1LMOV MP1L, A ; MP1 points to EEC registerMOV A, 01H ; setup memory pointer MP1HMOV MP1H, ASET IAR1.1 ; set RDEN bit, enable read operationsSET IAR1.0 ; start Read Cycle - set RD bitBACK:SZ IAR1.0 ; check for read cycle endJMP BACKCLR IAR1 ; disable EEPROM read/writeCLR BPMOV A, EED ; move read data to registerMOV READ_DATA, A

Writing Data to the EEPROM - polling methodMOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, EEPROM_DATA ; user defined dataMOV EED, AMOV A, 040H ; setup memory pointer MP1LMOV MP1L, A ; MP1 points to EEC registerMOV A, 01H ; setup memory pointer MP1HMOV MP1H, ACLR EMI ; diable global interruptSET IAR1.3 ; set WREN bit, enable write operationsSET IAR1.2 ; start Write Cycle - set WR bitSET EMI ; enable global interruptBACK:SZ IAR1.2 ; check for write cycle endJMP BACKCLR IAR1 ; disable EEPROM writeCLR MP1H

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

OscillatorVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughacombinationofconfigurationoptionsandregisters.

Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfortheWatchdogTimerandTimeBaseInterrupts.Theexternaloscillatorsrequiringsomeexternalcomponentsaswellasfully integrated internaloscillatorsrequiringnoexternalcomponentsareprovided to formawide rangeofboth fastandslowsystemoscillators.Alloscillatoroptionsareselected through theconfigurationoptions.Thehigherfrequencyoscillatorprovideshigherperformancebutcarrywithit thedisadvantageofhigherpowerrequirements,whiletheoppositeisofcoursetrueforthelowerfrequencyoscillators.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock, thedevicehas theflexibility tooptimize theperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Freq. PinsExte�nal C�ystal HXT 4��kHz~2�MHz OSC1/OSC2Inte�nal High Speed RC HIRC 8MHz —Exte�nal low speed C�ystal LXT 32.�68kHz XT1/XT2Inte�nal Low Speed RC LIRC 32kHz —

Oscillator Types

System Clock ConfigurationsTherearefourmethodsofgeneratingthesystemclock,twohighspeedoscillatorsandtwolowspeedoscillators.Thehighspeedoscillatorsaretheexternalcrystaloscillatorandtheinternal8MHzRCoscillator.Thelowspeedoscillatorsaretheexternal32.768kHzcrystaloscillatorandinternal32kHzRCoscillator.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.

Theactualsourceclockusedforeachof thehighspeedandthe lowspeedoscillators ischosenviaconfigurationoptions.Thefrequencyof theslowspeedorhighspeedsystemclock isalsodeterminedusing theHLCLKbitandCKS2~CKS0bits in theSMODregister.Note that twooscillatorselectionsmustbemadenamelyonehighspeedandonelowspeedsystemoscillators.Itisnotpossibletochooseano-oscillatorselectionforeitherthehighorlowspeedoscillator.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

HXT

High Speed Oscillators

HIRC

Low Speed Oscillators

fH 6-stage Prescaler

High Speed Oscillator Configuration Option

HLCLK, CKS2~CKS0 bits

fH/2fH/4

fH/8fH/16

fH/32fH/64

fL

Fast Wake-up from SLEEP Mode or IDLE Mode Control (for HXT only)

fSYS

fSUB

fLLXT

LIRC

Low Speed Oscillator Configuration Option

Note:TheOSC1/XT1andOSC2/XT2share thesamepins,so theHXToscillatorand theLXToscillatorcannotbeselectedatthesametime.

System Clock Configurations

External Crystal/Ceramic Oscillator – HXTTheExternalCrystal/CeramicSystemOscillator isoneof thehighfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Formostcrystaloscillatorconfigurations, thesimpleconnectionofacrystalacrossOSC1andOSC2willcreatethenecessaryphaseshiftandfeedbackforoscillation,withoutrequiringexternalcapacitors.However,forsomecrystaltypesandfrequencies,toensureoscillation, itmaybenecessarytoaddtwosmallvaluecapacitors,C1andC2.Usingaceramicresonatorwillusuallyrequiretwosmallvaluecapacitors,C1andC2,tobeconnectedasshownforoscillationtooccur.ThevaluesofC1andC2shouldbeselectedinconsultationwiththecrystalorresonatormanufacturer’sspecification.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk, it isimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwithinterconnectinglinesarealllocatedasclosetotheMCUaspossible.

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Crystal/Resonator Oscillator – HXT

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Crystal Oscillator C1 and C2 Values

Crystal Frequency C1 C212MHz �pF �pF8MHz �pF �pF4MHz �pF �pF1MHz 1��pF 1��pF

�ote: C1 and C2 values a�e fo� guidance only.

Crystal Recommended Capacitor Values

Internal RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.The internalRCoscillator has a fixed frequency of 8MHz.Device trimming during themanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethat theinfluenceof thepowersupplyvoltage, temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandattemperatureof25°Cdegrees,thefixedoscillationfrequencyoftheHIRCwillhaveatolerancewithin2%.PB3andPB4canbeusedasnormalI/Opins.

External 32.768kHz Crystal Oscillator – LXTTheExternal32.768kHzCrystalSystemOscillatorisoneofthelowfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Thisclocksourcehasafixedfrequencyof32.768kHzandrequiresa32.768kHzcrystaltobeconnectedbetweenpinsXT1andXT2.Theexternalresistorandcapacitorcomponentsconnectedtothe32.768kHzcrystalarenecessarytoprovideoscillation.Forapplicationswhereprecise frequenciesareessential, thesecomponentsmayberequired toprovidefrequencycompensationduetodifferentcrystalmanufacturingtolerances.Duringpower-upthereisatimedelayassociatedwiththeLXToscillatorwaitingforittostart-up.

WhenthemicrocontrollerenterstheSLEEPorIDLEMode,thesystemclockisswitchedofftostopmicrocontrolleractivityand toconservepower.However, inmanymicrocontrollerapplicationsitmaybenecessary tokeep the internal timersoperationalevenwhenthemicrocontroller is intheSLEEPorIDLEMode.Todothis,anotherclock, independentof thesystemclock,mustbeprovided.

However,forsomecrystals,toensureoscillationandaccuratefrequencygeneration,itisnecessarytoadd twosmallvalueexternalcapacitors,C1andC2.TheexactvaluesofC1andC2shouldbeselectedinconsultationwiththecrystalorresonatormanufacturerspecification.Theexternalparallelfeedbackresistor,Rp,isrequired.

SomeconfigurationoptionsdetermineiftheXT1/XT2pinsareusedfortheLXT/HXToscillatororasI/Opins.

• IftheLXToscillatorisnotusedforanyclocksource,theXT1/XT2pinscanbeusedasnormalI/OpinsorHXToscillator.

• IftheLXToscillatorisusedforanyclocksource,the32.768kHzcrystalshouldbeconnectedtotheXT1/XT2pins.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk, it isimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwithinterconnectinglinesarealllocatedasclosetotheMCUaspossible.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

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External LXT Oscillator

LXT Oscillator C1 and C2 Values

Crystal Frequency C1 C232.�68kHz 1�pF 1�pF

�ote: 1. C1 and C2 values a�e fo� guidance only.2. RP=5MΩ~10MΩ is recommended.

32.768kHz Crystal Recommended Capacitor Values

LXT Oscillator Low Power Function TheLXToscillatorcanfunctioninoneoftwomodes,theQuickStartModeandtheLowPowerMode.ThemodeselectionisexecutedusingtheLXTLPbitintheTBCregister.

LXTLP LXT Mode� Quick Sta�t Mode1 Low Powe� Mode

Afterpoweron,theLXTLPbitwillbeautomaticallyclearedtozeroensuringthattheLXToscillatoris in theQuickStartoperatingmode.IntheQuickStartModetheLXToscillatorwillpowerupandstabilisequickly.However,after theLXToscillatorhas fullypoweredup itcanbeplacedintotheLow-powermodebysettingtheLXTLPbithigh.Theoscillatorwillcontinuetorunbutwithreducedcurrentconsumption,asthehighercurrentconsumptionisonlyrequiredduringtheLXToscillatorstart-up.Inpowersensitiveapplications,suchasbatteryapplications,wherepowerconsumptionmustbekepttoaminimum,itisthereforerecommendedthattheapplicationprogramsetstheLXTLPbithighabout2secondsafterpower-on.

Itshouldbenotedthat,nomatterwhatconditiontheLXTLPbit issetto, theLXToscillatorwillalwaysfunctionnormally,theonlydifferenceisthatitwilltakemoretimetostartupifintheLow-powermode.

Internal 32kHz Oscillator – LIRCThe Internal32kHzSystemOscillator is the lowfrequencyoscillator. It isa fully integratedRCoscillatorwitha typicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor itsimplementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationson theoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandatatemperatureof25°Cdegrees,thefixedoscillationfrequencyof32kHzwillhaveatolerancewithin10%.

Supplementary OscillatorThelowspeedoscillator, inadditiontoprovidingasystemclocksource isalsoused toprovideaclocksource to twootherdevicefunctions.Theseare theWatchdogTimerandtheTimeBaseInterrupts.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcoursevice-versa, lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovided thisdevicewithbothhighand lowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationoftheirmicrocontrollertoachievethebestperformance/powerratio.

System ClocksThedevicehasmanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockoptionsusingconfigurationoptionsandregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

Themainsystemclock,cancomefromeitherahighfrequency,fH,oralowfrequency,fL,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.ThehighspeedsystemclockcanbesourcedfromeitheranHXTorHIRCoscillator,selectedviaaconfigurationoption.ThelowspeedsystemclocksourcecanbesourcedfrominternalclockfL.IffL isselectedthenitcanbesourcedbyeithertheLXTorLIRCoscillator,selectedviaaconfigurationoption.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

Therearetwoadditionalinternalclocksfor theperipheralcircuits, thesubstituteclock,fSUB,andtheTimeBaseclock,fTBC.EachoftheseinternalclocksissourcedbytheLIRCorLXToscillator.ThefSUBclockisusedtoprovideasubstituteclockforthemicrocontrollerjustafterawake-uphasoccurredtoenablefasterwake-uptimes.ThefSUB isusedfor theWatchdogTimerwhile thefTBCprovidestheclockfortheTimebaseandTMs.

HXT

High Speed Oscillato�s

HIRC

Low Speed Oscillato�s

fH 6-stage P�escale�

High Speed Oscillato� Configu�ation Option

HLCLK� CKS2~CKS� �its

fH/2

fH/4

fH/8

fH/16

fH/32

fH/64

fL

Fast Wake-up f�o� SLEEP Mode o� IDLE Mode Cont�ol (fo� HXT only)

fSYS

fSUB

WDTfSUB

fSYS/4Ti�e BasefTB

TBCK

fTBC

fLLXT

LIRC

Low Speed Oscillato� Configu�ation Option

System Clock ConfigurationsNote:WhenthesystemclocksourcefSYS isswitchedtofLfromfH, thehighspeedoscillationwill

stoptoconservethepower.ThusthereisnofH~fH/64forperipheralcircuittouse.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

System Operation ModesThereare6differentmodesofoperationfor themicrocontroller,eachonewith itsownspecialcharacteristics andwhich canbe chosen according to the specific performance andpowerrequirements of the application.There are threemodes allowingnormal operationof themicrocontroller, theNORMAL,SLOW0andSLOW1Mode.The remaining threemodes, theSLEEP, IDLE0and IDLE1Modesareusedwhen themicrocontrollerCPUis switchedoff toconservepower.

OperatingMode

Description

CPU fSYS fSUB fTBC

�ORMAL �ode On fH~fH/64 On OnSLOW� �ode On fL On OnSLOW1 �ode On fH/2~fH/64 On OnILDE� �ode Off Off On OnIDLE1 �ode Off On On OnSLEEP �ode Off Off On Off

NORMAL ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbyoneofthehighspeedoscillators.Thismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromoneofthehighspeedoscillators,HXTorHIRC.

SLOW0 ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.TheclocksourceusedwillbefromthelowspeedoscillatorLIRCorLXT.Runningthemicrocontrollerinthismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode0,thefHisoff.

SLOW1 ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom2to64,theactualratiobeingselectedbytheCKS2~CKS0bitsintheSMODregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

SLEEP ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandtheIDLENbitintheSMODregisterislow.IntheSLEEPmodetheCPUwillbestopped.HoweverthefSUBclockwillcontinuetooperateastheWatchdogTimerclock.

IDLE0 ModeTheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutsomeperipheralfunctionswillremainoperationalsuchastheWatchdogTimerandTMs.IntheIDLE0Mode,thesystemoscillatorwillbestopped.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

IDLE1 ModeTheIDLE1ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclocksourcetokeepsomeperipheralfunctionsoperationalsuchastheWatchdogTimerandTMs.IntheIDLE1Mode,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1ModetheWatchdogTimerclock,fSUB,willbeon.

Control RegisterAsingleregister,SMOD,isusedforoverallcontroloftheinternalclockswithinthedevice.

SMOD Register

Bit 7 6 5 4 3 2 1 0�a�e CKS2 CKS1 CKS� FSTE� LTO HTO IDLE� HLCLKR/W R/W R/W R/W R/W R R R/W R/WPOR � � � � � � 1 1

Bit7~5 CKS2 ~ CKS0:ThesystemclockselectionbitswhenHLCLK=0000:fL(LIRCorLXT)001:fL(LIRCorLXT)010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2

Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.Inadditiontothesystemclocksource,whichcanbetheLIRCorLXT,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.

Bit4 FSTEN:FastWake-upControl(onlyforHXT)0:Disable1:Enable

This is theFastWake-upControlbitwhichdetermines if the fSUBclocksource isinitiallyusedafterthedevicewakesup.Whenthebitishigh,thefSUBclocksourcecanbeusedasatemporarysystemclocktoprovideafasterwakeuptimeasthefSUBclockisavailable.

Bit3 LTO:Lowspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeedsystemoscillatorisstableafterpoweronreset.

Bit2 HTO:Highspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstable.Thisflagisclearedto“0”byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas“1”bytheapplicationprogramafterdevicepower-on.TheflagwillbelowwhenintheSLEEP,IDLE0orSLOW0Mode,butafterpoweronresetorawake-uphasoccurred,theflagwillchangetoahighlevelafter128clockcyclesiftheHXToscillatorisusedandafter15~16clockcyclesiftheHIRCoscillatorisused.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Bit1 IDLEN:IDLEModeControl0:Disable1:Enable

This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.

Bit0 HLCLK:SystemClockSelection0:fH/2~fH/64orfL1:fH

Thisbit isusedtoselectif thefHclockorthefH/2~fH/64orfLclockisusedasthesystemclock.WhenthebitishighthefHclockwillbeselectedandiflowthefH/2~fH/64orfLclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefLclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.

CTRL Register

Bit 7 6 5 4 3 2 1 0�a�e FSYSO� — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR � — — — — � � �

Bit7 FSYSON:fSYSControlIDLEMode0:Disable1:Enable

Bit6~3 Unimplemented,readas“0”Bit2 LVRF:LVRfunctionresetflag

DescribeelsewhereBit1 LRF:LVRCregistersoftwareresetflag

DescribeelsewhereBit0 WRF:WDTCregistersoftwareresetflag

Describeelsewhere

Fast Wake-upTominimisepowerconsumptionthedevicecanentertheSLEEPorIDLE0Mode,wherethesystemclocksourcetothedevicewillbestopped.Howeverwhenthedeviceiswokenupagain,itcantakeaconsiderabletimefortheoriginalsystemoscillatortorestart,stabiliseandallownormaloperationtoresume.ToensurethedeviceisupandrunningasfastaspossibleaFastWake-upfunctionisprovided,whichallowsfSUB, toactasatemporaryclocktofirstdrivethesystemuntiltheoriginalsystemoscillatorhasstabilised.ThetemporaryclockissourcedbytheLIRCorLXToscillator.AstheclocksourcefortheFastWake-upfunctionisfSUB,theFastWake-upfunctionisonlyavailableintheSLEEPandIDLE0modes.TheFastWake-upenable/disablefunctioniscontrolledusingtheFSTENbitintheSMODregister.

If theHXToscillator isselectedas theNORMALModesystemclock,andif theFastWake-upfunctionisenabled, thenitwill takeonetotwotSUBclockcyclesforthesystemtowake-up.ThesystemwilltheninitiallyrununderthefSUBclocksourceuntil128HXTclockcycleshaveelapsed,atwhichpointtheHTOflagwillswitchhighandthesystemwillswitchovertooperatingfromtheHXToscillator.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

If theHIRCoscillatorsorLIRCoscillatorisusedasthesystemoscillatorthenitwill take15~16clockcyclesor1~2cyclestowakeupthesystemfromtheSLEEPorIDLE0Mode.TheFastWake-upbit,FSTENwillhavenoeffectinthesecases.

System Oscillator FSTEN Bit Wake-up Time

(SLEEP Mode)Wake-up Time (IDLE0 Mode)

Wake-up Time (IDLE1 Mode)

HXT

� 128 HXT cycles 1~2 HXT cycles

11~2 fSUB cycles(Syste� �uns with fSUB first for 128 HXT cycles and then switches ove� to �un with the HXT clock)

1~2 HXT cycles

HIRC × 15~16 HIRC cycles 1~2 HIRC cyclesLIRC × 1~2 LIRC cycles 1~2 LIRC cyclesLXT × 128 LXT cycles 1~2 LXT cycles

Wake-up Times

Operating Mode Switching Thedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionof theIDLENbit in theSMODregisterandFSYSONintheCTRLregister.

WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfL.IftheclockisfromthefL,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofotherinternalfunctionssuchas theTMs.Theaccompanyingflowchartshowswhathappenswhenthedevicemovesbetweenthevariousoperatingmodes.

NORMAL Mode to SLOW0 Mode SwitchingWhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower, thesystemclockcanswitch to run in theSLOW0Modebysetting theHLCLKbitto“0”andsettingtheCKS2~CKS0bitsto“000”or“001”intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.TheSLOWModeissourcedfromtheLIRCorLXToscillatorandthereforerequirestheseoscillatorstobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

NORMAL Mode to SLOW1 Mode SwitchingWhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower, thesystemclockcanswitch to run in theSLOW1Modebysetting theHLCLKbit to“0”andsetting theCKS2~CKS0bits to“010”,“011”,“100”,“101”,“110”or“111”intheSMODregister.Thiswillthenuseadividedclockofthehighspeedsystemoscillatorwhichcanreducetheoperatingcurrent.TheSLOW1ModeisstillsourcedfromtheHIRCorHXToscillatorandthereforerequireslesstimeforfullmodeswitching.

SLOW0 Mode to NORMAL Mode Switching InSLOW0ModethesystemusesLIRCorLXTlowspeedsystemoscillator.ToswitchbacktotheNORMALMode,wherethehighspeedsystemoscillatorisused,theHLCLKbitshouldbesetto“1”.Asacertainamountoftimewillberequiredforthehighfrequencyclocktostabilise,thestatusoftheHTObitischecked.Theamountoftimerequiredforhighspeedsystemoscillatorstabilizationdependsuponwhichhighspeedsystemoscillatortypeisused.

SLOW1 Mode to NORMAL Mode Switching InSLOW1Modethesystemstilluseshighspeedsystemoscillator.ToswitchbacktotheNORMALMode,wherealsothehighspeedsystemoscillatorisused,theHLCLKbitshouldbesetto“1”.Asthetwomodesbothusethehighspeedsystemoscillator,thereforerequireslesstimeforfullmodeswitching.

Entering the SLEEP ModeThereisonlyonewayforthedevicetoentertheSLEEPModeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTon.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction,buttheWDTwillremainwiththeclocksourcecomingfromthefSUBclock.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandresumecounting.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

Entering the IDLE0 ModeThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinCTRLregisterequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction,buttheTimeBaseclockfTBCandthefSUBclockwillbeon.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandresumecounting.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Entering the IDLE1 ModeThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinCTRLregisterequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockandfSUBwillbeonandtheapplicationprogramwillstopatthe“HALT”instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandresumecounting.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerifthepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbonbedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobe takenwith the loads,whichareconnected to I/Opins,whichare setupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuitsthatdonotdrawcurrent,suchasotherCMOSinputs.IntheIDLE1Modethesystemoscillator ison, if thesystemoscillator is fromthehighspeedsystemoscillator, theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

Wake-upAfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

IfthedeviceiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.Althoughbothofthesewake-upmethodswillinitiatearesetoperation,theactualsourceofthewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe“HALT”instruction.TheTOflagisset ifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.

Programming ConsiderationsThehighspeedandlowspeedoscillatorsbothusethesameSSTcounter.Forexample,ifthesystemiswokenupfromtheSLEEPModeandtheHIRCoscillatorsneedtostart-upfromanoffstate.

• If thedevice iswokenupfromtheSLEEPModetoNORMALMode,and thesystemclocksourceisfromHXToscillatorandFSTENis“1”,thesystemclockcanbeswitchedtotheLIRCorLXToscillatorafterwakeup.

• Thereareperipheralfunctions,suchasTMs,forwhichthefSYSisused.IfthesystemclocksourceisswitchedfromfHto fL, theclocksource to theperipheral functionsmentionedabovewillchangeaccordingly.

Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbythefSUBclock.ThefSUBclockcanbesourcedfromeithertheLIRCorLXToscillatorselectedbyaconfigurationoption.TheLIRCinternaloscillatorhasanapproximatefrequencyof32kHzandthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.TheLXToscillator issuppliedbyanexternal32.768kHzcrystal.TheWatchdogTimersourceclockisthensubdividedbyaratioof28 to218 togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.

Watchdog Timer Control RegisterAsingle register,WDTC,controls the required timeoutperiodaswellas theenableor resetoperation.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

WDTC Register

Bit 7 6 5 4 3 2 1 0�a�e WE4 WE3 WE2 WE1 WE� WS2 WS1 WS�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � 1 � 1 � � 1 1

Bit7~3 WE4 ~ WE0:WDTfunctionsoftwarecontrol10101/01010:WDTenableOthervalues:ResetMCU

Whenthesebitsarechangedtoanyothervaluesbytheenvironmentalnoisetoresetthemicrocontroller, theresetoperationwillbeactivatedafter2~3 tSUBclockcyclesandtheWRFbitintheCTRLregisterwillbesetto1toindicatetheresetsource.

Bit2~0 WS2 ~ WS0:WDTTime-outperiodselection000:28/fSUB

001:210/fSUB

010:212/fSUB

011:214/fSUB100:215/fSUB

101:216/fSUB

110:217/fSUB

111:218/fSUB

Thesethreebitsdeterminethedivisionratioof theWatchdogTimersourececlock,whichinturndeterminesthetimeoutperiod.

CTRL Register

Bit 7 6 5 4 3 2 1 0�a�e FSYSO� — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR � — — — — � � �

Bit7 FSYSON:fSYSControlIDLEModeDescribeelsewhere

Bit6~3 Unimplemented,readas“0”Bit2 LVRF:LVRfunctionresetflag

DescribeelsewhereBit1 LRF:LVRCregistersoftwareresetflag

DescribeelsewhereBit0 WRF:WDTCregistersoftwareresetflag

0:Notoccur1:Occurred

Thisbit isset to1bytheWDTCControlregistersoftwareresetandclearedbytheapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theclearWDTinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.WithregardtotheWatchdogTimerenable/resetfunction,therearefivebits,WE4~WE0,intheWDTCregistertoadditionalenableandresetcontroloftheWatchdogTimer.

WE4 ~ WE0 Bits WDT Function1�1�1B/�1�1�B Ena�leAny othe� value Reset MCU

Watchdog Timer Enable/Reset Control

Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansavalueotherthan01010Band10101BiswrittenintotheWE4~WE0bitlocations,thesecondisusingtheWatchdogTimersoftwareclearinstructionsandthethirdisviaaHALTinstruction.ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle“CLRWDT”instructiontocleartheWDT.

Themaximumtime-outperiodiswhenthe218divisionratioisselected.Asanexample,witha32kHzLIRCoscillatoras itssourceclock, thiswillgiveamaximumwatchdogperiodofaround8secondsforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.

“CLR WDT”Instruction

8-stage Divider WDT Prescaler

WE4~WE0 bitsWDTC Register Reset MCU

LXT fSUB fSUB/28

8-to-1 MUX

CLR

WS2~WS0(fSUB/28 ~ fSUB/218)

WDT Time-out(28/fSUB ~ 218/fSUB)

LIRC

MUX

Configuration option

Watchdog Timer

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Another typeofreset iswhentheWatchdogTimeroverflowsandresets themicrocontroller.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullresetisimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

Reset FunctionsThereareseveralwaysinwhichamicrocontrollerresetcanoccur, througheventsoccurringbothinternallyandexternally:

Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

� � �

� � � � � � � � � � � � � �

� � � � � � � � � � � �

Note:tRSTDispower-ondelay,typicaltime=50msPower-On Reset Timing Chart

Low Voltage Reset – LVRThemicrocontrollercontainsalowvoltageresetcircuit inordertomonitorthesupplyvoltageofthedevice,whichisalwaysenabledselectedbytheconfigurationoption.If thesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedeviceinternallyandtheLVRFbitintheCTRLregisterwillalsobesetto1.ForavalidLVRsignal,alowvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexistforgreater thanthevaluetLVRspecified in theA.C.characteristics. If the lowvoltagestatedoesnotexceedthisvalue,theLVRwillignorethelowsupplyvoltageandwillnotperformaresetfunction.TheactualVLVRcanbeselectedbytheLVS7~LVS0bitsintheLVRCregister.IftheLVS7~LVS0bitsarechangedtosomecertainvaluesbytheenvironmentalnoise,theLVRwillresetthedeviceafter2~3LIRC/LXTclockcycles.Whenthishappens,theLRFbitintheCTRLregisterwillbesetto1.Afterpowerontheregisterwillhavethevalueof01010101B.NotethattheLVRfunctionwillbeautomaticallydisabledwhenthedeviceentersthepowerdownmode.

� � �

� � � � � � � � � � � � � �

� � � � � � � � � � � �

Note:tRSTDispower-ondelay,typicaltime=50msLow Voltage Reset Timing Chart

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

• LVRC Register

Bit 7 6 5 4 3 2 1 0�a�e LVS� LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS�R/W R/W R/W R/W R/W R R R/W R/WPOR � 1 � 1 � 1 � 1

Bit7~0 LVS7 ~ LVS0:LVRVoltageSelectcontrol01010101:2.1V00110011:2.55V10011001:3.15V10101010:3.8VOthervalues:MCUreset–registerisresettoPORvalue

Whenanactuallowvoltageconditionoccurs,asspecifiedbyoneofthefourdefinedLVRvoltagevaluesabove,anMCUresetwillbegenerated.Theresetoperationwillbeactivatedafter2~3LIRC/LXTclockcycles.Inthissituationthisregistercontentswillremainthesameaftersucharesetoccurs.

• CTRL Register

Bit 7 6 5 4 3 2 1 0�a�e FSYSO� — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR � — — — — � � �

Bit7 FSYSON:fSYSControlIDLEModeDescribeelsewhere

Bit6~3 Unimplemented,readas“0”Bit2 LVRF:LVRfunctionresetflag

0:Notoccur1:Occurred

Thisbitissetto1whenaspecificLowVoltageResetsituationconditionoccurs.Thisbitcanonlybeclearedtozerobytheapplicationprogram.

Bit1 LRF:LVRCregistersoftwareresetflag0:Notoccur1:Occurred

Thisbitissetto1iftheLVRCregistercontainsanynondefinedLVRvoltageregistervalues.Thisineffectactslikeasoftwareresetfunction.Thisbitcanonlybeclearedtozerobytheapplicationprogram.

Bit0 WRF:WDTCregistersoftwareresetflagDescribeelsewhere

Watchdog Time-out Reset during Normal OperationTheWatchdogtime-outResetduringnormaloperationisthesameasanLVRresetexceptthattheWatchdogtime-outflagTOwillbesetto“1”.

� � � � � � � � � � � �

� � � � � � � � � � � �

� � � � � � � � � � � � �

Note:tRSTDispower-ondelay,typicaltime=16.7msWDT Time-out Reset during Normal Operation Timing Chart

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Watchdog Time-out Reset during SLEEP or IDLE ModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto“0”andtheTOflagwillbesetto“1”.RefertotheA.C.CharacteristicsfortSSTdetails.

� � � �

� � � � � � � � � � � �

� � � � � � � � � � � � �

Note:ThetSSTis15~16clockcyclesifthesystemclocksourceisprovidedbytheHIRC.ThetSSTis128clockcyclesforHXT/LXT.ThetSSTis1~2clockcyclesfortheLIRC.

WDT Time-out Reset during SLEEP or IDLE Timing Chart

Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF RESET Conditions� � Powe�-on �esetu u LVR �eset du�ing �ORMAL o� SLOW Mode ope�ation1 u WDT ti�e-out �eset du�ing �ORMAL o� SLOW Mode ope�ation1 1 WDT ti�e-out �eset du�ing IDLE o� SLEEP Mode ope�ation

�ote: “u” stands fo� unchangedThefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition After RESETP�og�a� Counte� Reset to ze�oInte��upts All inte��upts will �e disa�ledWDT Clea� afte� �eset� WDT �egins countingTi�e� Modules Ti�e� Modules will �e tu�ned offInput/Output Po�ts I/O po�ts will �e setup as inputs Stack Pointe� Stack Pointe� will point to the top of the stack

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontroller is inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachof themicrocontroller internalregisters.Note thatwheremorethanonepackagetypeexiststhetablewillreflectthesituationforthelargerpackagetype.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Register Reset(Power On)

WDT Time-out(Normal Operation) LVR Reset WDT Time-out

(HALT)IAR� x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uMP� x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uIAR1 x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uMP1L x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uMP1H x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uIAR2 x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uMP2L x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uMP2H x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uACC x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uPCL � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �TBLP x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uTBLH x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uTBHP - - - x x x x x - - - u u u u u - - - u u u u u - - - u u u u uSTATUS x x � � x x x x u u 1 u u u u u u u u u u u u u u u 11 u u u uSMOD � � � � � � 11 � � � � � � 11 � � � � � � 11 u u u u u u u uI�TEG� � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uI�TEG1 - - - - � � � � - - - - � � � � - - - - � � � � - - - - u u u uWDTC � 1 � 1 � � 11 � 1 � 1 � � 11 � 1 � 1 � � 11 u u u u u u u uTBC � � 11 � 111 � � 11 � 111 � � 11 � 111 u u u u u u u uI�TC� - � � � � � � � - � � � � � � � - � � � � � � � - u u u u u u uI�TC1 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uI�TC2 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uI�TC3 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uMFI� - - � � - - � � - - � � - - � � - - � � - - � � - - u u - - u uMFI1 � - � � - - � � � - � � - - � � � - � � - - � � u - u u - - u uMFI2 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uPAWU � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uPAPU � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uPA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPBPU � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u �PB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPBC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPCPU � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uPC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPCC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPDPU - - � � � � � � - - � � � � � � - - � � � � � � - - u u u u u uPD - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u uPDC - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u uIOHR� � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uIOHR1 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uIOHR2 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uIOHR3 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uCTRL � - - - - � � � � - - - - � � � � - - - - � � � u - - - - u u uLVRC � 1 � 1 � 1 � 1 � 1 � 1 � 1 � 1 u u u u u u u u u u u u u u u uADRL(ADRFS=�) x x x x - - - - x x x x - - - - x x x x - - - - u u u u - - - -ADRL(ADRFS=1) x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uADRH(ADRFS=�) x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Register Reset(Power On)

WDT Time-out(Normal Operation) LVR Reset WDT Time-out

(HALT)ADRH(ADRFS=1) - - - - x x x x - - - - x x x x - - - - x x x x - - - - u u u uADCR� � 11 � - � � � � 11 � - � � � � 11 � - � � � u u u u - u u uADCR1 � � - - � � � � � � - - � � � � � � - - � � � � u u - - u u u uACERL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uTMPC� - � - � - � - � - � - � - � - � - � - � - � - � - u - u - u - uEEA - - � � � � � � - - � � � � � � - - � � � � � � - - u u u u u uEED � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uEEC - - - - � � � � - - - - � � � � - - - - � � � � - - - - u u u uCTMC� � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uCTMC1 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uCTMDL � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uCTMDH - - - - - - � � - - - - - - � � - - - - - - � � - - - - - - u uCTMAL � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uCTMAH - - - - - - � � - - - - - - � � - - - - - - � � - - - - - - u uSTMC� � � � � � - - - � � � � � - - - � � � � � - - - u u u u u - - -STMC1 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uSTMDL � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uSTMDH � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uSTMAL � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uSTMAH � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uSTMRP � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uPTM�C� � � � � � - - - � � � � � - - - � � � � � - - - u u u u u - - -PTM�C1 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uPTM�DL � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uPTM�DH - - - - - - � � - - - - - - � � - - - - - - � � - - - - - - u uPTM�AL � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uPTM�AH - - - - - - � � - - - - - - � � - - - - - - � � - - - - - - u uPTM�RPL � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uPTM�RPH - - - - - - � � - - - - - - � � - - - - - - � � - - - - - - u uPTM1C� � � � � � - - - � � � � � - - - � � � � � - - - u u u u u - - -PTM1C1 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uPTM1DL � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uPTM1DH - - - - - - � � - - - - - - � � - - - - - - � � - - - - - - u uPTM1AL � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uPTM1AH - - - - - - � � - - - - - - � � - - - - - - � � - - - - - - u uPTM1RPL � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uPTM1RPH - - - - - - � � - - - - - - � � - - - - - - � � - - - - - - u uSIMTOC � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uSIMC� 111 - � � � � 111 - � � � � 111 - � � � � u u u - u u u uSIMC1 1 � � � � � � 1 1 � � � � � � 1 1 � � � � � � 1 u u u u u u u uSIMD x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uSIMA � � � � � � � - � � � � � � � - � � � � � � � - u u u u u u u uSIMC2 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uLVDC - - � � - � � � - - � � - � � � - - � � - � � � - - u u - u u uUSR � � � � 1 � 11 � � � � 1 � 11 � � � � 1 � 11 u u u u u u u uUCR1 � � � � � � x � � � � � � � x � � � � � � � x � u u u u u u u uUCR2 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uBRG x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Register Reset(Power On)

WDT Time-out(Normal Operation) LVR Reset WDT Time-out

(HALT)TXR/RXR x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uSLCDC� � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uSLCDC1 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uSLCDC2 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uSLCDC3 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u uSLCDC4 � � � � � � � � � � � � � � � � � � � � � � � � u u u u u u u u

Note:"-"notimplement"u"standsfor"unchanged""x"standsfor"unknown"

Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedeviceprovidesbidirectional input/output lines labeledwithportnamesPA~PD.TheseI/OportsaremappedtotheRAMDataMemorywithspecificaddressesasshownintheSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

RegisterName

Bit7 6 5 4 3 2 1 0

PAWU PAWU� PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU�PAPU PAPU� PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU�

PA PA� PA6 PA5 PA4 PA3 PA2 PA1 PA�PAC PAC� PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC�

PBPU PBPU� PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU�PB PB� PB 6 PB 5 PB4 PB3 PB2 PB1 PB�

PBC PBC� PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC�PCPU PCPU� PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU�

PC PC� PC6 PC5 PC4 PC3 PC2 PC1 PC�PCC PCC� PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC�

PDPU — — PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU�PD — — PD5 PD4 PD3 PD2 PD1 PD�

PDC — — PDC5 PDC4 PDC3 PDC2 PDC1 PDC�

I/O Control Register List

PAPUn, PBPUn, PCPUn, PDPUn:I/OPortPull-HighControl0:Disable1:Enable

PAWUn:I/OPortAbit7~bit0WakeUpControl0:Disable1:Enable

PACn, PBCn, PCCn, PDCn:I/OPortInput/OutputControl0:Output1:Input

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregistersPAPU~PDPU,andare implementedusingweakPMOStransistors.

Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

I/O Port Control RegistersEach I/Oporthas itsowncontrol registerknownasPAC~PDC, to control the input/outputconfiguration.With this control register, eachCMOSoutput or input canbe reconfigureddynamicallyundersoftwarecontrol.Eachpinof theI/Oports isdirectlymappedtoabit in itsassociatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa“1”.Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forsomepins,thechosenfunctionofthemulti-functionI/Opinsissetbyconfigurationoptionswhileforothersthefunctionissetbyapplicationprogramcontrol.

I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

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A/D Input/Output Structure

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

I/O Port source current selectionThePA~PDinput/outputportshaveprogrammablesourcecurrentfunctions.Fourlevelsofsourcecurrentcanbeselectedbytheregisters.

IOHR0 Register

Bit 7 6 5 4 3 2 1 0�a�e IOHS31 IOHS3� IOHS21 IOHS2� IOHS11 IOHS1� IOHS�1 IOHS��R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~6 IOHS31~IOHS30:PA3sourcecurrentoutputselectionbit00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

Bit5~4 IOHS21~IOHS20:PA2sourcecurrentoutputselectionbit00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

Bit3~2 IOHS11~IOHS10:PA1sourcecurrentoutputselectionbit00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

Bit1~0 IOHS01~IOHS00:PA0sourcecurrentoutputselectionbit00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

IOHR1 Register

Bit 7 6 5 4 3 2 1 0�a�e IOHS�1 IOHS�� IOHS61 IOHS6� IOHS51 IOHS5� IOHS41 IOHS4�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~6 IOHS71~IOHS70:PA7sourcecurrentoutputselectionbit00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

Bit5~4 IOHS61~IOHS60:PA6sourcecurrentoutputselectionbit00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

Bit3~2 IOHS51~IOHS50:PA5sourcecurrentoutputselectionbit00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Bit1~0 IOHS41~IOHS40:PA4sourcecurrentoutputselectionbit00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

IOHR2 Register

Bit 7 6 5 4 3 2 1 0�a�e IOHSB1 IOHSB� IOHSA1 IOHSA� IOHS�1 IOHS�� IOHS81 IOHS8�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~6 IOHSB1~IOHSB0:PC4~PC7sourcecurrentoutputselectionbit00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

Bit5~4 IOHSA1~IOHSA0:PC0~PC3sourcecurrentoutputselectionbit00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

Bit3~2 IOHS91~IOHS90:PB4~PB7sourcecurrentoutputselectionbit00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

Bit1~0 IOHS81~IOHS80:PB0~PB3sourcecurrentoutputselectionbit00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

IOHR3 Register

Bit 7 6 5 4 3 2 1 0�a�e — — — — IOHSD1 IOHSD� IOHSC1 IOHSC�R/W — — — — R/W R/W R/W R/WPOR — — — — � � � �

Bit7~4 Unimplemented,readas“0”Bit3~2 IOHSD1~IOHSD0:PD4~PD5sourcecurrentoutputselectionbit

00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

Bit1~0 IOHSC1~IOHSC0:PD0~PD3sourcecurrentoutputselectionbit00:Fullsourcecurrentoutput01:10/22fullsourcecurrentoutput10:7/22fullsourcecurrentoutput11:4/22fullsourcecurrentoutput

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Programming ConsiderationsWithintheuserprogram,oneofthefirstthingstoconsiderisportinitialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate, thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregisters,PAC~PDC,arethenprogrammedtosetupsomepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregisters,PA~PD,arefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvaluesintotheappropriateportcontrolregisterorbyprogrammingindividualbits intheportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasure time.To implement timerelatedfunctions thedevice includesseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.EachoftheTMshastwoindividual interrupts.Theadditionof inputandoutputpins foreachTMensures thatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.

ThecommonfeaturesofthedifferentTMtypesaredescribedherewithmoredetailedinformationprovidedintheindividualCompact,StandardandPeriodicTMsections.

IntroductionThedevicecontainsa10-bitCompactTM-CTM,a16-bitStandardTM-STMandtwo10-bitPeriodicTMs-PTM0andPTM1.Althoughsimilar innature, thedifferentTMtypesvaryin theirfeaturecomplexity.ThecommonfeaturestotheCompact,StandardandPeriodicTMswillbedescribedinthissectionandthedetailedoperationwillbedescribedincorrespondingsections.ThemainfeaturesanddifferencesbetweenthethreetypesofTMsaresummarisedintheaccompanyingtable.

Function CTM STM PTMTi�e�/Counte� √ √ √I/P Captu�e — √ √Co�pa�e Match Output √ √ √PWM Channels 1 1 1Single Pulse Output — 1 1PWM Align�ent Edge Edge EdgePWM Adjust�ent Pe�iod & Duty Duty o� Pe�iod Duty o� Pe�iod Duty o� Pe�iod

TM Function Summary

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

TM OperationThethreedifferenttypesofTMsofferadiverserangeoffunctions,fromsimpletimingoperationstoPWMsignalgeneration.ThekeytounderstandinghowtheTMoperatesistoseeitintermsofafreerunningcounterwhosevalueis thencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounter isdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.

TM Clock SourceTheclocksourcewhichdrivesthemaincounterineachTMcanoriginatefromvarioussources.TheselectionoftherequiredclocksourceisimplementedusingthexTnCK2~xTnCK0bitsintheTMcontrolregisters.TheclocksourcecanbearatioofeitherthesystemclockfSYSortheinternalhighclockfH, thefTBCclocksourceortheexternalxTCKnpin.ThexTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.

TM InterruptsTheCompact,StandardandPeriodic typeTMseachhas two internal interrupts, the internalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.WhenaTMinterruptisgenerated,itcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.

TM External PinsEachoftheTMs,irrespectiveofwhattype,hasoneTMinputpin,withthelabelxTCKn.TheTMinputpin,isessentiallyaclocksourcefortheTMandisselectedusingthexTnCK2~xTnCK0bitsinthexTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThisexternalTMinputpinissharedwithotherfunctionsbutwillbeconnectedtotheinternalTMifselectedusingthexTnCK2~xTnCK0bits.TheTMinputpincanbechosentohaveeitherarisingorfallingactiveedge.

TheTMseachhaveoneoutputpin.WhentheTMisintheCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalxTPnoutputpinisalsothepinwheretheTMgeneratesthePWMoutputwaveform.AstheTMoutputpinsarepin-sharedwithotherfunction,theTMoutputfunctionmustfirstbesetupusingregisters.AsinglebitinoneoftheregistersdeterminesifitsassociatedpinistobeusedasanexternalTMoutputpinorifitistohaveanotherfunction.ThenumberofoutputpinsforeachTMtypeisdifferent,thedetailsareprovidedintheaccompanyingtable.

Pin TM Type Input Output

CTM CTM CTCK CTPSTM STM STCK STP

PTMPTM� PTCK� PTP�PTM1 PTCK1 PTP1

TM Input/Output pin

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

TM Input/Output Pin Control RegisterSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunctionisimplementedusingoneregister,withasinglebitintheregistercorrespondingtoaTMinput/outputpin.SettingthebithighwillsetupthecorrespondingpinasaTMinput/output,ifresettozerothepinwillretainitsoriginalotherfunction.

TMPC0 Register

Bit 7 6 5 4 3 2 1 0�a�e — PTP1CP� — PTP�CP� — STPCP� — CTPCP�R/W — R/W — R/W — R/W — R/WPOR — � — � — � — �

Bit7 Unimplemented,readasBit6 PTP1CP0:PTP1pinControl

0:NormalI/O1:PTP1function

Bit5 Unimplemented,readasBit4 PTP0CP0:PTP0pinControl

0:NormalI/O1:PTP0function

Bit3 Unimplemented,readasBit2 STPCP0:STPpinControl

0:NormalI/O1:STPfunction

Bit1 Unimplemented,readasBit0 CTPCP0:CTPpinControl

0:NormalI/O1:CTPfunction

CTM Mode Controller (CTM) CTP

CTPCP0

PB2 data bit

1

0

CTP

CTM Function Pin Control Block Diagram

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

STM Mode Controller (STM)

STP

STPCP0

PB7 data bit

1

0

1

0

STPCP0

0

STP

STP

STM Function Pin Control Block Diagram

PTM Mode Controller (PTM0)

PTP0

PTP0CP0

PB0 data bit

1

0

1

0

PTP0CP0

0

PTP0

PTP0

PTM Mode Controller (PTM1)

PTP1

PTP1CP0

PA5 data bit

1

0

1

0

PTP1CP0

0

PTP1

PTP1

PTM0, PTM1 Function Pin Control Block Diagram

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAorCCRPregister,beingeither10-bitor16-bit,allhavealowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.

AstheCCRAandCCRPregistersareimplementedinthewayshowninthefollowingdiagramandaccessingthisregisteriscarriedoutinaspecificwaydescribedabove,itisrecommendedtousethe“MOV”instructiontoaccesstheCCRAorCCRPlowbyteregister,namedxTMnALorPTMnRPL,in the followingaccessprocedures.Accessing theCCRAorCCRP lowbyte registerwithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.

Data Bus

8-�it Buffe�

xTMnDHxTMnDL

PTMnRPHPTMnRPL

xTMnAHxTMnAL

TM Counte� Registe� (Read only)

xTM CCRA Registe� (Read/W�ite)

PTMn CCRP Registe� (Read/W�ite)

Thefollowingstepsshowthereadandwriteprocedures:

• WritingDatatoCCRAorCCRP♦ Step1.WritedatatoLowBytexTMnALorPTMnRPL

– Notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighBytexTMnAHorPTMnRPH

– Heredataiswrittendirectlytothehighbyteregistersandsimultaneouslydatais latchedfromthe8-bitbuffertotheLowByteregisters.

• ReadingDatafromtheCounterRegistersandCCRAorCCRP♦ Step1.ReaddatafromtheHighBytexTMnDH,xTMnAHorPTMnRPH

– HeredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.

♦ Step2.ReaddatafromtheLowBytexTMnDL,xTMnALorPTMnRPL– Thisstepreadsdatafromthe8-bitbuffer.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Compact Type TM – CTMAlthough thesimplest formof the threeTMtypes, theCompactTMtypestill contains threeoperatingmodes,whichareCompareMatchOutput,Timer/EventCounterandPWMOutputmodes.TheCompactTMcanalsobecontrolledwithanexternalinputpinandcandriveoneexternaloutputpin.

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Compact Type TM Block Diagram

Compact TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealso twointernalcomparatorswith thenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPisthreebitswidewhosevalueiscomparedwiththehighestthreebitsinthecounterwhiletheCCRAisthetenbitsandthereforecompareswithallcounterbits.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theCTONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheCompactTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontroltwooutputpins.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Compact Type TM Register DescriptionOveralloperationofeachCompactTMiscontrolledusingseveralregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10-bitCCRAvalue.TheremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthethreeCCRPbits.

RegisterName

Bit

7 6 5 4 3 2 1 0CTMC� CTPAU CTCK2 CTCK1 CTCK� CTO� CTRP2 CTRP1 CTRP�CTMC1 CTM1 CTM� CTIO1 CTIO� CTOC CTPOL CTDPX CTCCLRCTMDL D� D6 D5 D4 D3 D2 D1 D�CTMDH — — — — — — D� D8CTMAL D� D6 D5 D4 D3 D2 D1 D�CTMAH — — — — — — D� D8

Compact TM Register List

CTMC0 Register

Bit 7 6 5 4 3 2 1 0�a�e CTPAU CTCK2 CTCK1 CTCK� CTO� CTRP2 CTRP1 CTRP�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7 CTPAU:CTMCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 CTCK2 ~ CTCK0:SelectCTMCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fTBC101:fTBC110:CTCKrisingedgeclock111:CTCKfallingedgeclock

These threebitsareusedtoselect theclocksourcefor theCTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 CTON:CTMCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheCTOCbit,whentheCTONbitchangesfromlowtohigh.

Bit2~0 CTRP2~CTRP0:CTMCCRP3-bitregister,comparedwiththeCTMCounterbit9~bit7ComparatorPMatchPeriod000:1024CTMclocks001:128CTMclocks010:256CTMclocks011:384CTMclocks100:512CTMclocks101:640CTMclocks110:768CTMclocks111:896CTMclocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter'shighest threebits.Theresultof thiscomparisoncanbeselectedtocleartheinternalcounterif theCTCCLRbit isset tozero.SettingtheCTCCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

CTMC1 Register

Bit 7 6 5 4 3 2 1 0�a�e CTM1 CTM� CTIO1 CTIO� CTOC CTPOL CTDPX CTCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~6 CTM1~CTM0:SelectCTMOperatingMode00:CompareMatchOutputMode01:CompareMatchOutputMode10:PWMMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetothebits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 CTIO1~CTIO0:SelectCTMoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode00:PWMoutputinactivestate01:PWMoutputactivestate10:PWMoutput11:Undefined

Timer/counterModeUnused

ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

IntheCompareMatchOutputMode,theCTIO1~CTIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.WhentheCTIO1~CTIO0bitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheCTOCbit.NotethattheoutputlevelrequestedbytheCTIO1~CTIO0bitsmustbedifferentfromtheinitialvaluesetupusingtheCTOCbitotherwisenochangewilloccuron theTMoutputpinwhenacomparematchoccurs.After theTMoutputpinchangesstate itcanbereset to its initial levelbychangingtheleveloftheCTONbitfromlowtohigh.In thePWMMode, theCTIO1andCTIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.It isnecessarytochangethevaluesoftheCTIO1andCTIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurif theCTIO1andCTIO0bitsarechangedwhentheTMisrunning.

Bit3 CTOC:CTMOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputMode itdetermines the logic levelof theTMoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesif thePWMsignal isactivehighoractivelow.

Bit2 CTPOL:CTMOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTMoutputpin.Whenthebit issethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 CTDPX:CTMPWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 CTCCLR:SelectCTMCounterclearcondition0:CTMComparatrorPmatch1:CTMComparatrorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theCompactTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear theinternalcounter.WiththeCTCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheCTCCLRbitisnotusedinthePWMMode.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

CTMDL Register

Bit 7 6 5 4 3 2 1 0�a�e D� D6 D5 D4 D3 D2 D1 D�R/W R R R R R R R RPOR � � � � � � � �

Bit7~0 D7~D0:CTMCounterLowByteRegisterbit7~bit0CTM10-bitCounterbit7~bit0

CTMDH Register

Bit 7 6 5 4 3 2 1 0�a�e — — — — — — D� D8R/W — — — — — — R RPOR — — — — — — � �

Bit7~2 Unimplemented,readas“0”Bit1~0 D9~D8:CTMCounterHighByteRegisterbit1~bit0

CTM10-bitCounterbit9~bit8

CTMAL Register

Bit 7 6 5 4 3 2 1 0�a�e D� D6 D5 D4 D3 D2 D1 D�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~0 D7~D0:CTMCCRALowByteRegisterbit7~bit0CTM10-bitCCRAbit7~bit0

CTMAH Register

Bit 7 6 5 4 3 2 1 0�a�e — — — — — — D� D8R/W — — — — — — R/W R/WPOR — — — — — — � �

Bit7~2 Unimplemented,readas“0”Bit1~0 D9~D8:CTMCCRAHighByteRegisterbit1~bit0

CTM10-bitCCRAbit9~bit8

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Compact Type TM Operating ModesTheCompactTypeTMcanoperateinoneofthreeoperatingmodes,CompareMatchOutputMode,PWMOutputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheCTM1andCTM0bitsintheCTMC1register.

Compare Match Output ModeToselect thismode,bitsCTM1andCTM0in theCTMC1register, shouldbeset to00or01respectively. In thismodeonce thecounter isenabledand running itcanbeclearedby threemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheCTCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothCTMAFandCTMPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheCTCCLRbitintheCTMC1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonlytheCTMAFinterruptrequestflagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenCTCCLRishighnoCTMPFinterruptrequestflagwillbegenerated.IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,value,howeverheretheCTMAFinterruptrequestflagwillnotbegenerated.

Asthenameof themodesuggests,afteracomparisonismade, theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaCTMAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheCTMPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.ThewayinwhichtheTMoutputpinchangesstatearedeterminedbytheconditionoftheCTIO1andCTIO0bits intheCTMC1register.TheTMoutputpincanbeselectedusingtheCTIO1andCTIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionoftheTMoutputpin,whichissetupaftertheCTONbitchangesfromlowtohigh,issetupusingtheCTOCbit.NotethatiftheCTIO1andCTIO0bitsarezerothennopinchangewilltakeplace.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

CCRA

CCRP

�x3FF

Counte� ove�flow

CCRA Int.Flag CTMAF

CCRP Int.Flag CTMPF

CCRP > �Counte� clea�ed �y CCRP value

CTM O/P Pin

CTO�

Pause

Counte�Reset

Output Pin set to Initial LevelLow if CTOC = �

Output Togglewith CTMAF flag

He�e CTIO[1:�] = 11Toggle Output Select

�ow CTIO[1:�] = 1� Active High Output Select

Output not affected �yCTMAF flag. Re�ains Highuntil �eset �y CTO� �it

CTCCLR = �; CTM[1:�] = �� / �1

CTPAU

Resu�e

Stop

Ti�e

CCRP > �

CCRP = �

CTPOL

Output PinReset to initial value

Output inve�tswhen CTPOL is high

un-defined

Counte� Value

Compare Match Output Mode – CTCCLR = 0Note:1.WithCTCCLR=0,aComparatorPmatchwillclearthecounter

2.TheTMoutputpincontrolledonlybytheCTMAFflag3.TheoutputpinresettoinitialstatebyaCTONbitrisingedge

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

CCRA

CCRP

�x3FF

CCRP Int.Flag CTMPF

CCRA Int.Flag CTMAF

CCRA > � Counte� clea�ed �y CCRA value

CTM O/P Pin

CTO�

Pause Counte� Reset

Output Pin set to Initial LevelLow if CTOC = �

Output Togglewith CTMAF flag

He�e CTIO[1:�] = 11Toggle Output Select

�ow CTIO[1:�] = 1� Active High Output Select

Output not affected �yCTMAF flag. Re�ains Highuntil �eset �y CTO� �it

CTCCLR= 1; CTM[1:�] = �� / �1

CTPAU

Resu�e

Stop

Ti�e

CCRA = �

CTPOL

Output PinReset to initial value

Output inve�tswhen CTPOL is high

Counte� Value

Output doesnot change

�o CTMAF flaggene�ated on

CCRA ove�flow

CCRA = �Counte� ove�flow

CTMPF notgene�ated

un-defined

Compare Match Output Mode – CTCCLR = 1Note:1.WithCTCCLR=1,aComparatorAmatchwillclearthecounter

2.TheTMoutputpincontrolledonlybytheCTMAFflag3.TheoutputpinresettoinitialstatebyaCTONrisingedge4.TheCTMPFflagsisnotgeneratedwhenCTCCLR=1

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Timer/Counter ModeToselectthismode,bitsCTM1andCTM0intheCTMC1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsCTM1andCTM0intheCTMC1registershouldbesetto10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.Byprovidingasignalof fixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.In thePWMmode, theCTCCLRbithasnoeffectas thePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.WhichregisterisusedtocontroleitherfrequencyordutycycleisdeterminedusingtheCTDPXbitintheCTMC1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheCTOCbitIntheCTMC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoCTIO1andCTIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheCTPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

• CTM, PWM Mode, Edge-aligned Mode, CTDPX=0

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod 128 256 384 512 64� �68 8�6 1�24Duty CCRA

IffSYS=16MHz,TMclocksourceisfSYS/4,CCRP=100b,CCRA=128,

TheCTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

• CTM, PWM Mode, Edge-aligned Mode, CTDPX=1

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod CCRADuty 128 256 384 512 64� �68 8�6 1�24

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

CCRP

CCRA

CounterValue Counter Cleared by CCRP

CCRA Int.Flag CTMAF

CCRP Int.Flag CTMPF

CTM O/P Pin(CTOC=1)

CTON

PWM Duty Cycleset by CCRA

PWM Periodset by CCRP

Counter stop if CTON bit low

Counter reset when CTON returns high

PWM resumes operation

Time

CTDPX=0;CTM[1:0]=10

CTPOL

Output InvertsWhen CTPOL = 1

CTPAU

ResumePause

CTM O/P Pin(CTOC=0)

un-defined

PWM Mode – CTDPX = 0 Note:1.HereCTDPX=0-CounterclearedbyCCRP

2.AcounterclearsetsPWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenCTIO[1:0]=00or014.TheCTCCLRbithasnoinfluenceonPWMoperation

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

CCRA

CCRP

Counte�Value Counte� Clea�ed �y CCRA

CCRP Int.Flag CTMPF

CCRA Int.Flag CTMAF

CTM O/P Pin(CTOC=1)

CTO�

PWM Duty Cycleset �y CCRP

PWM Pe�iodset �y CCRA

Counte� stop if CTO� �it low

Counte� �eset when CTO� �etu�ns high

PWM �esu�es ope�ation

Ti�e

CTDPX=1;CTM[1:�]=1�

CTPOL

Output Inve�tsWhen CTPOL = 1

CTPAU

Resu�ePause

CTM O/P Pin(CTOC=�)

un-defined

PWM Mode – CTDPX = 1Note:1.HereCTDPX=1-CounterclearedbyCCRA

2.AcounterclearsetsPWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenCTIO[1:0]=00or014.TheCTCCLRbithasnoinfluenceonPWMoperation

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Rev. 1.21 �4 �ove��e� ��� 2�1� Rev. 1.21 �5 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Standard Type TM – STMTheStandardTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheStandardTMcandriveoneexternaloutputpin.

� � � �

� � � �

� � � � � �

� � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � �

� � � � � � � � � �

� � � � � � �

� � � � � �

� � � � � � � � � � � � � � � � � �

� � � � � �� � � � � � � � � � � �

� � � � � � � � � � � � �� � � � � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � �

� � � � � � � � � � � � � � �

� � � � � � �

  ­ � �� � � � � � � �

� � � � � � � � � �

� � � � � � � � � �� � � � � � � � � �

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� � �

� � � � � � � �� � � � � � �

� � � � �� � � � � � �

� � �

� � � � � � �

� � �� � �� � �� � �� � �� � �� � �

� � � � � �� � � �� � � � �� � � � �� � � �� � � �

��

� � � � � � �� � � � � � � � � � �

Standard Type TM Block Diagram

Standard TM OperationAtitscoreisa16-bitcount-upcounterwhichisdrivenbyauserselectableinternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPis8-bitwidewhosevalueiscomparedwiththehighest8bitsinthecounterwhiletheCCRAis16bitsandthereforecompareswithallcounterbits.

Theonlywayofchanging thevalueof the16-bitcounterusing theapplicationprogram, is toclear thecounterbychangingtheSTONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheStandardTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

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Rev. 1.21 �6 �ove��e� ��� 2�1� Rev. 1.21 �� �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Standard Type TM Register DescriptionOveralloperationof theStandardTMiscontrolledusingseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter16-bitvalue,whilearead/writeregisterpairexiststostoretheinternal16-bitCCRAvalue.TheremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellaseightCCRPbits.

RegisterName

Bit

7 6 5 4 3 2 1 0STMC� STPAU STCK2 STCK1 STCK� STO� — — —STMC1 STM1 STM� STIO1 STIO� STOC STPOL STDPX STCCLRSTMDL D� D6 D5 D4 D3 D2 D1 D�STMDH D15 D14 D13 D12 D11 D1� D� D8STMAL D� D6 D5 D4 D3 D2 D1 D�STMAH D15 D14 D13 D12 D11 D1� D� D8STMRP D� D6 D5 D4 D3 D2 D1 D�

16-bit Standard TM Register List

STMC0 Register

Bit 7 6 5 4 3 2 1 0�a�e STPAU STCK2 STCK1 STCK� STO� — — —R/W R/W R/W R/W R/W R/W — — —POR � � � � � — — —

Bit7 STPAU:STMCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 STCK2 ~ STCK0:SelectSTMCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fTBC101:fTBC110:STCKrisingedgeclock111:STCKfallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 STON:STMCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheSTOCbit,whentheSTONbitchangesfromlowtohigh.

Bit2~0 Unimplemented,readas“0”

STMC1 Register

Bit 7 6 5 4 3 2 1 0�a�e STM1 STM� STIO1 STIO� STOC STPOL STDPX STCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~6 STM1~STM0:SelectSTMOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetothebits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 STIO1~STIO0:SelectSTMoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMoutputinactivestate01:PWMoutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofSTP01:InputcaptureatfallingedgeofSTP10:Inputcaptureatfalling/risingedgeofSTP11:Inputcapturedisabled

Timer/counterModeUnused

ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.IntheCompareMatchOutputMode,theSTIO1~STIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.WhentheSTIO1~STIO0bitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheSTOCbit.NotethattheoutputlevelrequestedbytheSTIO1~STIO0bitsmustbedifferentfromtheinitialvaluesetupusingtheSTOCbitotherwisenochangewilloccuron theTMoutputpinwhenacomparematchoccurs.After theTMoutputpinchangesstate itcanbereset to its initial levelbychangingtheleveloftheSTONbitfromlowtohigh.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

In thePWMMode, theSTIO1andSTIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.It isnecessarytochangethevaluesoftheSTIO1andSTIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurif theSTIO1andSTIO0bitsarechangedwhentheTMisrunning.

Bit3 STOC:STMOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode/SinglePulseOutputMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogicleveloftheTMoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesifthePWMsignalisactivehighoractivelow.

Bit2 STPOL:STMOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTMoutputpin.Whenthebit issethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 STDPX:STMPWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 STCCLR:SelectSTMCounterclearcondition0:TMComparatorPmatch1:TMComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theStandardTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear theinternalcounter.With theSTCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheSTCCLRbitisnotusedinthePWM,SinglePulseorInputCaptureMode.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

STMDL Register

Bit 7 6 5 4 3 2 1 0�a�e D� D6 D5 D4 D3 D2 D1 D�R/W R R R R R R R RPOR � � � � � � � �

Bit7~0 D7~D0:STMCounterLowByteRegisterbit7~bit0STM16-bitCounterbit7~bit0

STMDH Register

Bit 7 6 5 4 3 2 1 0�a�e D15 D14 D13 D12 D11 D1� D� D8R/W R R R R R R R RPOR � � � � � � � �

Bit7~0 D15~D8:STMCounterHighByteRegisterbit7~bit0STM16-bitCounterbit15~bit8

STMAL Register

Bit 7 6 5 4 3 2 1 0�a�e D� D6 D5 D4 D3 D2 D1 D�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~0 D7~D0:STMCCRALowByteRegisterbit7~bit0STM16-bitCCRAbit7~bit0

STMAH Register

Bit 7 6 5 4 3 2 1 0�a�e D15 D14 D13 D12 D11 D1� D� D8R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~0 D15~D8:STMCCRAHighByteRegisterbit7~bit0STM16-bitCCRAbit15~bit8

STMRP Register

Bit 7 6 5 4 3 2 1 0�a�e D� D6 D5 D4 D3 D2 D1 D�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~0 STMRP:STMCCRPHighByteRegisterbit7~bit0STMCCRP8-bitregister,comparedwiththeSTMCounterbit15~bit8.ComparatorPMatchPeriod0:65536STMclocks1~255:256×(1~255)STMclocks

TheseeightbitsareusedtosetupthevalueontheinternalCCRP8-bitregister,whichare thencomparedwith the internalcounter'shighesteightbits.Theresultof thiscomparisoncanbeselectedtocleartheinternalcounterif theSTCCLRbit isset tozero.SettingtheSTCCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighesteightcounterbits, thecomparevaluesexist in256clockcyclemultiples.Clearingalleightbits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Standard Type TM Operating ModesTheStandardTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheSTM1andSTM0bitsintheSTMC1register.

Compare Match Output ModeToselectthismode,bitsSTM1andSTM0intheSTMC1register,shouldbesetto00respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheSTCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothSTMAFandSTMPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheSTCCLRbitintheSTMC1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonlytheSTMAFinterruptrequestflagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenSTCCLRishighnoSTMPFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto“0”.

Asthenameofthemodesuggests,afteracomparisonismade,theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaSTMAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheSTMPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.Thewayinwhich theTMoutputpinchangesstatearedeterminedby theconditionof theSTIO1andSTIO0bitsintheSTMC1register.TheTMoutputpincanbeselectedusingtheSTIO1andSTIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,which issetupafter theSTONbitchangesfromlowtohigh,issetupusingtheSTOCbit.NotethatiftheSTIO1andSTIO0bitsarezerothennopinchangewilltakeplace.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

CCRA

CCRP

�xFFFF

Counte� ove�flow

CCRA Int.Flag STMAF

CCRP Int.Flag STMPF

CCRP > �Counte� clea�ed �y CCRP value

STM O/P Pin

STO�

Pause

Counte�Reset

Output Pin set to Initial LevelLow if STOC = �

Output Togglewith STMAF flag

He�e STIO[1:�] = 11Toggle Output Select

�ow STIO[1:�] = 1� Active High Output Select

Output not affected �ySTMAF flag. Re�ains Highuntil �eset �y STO� �it

STCCLR = �; STM[1:�] = ��

STPAU

Resu�e

Stop

Ti�e

CCRP > �

CCRP = �

STPOL

Output PinReset to initial value

Output inve�tswhen STPOL is high

Output cont�olled�y othe� pin - sha�ed function

Counte� Value

Compare Match Output Mode – STCCLR = 0Note:1.WithSTCCLR=0aComparatorPmatchwillclearthecounter

2.TheTMoutputpincontrolledonlybytheSTMAFflag3.TheoutputpinresettoinitialstatebyaSTONbitrisingedge

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

CCRA

CCRP

�xFFFF

CCRA Int.Flag STMPF

CCRP Int.Flag STMAF

CCRA > � Counte� clea�ed �y CCRA value

STM O/P Pin

STO�

Pause Counte� Reset

Output Pin set to Initial LevelLow if STOC = �

Output Togglewith STMAF flag

He�e STIO[1:�] = 11Toggle Output Select

�ow STIO[1:�] = 1� Active High Output Select

Output not affected �ySTMAF flag. Re�ains Highuntil �eset �y STO� �it

STCCLR = 1; STM[1:�] = ��

STPAU

Resu�e

Stop

Ti�e

CCRA = �

STPOL

Output PinReset to initial value

Output inve�tswhen STPOL is high

Output cont�olled�y othe� pin -sha�ed function

Counte� Value

Output doesnot change

�o STMAF flaggene�ated on

CCRA ove�flow

CCRA = �Counte� ove�flow

STMPF notgene�ated

Compare Match Output Mode – STCCLR = 1Note:1.WithSTCCLR=1aComparatorAmatchwillclearthecounter

2.TheTMoutputpincontrolledonlybytheSTMAFflag3.TheoutputpinresettoinitialstatebyaSTONrisingedge4.TheSTMPFflagsisnotgeneratedwhenSTCCLR=1

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Timer/Counter ModeToselectthismode,bitsSTM1andSTM0intheSTMC1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsSTM1andSTM0intheSTMC1registershouldbesetto10respectivelyandalso theSTIO1andSTIO0bitsshouldbeset to10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.In thePWMmode, theSTCCLRbithasnoeffectas thePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.WhichregisterisusedtocontroleitherfrequencyordutycycleisdeterminedusingtheSTDPXbitintheSTMC1register.

ThePWMwaveformfrequencyanddutycyclecan thereforebecontrolledby thevalues in theCCRAandCCRPregisters.An interrupt flag,one foreachof theCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheSTOCbitIntheSTMC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoSTIO1andSTIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheSTPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

• 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=0

CCRP 1~255 0Pe�iod CCRP×256 65536Duty CCRA

IffSYS=16MHz,TMclocksourceisfSYS/4,CCRP=2andCCRA=128,

TheSTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

• 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=1

CCRP 1~255 0Pe�iod CCRADuty CCRP×256 65536

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbythe(CCRP×256)exceptwhentheCCRPvalueisequalto0.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

CCRP

CCRA

CounterValue Counter Cleared by CCRP

CCRA Int.Flag STMAF

CCRP Int.Flag STMPF

STM O/P Pin(STOC=1)

STON

PWM Duty Cycleset by CCRA

PWM Periodset by CCRP

Counter Stop If STON bit low

Counter reset when STON returns high

PWM resumes operationOutput controlled by

Other pin-shared function

Time

STDPX=0;STM[1:0]=10

STPOL

Output InvertsWhen STPOL = 1

STPAU

ResumePause

STM O/P Pin(STOC=0)

PWM Mode – STDPX=0Note:1.HereSTDPX=0-CounterclearedbyCCRP

2.AcounterclearsetsPWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenSTIO[1:0]=00or014.TheSTCCLRbithasnoinfluenceonPWMoperation

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

CCRA

CCRP

CounterValue Counter Clearedby CCRA

CCRP Int.Flag STMPF

CCRA Int.Flag STMAF

STM O/P Pin(STOC=1)

STON

PWM Duty Cycleset by CCRP

PWM Periodset by CCRA

Counter Stop If STON bit low

Counter reset when STON returns high

PWM resumes operationOutput controlled by

Other pin-shared function

Time

STDPX=1;STM[1:0]=10

STPOL

Output InvertsWhen STPOL = 1

STPAU

ResumePause

STM O/P Pin(STOC=0)

PWM Mode – STDPX=1Note:1.HereSTDPX=1-CounterclearedbyCCRA

2.AcounterclearsetsPWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenSTIO[1:0]=00or014.TheSTCCLRbithasnoinfluenceonPWMoperation

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Single Pulse ModeToselectthismode,bitsSTM1andSTM0intheSTMC1registershouldbesetto10respectivelyandalsotheSTIO1andSTIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionoftheSTONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,theSTONbitcanalsobemadetoautomaticallychangefromlowtohighusingtheexternalSTCKpin,whichwillinturninitiatetheSinglePulseoutput.

WhentheSTONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheSTONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheSTONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

� � � � � � � � � � � �

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� �� � � � � � � � � � � � � � � � � �

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� � � � � � � � � � � � � �

Single Pulse Generation

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Counte� Value

CCRP

CCRA

STO�

STPAU

STPOL

CCRP Int. Flag STMPF

CCRA Int. Flag STMAF

STM O/P Pin(STOC=1)

Ti�e

Counte� stopped �y CCRA

PauseResu�e Counte� Stops

�y softwa�e

Counte� Reset when STO� �etu�ns high

STM [1:�] = 1� ; STIO [1:�] = 11

Pulse Width set �y CCRA

Output Inve�tswhen STPOL = 1

�o CCRP Inte��upts gene�ated

STM O/P Pin(STOC=�)

STCK pin

Softwa�e T�igge�

Clea�ed �y CCRA �atch

STCK pin T�igge�

Auto. set �y STCK pin

Softwa�e T�igge�

Softwa�e Clea�

Softwa�e T�igge�Softwa�e

T�igge�

Single Pulse Mode Note:1.CounterstoppedbyCCRAmatch

2.CCRPisnotused3.ThepulseistriggeredbysettingtheSTONbithighorSTCKpin4.IntheSinglePulseMode,STIO[1:0]mustbesetto“11”andcannotbechanged.

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Rev. 1.21 88 �ove��e� ��� 2�1� Rev. 1.21 8� �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheSTONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaTMinterrupt.Thecountercanonlyberesetback tozerowhen theSTONbitchangesfromlowtohighwhen thecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheSTCCLRandSTDPXbitsarenotusedinthisMode.

Capture Input ModeToselectthismodebitsSTM1andSTM0intheSTMC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheSTPpin,whoseactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges; theactiveedgetransitiontypeisselectedusingtheSTIO1andSTIO0bits intheSTMC1register.ThecounterisstartedwhentheSTONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.

WhentherequirededgetransitionappearsontheSTPpinthepresentvalueinthecounterwillbelatchedintotheCCRAregistersandaTMinterruptgenerated.IrrespectiveofwhateventsoccurontheSTPpinthecounterwillcontinuetofreerununtiltheSTONbitchangesfromhightolow.WhenaCCRPcomparematchoccurs thecounterwill resetbacktozero; in thiswaytheCCRPvaluecanbeused tocontrol themaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheSTIO1andSTIO0bitscanselecttheactivetriggeredgeontheSTPpintobearisingedge,fallingedgeorbothedgetypes.IftheSTIO1andSTIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheSTPpin,howeveritmustbenotedthatthecounterwillcontinuetorun.

AstheSTPpin ispinsharedwithotherfunctions,caremustbe taken if theTMis in theInputCaptureMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.TheSTCCLRandSTDPXbitsarenotusedinthisMode.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Counte� Value

YY

CCRP

STO�

STPAU

CCRP Int. Flag STMPF

CCRA Int. Flag STMAF

CCRA Value

Ti�e

Counte� clea�ed �y CCRP

PauseResu�e

Counte� Reset

STM [1:0] = 01

STM captu�e pin STP

XX

Counte� Stop

STIO [1:�] Value

XX YY XX YY

Active edge Active

edgeActive edge

�� – Rising edge �1 – Falling edge 1� – Both edges 11 – Disa�le Captu�e

Capture Input Mode Note:1.STM[1:0]=01andactiveedgesetbytheSTIO[1:0]bits

2.ATMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.TheSTCCLRbitisnotused4.Nooutputfunction-STOCandSTPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Periodic Type TM – PTM0, PTM1ThePTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheP-typeTMcanalsobecontrolledwithanexternalinputpinandcandriveoneoutputpins.

Periodic TM OperationThereare twoP-typeTMs,bothare10-bitwide.At thecore isa10count-upcounterwhich isdrivenbyauserselectableinternalorexternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPcomparatoris10-bitswide.

Theonlywayofchangingthevalueofthe10counterusingtheapplicationprogram,istoclearthecounterbychangingthePTnONbitfromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.When theseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.ThePeriodicTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

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� � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � �

� � � � � � � � �

� � � � �

� � � � � � � � � � � � � � � � � � � �

� � � � � � �� � � � � � � � � � � �

� � � � � � � � � � � � �� � � � � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � �

� � � � � � � �� � � � � � � � � � �

� � � � �

� �   �­ � � � � � � �

� � � � � � � � � � � �

� � � � � � � � � � � �� � � � � � � � � � � �

� � � � �

� � � �

� � � � � � � �� � � � � � �

� � � � �� � � � � � �

� � � �

� � � � � � � �

� � �� � �� � �� � �� � �� � �� � �

� � � � � �� � � �� � � � �� � � � �� � � �� � � �

��

��

� � � � � �

Periodic Type TM Block Diagram (n=0, 1)

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Rev. 1.21 �� �ove��e� ��� 2�1� Rev. 1.21 �1 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

PTM register descriptionOveralloperationoftheP-typeTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whiletworead/writeregisterpairsexisttostoretheinternal10-bitCCRA/CCRPvalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.

RegisterName

Bit

7 6 5 4 3 2 1 0PTMnC� PTnPAU PTnCK2 PTnCK1 PTnCK� PTnO� — — —PTMnC1 PTnM1 PTnM� PTnIO1 PTnIO� PTnOC PTnPOL PTnCKS PTnCCLRPTMnDL D� D6 D5 D4 D3 D2 D1 D�PTMnDH — — — — — — D� D8PTMnAL D� D6 D5 D4 D3 D2 D1 D�PTMnAH — — — — — — D� D8PTMnRPL D� D6 D5 D4 D3 D2 D1 D�PTMnRPH — — — — — — D� D8

10-bit Periodic TM Register List (n=0, 1)

PTMnC0 Register

Bit 7 6 5 4 3 2 1 0�a�e PTnPAU PTnCK2 PTnCK1 PTnCK� PTnO� — — —R/W R/W R/W R/W R/W R/W — — —POR � � � � � — — —

Bit7 PTnPAU:PTMnCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 PTnCK2 ~ PTnCK0:SelectPTMnCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fTBC101:fTBC110:PTCKnrisingedgeclock111:PTCKnfallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

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Rev. 1.21 �2 �ove��e� ��� 2�1� Rev. 1.21 �3 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Bit3 PTnON:PTMnCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbythePTnOCbit,whenthePTnONbitchangesfromlowtohigh.

Bit2~0 Unimplemented,readas“0”

PTMnC1 Register

Bit 7 6 5 4 3 2 1 0�a�e PTnM1 PTnM� PTnIO1 PTnIO� PTnOC PTnPOL PTnCKS PTnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~6 PTnM1~PTnM0:SelectPTMnOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremade to thePTnM1andPTnM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 PTnIO1~PTnIO0:SelectPTPnoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:Forceinactivestate01:Forceactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofPTPnorPTCKn01:InputcaptureatfallingedgeofPTPnorPTCKn10:Inputcaptureatfalling/risingedgeofPTPnorPTCKn11:Inputcapturedisabled

Timer/counterModeUnused

These twobitsareused todeterminehowtheTMoutputpinchangesstatewhenacertaincondition is reached.Thefunction that thesebitsselectdependsupon inwhichmodetheTMisrunning.IntheCompareMatchOutputMode,thePTnIO1andPTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.Theinitialvalueof theTMoutputpinshouldbesetupusing thePTnOCbit in thePTMnC1register.NotethattheoutputlevelrequestedbythePTnIO1andPTnIO0bitsmustbe

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Rev. 1.21 �2 �ove��e� ��� 2�1� Rev. 1.21 �3 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

differentfromtheinitialvaluesetupusingthePTnOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstateitcanberesettoitsinitiallevelbychangingthelevelofthePTnONbitfromlowtohigh.

Bit3 PTnOC:PTPnOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode/SinglePulseOutputMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogicleveloftheTMoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesifthePWMsignalisactivehighoractivelow.

Bit2 PTnPOL:PTPnOutputpolaritycontrol0:Non-invert1:Invert

ThisbitcontrolsthepolarityofthePTPnoutputpin.WhenthebitissethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 PTnCKS:InputCapturetriggersourceselection0:ExternalClocksourceofCaptureInputModecomesfromPTPn1:ExternalClocksourceofCaptureInputModecomesfromPTCKn

Bit0 PTnCCLR:SelectPTMnCounterclearcondition0:PTMnComparatorPmatch1:PTMnComparatorAmatch

Thisbitisusedtoselectthemethodwhichclearsthecounter.RememberthattheP-typeTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtocleartheinternalcounter.WiththePTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwitha counteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.ThePTnCCLRbitisnotusedinthePWM,SinglePulseorInputCaptureMode.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

PTMnDL Register

Bit 7 6 5 4 3 2 1 0�a�e D� D6 D5 D4 D3 D2 D1 D�R/W R R R R R R R RPOR � � � � � � � �

Bit7~0 D7~D0:PTMnCounterLowByteRegisterBit7~Bit0PTMn10-bitCounterbit7~bit0

PTMnDH Register

Bit 7 6 5 4 3 2 1 0�a�e — — — — — — D� D8R/W — — — — — — R RPOR — — — — — — � �

Bit7~2 Unimplemented,readas“0”Bit1~0 D9~D8:PTMnCounterHighByteRegisterBit1~Bit0

PTMn10-bitCounterbit9~bit8

PTMnAL Register

Bit 7 6 5 4 3 2 1 0�a�e D� D6 D5 D4 D3 D2 D1 D�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~0 D7~D0:PTMnCCRALowByteRegisterbit7~bit0PTMn10-bitCCRAbit7~bit0

PTMnAH Register

Bit 7 6 5 4 3 2 1 0�a�e — — — — — — D� D8R/W — — — — — — R/W R/WPOR — — — — — — � �

Bit7~2 Unimplemented,readas“0”Bit1~0 D9~D8:PTMnCCRAHighByteRegisterBit1~Bit0

PTMn10-bitCCRAbit9~bit8

PTMnRPL Register (n=0, 1)

Bit 7 6 5 4 3 2 1 0�a�e D� D6 D5 D4 D3 D2 D1 D�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~0 D7~D0:PTMnCCRPRegisterbit7~bit0PTMn10-bitCCRPbit7~bit0

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

PTMnRPH Register

Bit 7 6 5 4 3 2 1 0�a�e — — — — — — D� D8R/W — — — — — — R/W R/WPOR — — — — — — � �

Bit7~2 Unimplemented,readas“0”Bit1~0 D9~D8:PTMnCCRPRegisterbit1~bit0

PTMn10-bitCCRPbit9~bit8

Periodic Type TM Operating ModesTheP-typeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,Capture InputModeorTimer/CounterMode.TheoperatingmodeisselectedusingthePTnM1andPTnM0bitsinthePTMnC1register.

Compare Output ModeTo select thismode, bitsPTnM1andPTnM0 in thePTMnC1 register, shouldbe set to00respectively. In thismodeonce thecounter isenabledand running itcanbeclearedby threemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhenthePTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothPTMnAFandPTMnPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IfthePTnCCLRbitinthePTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonly thePTMnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenPTnCCLRishighnoPTMnPFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto“0”.

Asthenameof themodesuggests,afteracomparisonismade, theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaPTMnAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.ThePTMnPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.ThewayinwhichtheTMoutputpinchangesstatearedeterminedbytheconditionofthePTnIO1andPTnIO0bits in thePTMnC1register.TheTMoutputpincanbeselectedusingthePTnIO1andPTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,whichissetupafterthePTnONbitchangesfromlowtohigh,issetupusingthePTnOCbit.NotethatifthePTnIO1andPTnIO0bitsarezerothennopinchangewilltakeplace.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Counte� Value

�x3FF

CCRP

CCRA

PTnO�

PTnPAU

PTnPOL

CCRP Int. Flag PTMnPF

CCRA Int. Flag PTMnAF

PTM O/P Pin

Ti�e

CCRP=�

CCRP > �

Counte� ove�flowCCRP > �Counte� clea�ed �y CCRP value

Pause

Resu�e

Stop

Counte� Resta�t

PTnCCLR = �; PTnM [1:�] = ��

Output pin set to initial Level Low if PTnOC=�

Output Toggle with PTMnAF flag

�ote PTnIO [1:�] = 1� Active High Output selectHe�e PTnIO [1:�] = 11

Toggle Output select

Output not affected �y PTMnAF flag. Re�ains High until �eset �y PTnO� �it

Output PinReset to Initial value

Output Inve�tswhen PTnPOL is high

un-defined

Compare Match Output Mode – PTnCCLR=0 (n=0, 1)Note:1.WithPTnCCLR=0aComparatorPmatchwillclearthecounter

2.TheTMoutputpiniscontrolledonlybythePTMnAFflag3.TheoutputpinisresettoitsinitialstatebyaPTnONbitrisingedge

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Rev. 1.21 �6 �ove��e� ��� 2�1� Rev. 1.21 �� �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Counte� Value

�x3FF

CCRP

CCRA

PTnO�

PTnPAU

PTnPOL

CCRP Int. Flag PTMnPF

CCRA Int. Flag PTMnAF

PTM O/P Pin

Ti�e

CCRA=�

CCRA = �Counte� ove�flowCCRA > � Counte� clea�ed �y CCRA value

Pause

Resu�e

Stop Counte� Resta�t

PTnCCLR = 1; PTnM [1:�] = ��

Output pin set to initial Level Low if PTnOC=�

Output Toggle with PTMnAF flag

�ote PTnIO [1:�] = 1� Active High Output selectHe�e PTnIO [1:�] = 11

Toggle Output select

Output not affected �y PTMnAF flag. Re�ains High until �eset �y PTnO� �it

Output PinReset to Initial value

Output cont�olled �y othe� pin-sha�ed function

Output Inve�tswhen PTnPOL is high

PTMPF not gene�ated

�o PTMnAF flag gene�ated on CCRA ove�flow

Output does not change

Compare Match Output Mode – PTnCCLR=1 (n=0, 1)Note:1.WithPTnCCLR=1aComparatorAmatchwillclearthecounter

2.TheTMoutputpiniscontrolledonlybythePTMnAFflag3.TheoutputpinisresettoitsinitialstatebyaPTnONbitrisingedge4.APTMnPFflagisnotgeneratedwhenPTnCCLR=1

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Timer/Counter ModeTo select thismode, bitsPTnM1andPTnM0 in thePTMnC1 register shouldbe set to 11respectively.TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputModegenerating thesameinterruptflags.Theexception is that in theTimer/CounterModetheTMoutputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsPTnM1andPTnM0inthePTMnC1registershouldbesetto10respectivelyandalsothePTnIO1andPTnIO0bitsshouldbesetto10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMmode,thePTnCCLRbithasnoeffectasthePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.ThePTnOCbitinthePTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoPTnIO1andPTnIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.ThePTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

• 10-bit PWM Mode, Edge-aligned Mode

CCRP 0 1~1023Pe�iod 1�24 1~1�23Duty CCRA

IffSYS=16MHz,TMclocksourceselectfSYS/4,CCRP=512andCCRA=128,

ThePTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Counte� Value

CCRP

CCRA

PTnO�

PTnPAU

PTnPOL

CCRP Int. Flag PTMnPF

CCRA Int. Flag PTMnAF

PTM O/P Pin(PTnOC=1)

Ti�e

Counte� clea�ed �y CCRP

Pause Resu�e Counte� Stop if PTnO� �it low

Counte� Reset when PTnO� �etu�ns high

PTnM [1:�] = 1� ; PTnIO [1:�]=1�

PWM Duty Cycle set �y CCRA

PWM �esu�es ope�ation

Output cont�olled �y othe� pin-sha�ed function Output Inve�ts

When PTnPOL = 1PWM Pe�iod set �y CCRP

PTM O/P Pin(PTnOC=�)

PWM mode (n=0, 1)Note:1.AcounterclearsetsthePWMPeriod

2.TheinternalPWMfunctioncontinuesrunningevenwhenPTnIO[1:0]=00or013.ThePTnCCLRbithasnoinfluenceonPWMoperation

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Rev. 1.21 1�� �ove��e� ��� 2�1� Rev. 1.21 1�1 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Single Pulse ModeTo select thismode, bitsPTnM1andPTnM0 in thePTMnC1 register shouldbe set to 10respectivelyandalsothePTnIO1andPTnIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionofthePTnONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,thePTnONbitcanalsobemade toautomaticallychangefromlowtohighusing theexternalPTCKnpin,whichwillinturninitiatetheSinglePulseoutput.WhenthePTnONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.ThePTnONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhenthePTnONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

HoweveracomparematchfromComparatorAwillalsoautomaticallyclearthePTnONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaTMinterrupt.ThecountercanonlyberesetbacktozerowhenthePTnONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.ThePTnCCLRbitisnotusedinthisMode.

� � � � � � � � � � � �

� � � � � � � � �� � � � �

� � � � � � �� � � � � � � � � � �

�� � � � � � � � � � � � � � � � � �

� � � � � � � � �� � � � �

� � � � � � �� � � � � � � � � � � �� � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � �

� � � � � � � � � � � � � � �

Single Pulse Generation (n=0, 1)

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Rev. 1.21 1�� �ove��e� ��� 2�1� Rev. 1.21 1�1 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Counte� Value

CCRP

CCRA

PTnO�

PTnPAU

PTnPOL

CCRP Int. Flag PTMnPF

CCRA Int. Flag PTMnAF

PTM O/P Pin(PTnOC=1)

Ti�e

Counte� stopped �y CCRA

PauseResu�e Counte� Stops

�y softwa�e

Counte� Reset when PTnO� �etu�ns high

PTnM [1:�] = 1� ; PTnIO [1:�] = 11

Pulse Width set �y CCRA

Output Inve�tswhen PTnPOL = 1

�o CCRP Inte��upts gene�ated

PTM O/P Pin(PTnOC=�)

PTCKn pin

Softwa�e T�igge�

Clea�ed �y CCRA �atch

PTCKn pin T�igge�

Auto. set �y PTCKn pin

Softwa�e T�igge�

Softwa�e Clea�

Softwa�e T�igge�Softwa�e

T�igge�

Single Pulse Mode (n=0, 1)Note:1.CounterstoppedbyCCRA

2.CCRPisnotused3.ThepulseistriggeredbythePTCKnpinorbysettingthePTnONbithigh4.APTCKnpinactiveedgewillautomaticallysetthePTnONbithight5.IntheSinglePulseMode,PTnIO[1:0]mustbesetto“11”andcannotbechanged.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Capture Input ModeToselectthismodebitsPTnM1andPTnM0inthePTMnC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedonthePTPnorPTCKnpin,selectedbythePTnCKSbitinthePTMnC1register.Theinputpinactiveedgecanbearisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingthePTnIO1andPTnIO0bitsinthePTMnC1register.ThecounterisstartedwhenthePTnONbitchangesfromlowtohighwhichis initiatedusingtheapplicationprogram.

Whentherequirededge transitionappearson thePTPnorPTCKnpin thepresentvalue in thecounterwillbelatchedintotheCCRAregistersandaTMinterruptgenerated.Irrespectiveofwhateventsoccuron thePTPnorPTCKnpin thecounterwillcontinue tofreerununtil thePTnONbitchangesfromhighto low.WhenaCCRPcomparematchoccurs thecounterwill resetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.ThePTnIO1andPTnIO0bitscanselecttheactivetriggeredgeonthePTPnorPTCKnpintobearisingedge,fallingedgeorbothedgetypes.IfthePTnIO1andPTnIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensonthePTPnorPTCKnpin,howeveritmustbenotedthatthecounterwillcontinuetorun.

AsthePTPnpinispinorPTCKnpinsharedwithotherfunctions,caremustbetakenifthePTMnisintheInputCaptureMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.ThePTnCCLR,PTnOCandPTnPOLbitsarenotusedinthisMode.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Counte� Value

YY

CCRP

PTnO�

PTnPAU

CCRP Int. Flag PTMnPF

CCRA Int. Flag PTMnAF

CCRA Value

Ti�e

Counte� clea�ed �y CCRP

PauseResu�e

Counte� Reset

PTnM[1:0] = 01

PTMn Captu�e PinPTPn o� PTCKn

XX

Counte� Stop

PTnIO [1:�] Value

Active edge

Activeedge Active edge

�� - Rising edge �1 - Falling edge 1� - Both edges 11 - Disa�le Captu�e

XX YY XX YY

Capture Input Mode (n=0, 1)Note:1.PTnM[1:0]=01andactiveedgesetbythePTnIO[1:0]bits

2.ATMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.PTnCCLRbitnotused4.Nooutputfunction–PTnOCandPTnPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Analog to Digital ConverterTheneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.

A/D OverviewThedevicecontainsa8-channelanalogtodigitalconverterwhichcandirectlyinterfacetoexternalanalogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoa12-bitdigitalvalue.

TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.

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A/D Converter Structure

A/D Converter Register DescriptionOveralloperationoftheA/Dconverter iscontrolledusingfiveregisters.AreadonlyregisterpairexiststostoretheADCdata12-bitvalue.TheremainingthreeregistersarecontrolregisterswhichsetuptheoperatingandcontrolfunctionoftheA/Dconverter.

RegisterName

Bit

7 6 5 4 3 2 1 0ADRL(ADRFS=�) D3 D2 D1 D� — — — —ADRH(ADRFS=�) D11 D1� D� D8 D� D6 D5 D4ADRL(ADRFS=1) D� D6 D5 D4 D3 D2 D1 D�ADRH(ADRFS=1) — — — — D11 D1� D� D8ADCR� START EOCB ADOFF ADRFS — ACS2 ACS1 ACS�ADCR1 ACS4 V125E� — VREFS1 VREFS� ADCK2 ADCK1 ADCK�ACERL ACE� ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE�

A/D Converter Register List

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

A/D Converter Data Registers – ADRL, ADRHAsthedevicecontainsaninternal12-bitA/Dconverter, itrequirestwodataregisterstostoretheconvertedvalue.Theseareahighbyteregister,knownasADRH,andalowbyteregister,knownasADRL.After theconversionprocess takesplace, these registerscanbedirectly readby themicrocontrollertoobtainthedigitisedconversionvalue.Asonly12bitsofthe16-bitregisterspaceisutilised, theformat inwhichthedata isstorediscontrolledbytheADRFSbit in theADCR0registerasshownintheaccompanyingtable.D0~D11aretheA/Dconversionresultdatabits.Anyunusedbitswillbereadaszero.

ADRFSADRH ADRL

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0� D11 D1� D� D8 D� D6 D5 D4 D3 D2 D1 D� � � � �1 � � � � D11 D1� D� D8 D� D6 D5 D4 D3 D2 D1 D�

A/D Data Registers

A/D Converter Control Registers – ADCR0, ADCR1, ACERLTocontrol the functionandoperationof theA/Dconverter, threecontrol registersknownasADCR0,ADCR1,ACERLareprovided.These8-bitregistersdefinefunctionssuchastheselectionofwhichanalogchannelisconnectedtotheinternalA/Dconverter, thedigitiseddataformat, theA/DclocksourceaswellascontrollingthestartfunctionandmonitoringtheA/Dconverterendofconversionstatus.TheACS4intheADCR1registerandACS2~ACS0bitsintheADCR0registerdefine theADCinputchannelnumber.As thedevicecontainsonlyoneactualanalogtodigitalconverterhardwarecircuit,eachoftheindividual8analoginputsmustberoutedtotheconverter.ItisthefunctionoftheACS4,ACS2~ACS0bitstodeterminewhichanalogchannelinputsignalsorinternalVBGisactuallyconnectedtotheinternalA/Dconverter.

TheACERLcontrolregistercontainstheACE7~ACE0bitswhichdeterminewhichpinsonPortCareusedasanaloginputsfortheA/DconverterinputandwhichpinsarenottobeusedastheA/Dconverterinput.SettingthecorrespondingbithighwillselecttheA/Dinputfunction,clearingthebittozerowillselecteithertheI/Oorotherpin-sharedfunction.WhenthepinisselectedtobeanA/Dinput,itsoriginalfunctionwhetheritisanI/Oorotherpin-sharedfunctionwillberemoved.Inaddition,anyinternalpull-highresistorsconnectedtothesepinswillbeautomaticallyremovedifthepinisselectedtobeanA/Dinput.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

ADCR0 Register

Bit 7 6 5 4 3 2 1 0�a�e START EOCB ADOFF ADRFS — ACS2 ACS1 ACS�R/W R/W R R/W R/W — R/W R/W R/WPOR � 1 1 � — � � �

Bit7 START:StarttheA/Dconversion0→1→0:start0→1:resettheA/DconverterandsetEOCBto"1"

ThisbitisusedtoinitiateanA/Dconversionprocess.Thebitisnormallylowbutifsethighandthenclearedlowagain,theA/Dconverterwillinitiateaconversionprocess.WhenthebitissethightheA/Dconverterwillbereset.

Bit6 EOCB:EndofA/Dconversionflag0:A/Dconversionended1:A/Dconversioninprogress

ThisreadonlyflagisusedtoindicatewhenanA/Dconversionprocesshascompleted.Whentheconversionprocessisrunningthebitwillbehigh.

Bit5 ADOFF :ADCmodulepoweron/offcontrolbit0:ADCmodulepoweron1:ADCmodulepoweroff

Thisbitcontrols thepowerto theA/Dinternalfunction.ThisbitshouldbeclearedtozerotoenabletheA/Dconverter.IfthebitissethighthentheA/Dconverterwillbeswitchedoffreducingthedevicepowerconsumption.AstheA/Dconverterwillconsumealimitedamountofpower,evenwhennotexecutingaconversion,thismaybeanimportantconsiderationinpowersensitivebatterypoweredapplications.Note:1.itisrecommendedtosetADOFF=1beforeenteringIDLE/SLEEPModefor

savingpower.2.ADOFF=1willpowerdowntheADCmodule.

Bit4 ADRFS:ADCDataFormatControl0:ADCDataMSBisADRHbit7,LSBisADRLbit41:ADCDataMSBisADRHbit3,LSBisADRLbit0

Thisbitcontrols theformatof the12-bitconvertedA/Dvaluein thetwoA/Ddataregisters.DetailsareprovidedintheA/Ddataregistersection.

Bit3 Unimplemented,readas“0”Bit2~0 ACS2 ~ ACS0:SelectA/Dchannel(whenACS4is“0”)

000:AN0001:AN1010:AN2011:AN3100:AN4101:AN5110:AN6111:AN7

ThesearetheA/Dchannelselectcontrolbits.AsthereisonlyoneinternalhardwareA/DconvertereachoftheeightA/Dinputsmustberoutedtotheinternalconverterusingthesebits.IfbitACS4intheADCR1registerissethighthentheinternalVBGwillberoutedtotheA/DConverter.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

ADCR1 Register

Bit 7 6 5 4 3 2 1 0�a�e ACS4 V125E� — — VREFS ADCK2 ADCK1 ADCK�R/W R/W R/W — — R/W R/W R/W R/WPOR � � — — � � � �

Bit7 ACS4:SelecteInternalVBGasADCinputControl0:Disable1:Enable

ThisbitenablesVBG tobeconnected to theA/Dconverter.TheV125ENbitmustfirsthavebeenset toenablethebandgapcircuitVBGvoltagetobeusedbytheA/Dconverter.WhentheACS4bitissethigh,thebandgapvoltagewillberoutedtotheA/DconverterandtheotherA/Dinputchannelsdisconnected.

Bit6 V125EN:InternalVBGControl0:Disable1:Enable

Thisbitcontrols the internalBandgapcircuiton/offfunctionto theA/Dconverter.WhenthebitissethighthebandgapvoltageVBGcanbeusedbytheA/Dconverter.IfVBG isnotusedbytheA/DconverterandtheLVRfunctionisdisabledthenthebandgapreferencecircuitwillbeautomaticallyswitchedofftoconservepower.WhenVBGisswitchedonforusebytheA/Dconverter,atimetBGshouldbeallowedforthebandgapcircuittostabilisebeforeimplementinganA/Dconversion.

Bit5~4 Unimplemented,readas"0"Bit3 VREFS:SelecteADCreferencevoltage

0:InternalADCpowerAVDD

1:VREFpinThisbitisusedtoselectthereferencevoltagefortheA/Dconverter.Ifthebitis1thentheA/DconverterreferencevoltageissuppliedontheexternalpinVREF.Ifthepinis0thentheinternalreferenceisusedwhichistakenfromthepowersupplypinAVDD.WhentheA/DconverterreferencevoltageissuppliedontheexternalpinVREFwhichispin-sharedwithotherfunctions,alloftheotherpin-sharedfunctionsonthispinaredisabled.

Bit2~0 ADCK2 ~ ADCK0:SelectADCclocksource000:fSYS

001:fSYS/2010:fSYS/4011:fSYS/8100:fSYS/16101:fSYS/32110:fSYS/64111:Undefined

ThesethreebitsareusedtoselecttheclocksourcefortheA/Dconverter.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

ACERL Register

Bit 7 6 5 4 3 2 1 0�a�e ACE� ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

Bit7 ACE7:DefinePB1isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN7

Bit6 ACE6:DefinePC6isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN6

Bit5 ACE5:DefinePC5isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN5

Bit4 ACE4:DefinePC4isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN4

Bit3 ACE3:DefinePC3isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN3

Bit2 ACE2:DefinePC0isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN2

Bit1 ACE1:DefinePB7isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN1

Bit0 ACE0:DefinePB6isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN0

A/D OperationTheSTARTbit in theADCR0register isused tostartand reset theA/Dconverter.When themicrocontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbe initiated.WhentheSTARTbit isbroughtfromlowtohighbutnot lowagain, theEOCBbitintheADCR0registerwillbesethighandtheanalogtodigitalconverterwillbereset.ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigitalconverter.

TheEOCBbit in theADCR0register isused to indicatewhentheanalogtodigitalconversionprocess is complete.Thisbitwillbeautomatically set to “0”by themicrocontroller after aconversioncyclehasended.Inaddition, thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andif theinterruptsareenabled,anappropriateinternalinterruptsignalwillbegenerated.ThisA/Dinternal interruptsignalwilldirect theprogramflowto theassociatedA/Dinternal interruptaddressforprocessing.If theA/Dinternal interrupt isdisabled,themicrocontrollercanbeusedtopolltheEOCBbitintheADCR0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.

TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosentobeeither fSYSorasubdividedversionof fSYS.Thedivisionratiovalue isdeterminedby theADCK2~ADCK0bitsintheADCR1register.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYS,andbybitsADCK2~ADCK0,thereare some limitationson theA/Dclocksource speed range thatcanbe selected.As therecommendedrangeofpermissibleA/Dclockperiod,tAD,isfrom0.5μsto10μs,caremustbetakenforsystemclockfrequencies.Forexample,ifthesystemclockoperatesatafrequencyof4MHz,theADCK2~ADCK0bitsshouldnotbesetto000Bor110B.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/DclockperiodorgreaterthanthemaximumA/DclockperiodwhichmayresultininaccurateA/Dconversionvalues.

Refer to thefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod.

fSYS

A/D Clock Period (tAD)ADCK2,ADCK1,ADCK0

=000(fSYS)

ADCK2,ADCK1,ADCK0

=001(fSYS/2)

ADCK2,ADCK1, ADCK0

=010(fSYS/4)

ADCK2,ADCK1, ADCK0

=011(fSYS/8)

ADCK2,ADCK1,ADCK0

=100(fSYS/16)

ADCK2,ADCK1,ADCK0

=101(fSYS/32)

ADCK2,ADCK1,ADCK0

=110(fSYS/64)

ADCK2,ADCK1,ADCK0

=111

1MHz 1μs 2μs 4μs 8μs 16μs* 32μs* 64μs* Undefined2MHz 5��ns 1μs 2μs 4μs 8μs 16μs* 32μs* Undefined4MHz 250ns* 5��ns 1μs 2μs 4μs 8μs 16μs* Undefined8MHz 125ns* 250ns* 5��ns 1μs 2μs 4μs 8μs Undefined

12MHz 83ns* 167ns* 333ns* 66�ns 1.33μs 2.67μs 5.33μs Undefined16MHz 62ns* 125ns* 250ns* 5��ns 1μs 2μs 4μs Undefined

A/D Clock Period Examples

Controlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theADOFFbitintheADCR0register.ThisbitmustbezerotopowerontheA/Dconverter.WhentheADOFFbit isclearedtozerotopowerontheA/Dconverter internalcircuitryacertaindelay,asindicatedinthetimingdiagram,mustbeallowedbeforeanA/Dconversionisinitiated.EvenifnopinsareselectedforuseasA/DinputsbyclearingtheACE7~ACE0bitsintheACERLregisters,iftheADOFFbitiszerothensomepowerwillstillbeconsumed.InpowerconsciousapplicationsitisthereforerecommendedthattheADOFFissethightoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.

ThereferencevoltagesupplytotheA/DConvertercanbesuppliedfromeitherthepositivepowersupplypin,AVDD,or fromanexternal referencesource suppliedonpinVREF.ThedesiredselectionismadeusingtheVREFSbit.Asthepinispin-sharedwithotherfunction,whentheVREFpinfunctionisselected,thentheotherpinfunctionswillbedisabledautomatically.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

A/D Input PinsAllof theA/Danalog inputpinsarepin-sharedwith the I/OpinsonPortCaswellasotherfunctions.TheACE7~ACE0bitsintheACERLregisters,determinewhethertheinputpinsaresetupasA/Dconverteranaloginputsorwhethertheyhaveotherfunctions.IftheACE7~ACE0bitsforitscorrespondingpinissethighthenthepinwillbesetuptobeanA/Dconverterinputandtheoriginalpinfunctionsdisabled. In thisway,pinscanbechangedunderprogramcontrol tochange theirfunctionbetweenA/Dinputsandotherfunctions.Allpull-highresistors,whicharesetupthroughregisterprogramming,willbeautomaticallydisconnectedifthepinsaresetupasA/Dinputs.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputinthePCCportcontrolregistertoenabletheA/DinputaswhentheACE7~ACE0bitsenableanA/Dinput, thestatusof theportcontrolregisterwillbeoverridden.

TheA/Dconverterhasitsownreferencevoltagepins,VREF,howeverthereferencevoltagecanalsobesuppliedfromthepowersupplypin,achoicewhichismadethroughtheVREFSbitintheADCR1register.

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A/D Input Structure

Summary of A/D Conversion StepsThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.

• Step1SelecttherequiredA/DconversionclockbycorrectlyprogrammingbitsADCK2~ADCK0intheADCR1register.

• Step2EnabletheA/DbyclearingtheADOFFbitintheADCR0registertozero.

• Step3SelectwhichchannelistobeconnectedtotheinternalA/DconverterbycorrectlyprogrammingtheACS4,ACS2~ACS0bitswhicharealsocontainedintheADCR1andADCR0register.

• Step4SelectwhichpinsaretobeusedasA/DinputsandconfigurethembycorrectlyprogrammingtheACE7~ACE0bitsintheACERLregister.

• Step5If theinterruptsare tobeused, theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dconverterinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,andtheA/Dconverterinterruptbit,ADE,mustbothbesethightodothis.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

• Step6Theanalog todigitalconversionprocesscannowbe initialisedbysetting theSTARTbit intheADCR0registerfromlowtohighandthenlowagain.Notethat thisbitshouldhavebeenoriginallyclearedtozero.

• Step7Tocheckwhentheanalogtodigitalconversionprocessiscomplete,theEOCBbitintheADCR0registercanbepolled.Theconversionprocessiscompletewhenthisbitgoeslow.WhenthisoccurstheA/DdataregistersADRLandADRHcanbereadtoobtaintheconversionvalue.Asanalternativemethod,iftheinterruptsareenabledandthestackisnotfull,theprogramcanwaitforanA/Dinterrupttooccur.Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingtheEOCB

bitintheADCR0registerisused,theinterruptenablestepabovecanbeomitted.

Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.AfteranA/Dconversionprocesshasbeeninitiatedby theapplicationprogram, themicrocontroller internalhardwarewillbegin tocarryout theconversion,duringwhichtimetheprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADwheretADisequaltotheA/Dclockperiod.

ADC module ON

START

EOCB

ACS[4, 2:0]

off on off ontON2ST

tADCS

A/D sampling timetADCS

A/D sampling time

Start of A/D conversion

Reset A/D conversion

Start of A/D conversion

tADC

A/D conversion timetADC

A/D conversion time

0011B 0010B 0000B 0001B

ADOFF

End of A/D conversion

Reset A/D conversion

End of A/D conversion

Start of A/D conversion

Reset A/D conversion

Power-on Reset

Note: A/D clock must be fSYS, fSYS/2, fSYS/4, fSYS/8, fSYS/16, fSYS/32, fSYS/64, tADCS=4tADtADC=tADCS+n*tAD; n=bit count of ADC resolutiontON2ST: at least one instruction cycle (fSYS = 12MHz)

A/D Conversion Timing

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff to reducepowerconsumption,bysettingbitADOFFhigh in theADCR0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Os,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.

A/D Transfer FunctionAsthedevicecontainsa12-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal toFFFH.Sincethefull-scaleanaloginputvalueisequaltotheAVDDorVREFvoltage,thisgivesasinglebitanaloginputvalueofAVDDorVREFdividedby4096.

1LSB=(AVDDorVREF)/4096

TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:

A/Dinputvoltage=A/Doutputdigitalvalue×(AVDDorVREF)/4096

Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheAVDDorVREFlevel.

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Ideal A/D Transfer Function

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

A/D Programming ExamplesThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheEOCBbit intheADCR0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example: using an EOCB polling method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov ADCR1,a ; select fSYS/8 as A/D clock and switch off VBGclr ADOFFmov a,0Fh ; setup ACERL to configure pins AN0~AN3mov ACERL,amov a,00hmov ADCR0,a ; enable and connect AN0 channel to A/D converter:start_conversion:clr START ; high pulse on start bit to initiate conversionset START ; reset A/Dclr START ; start A/Dpolling_EOC:sz EOCB ; poll the ADCR0 register EOCB bit to detect end of A/D conversionjmp polling_EOC ; continue pollingmov a,ADRL ; read low byte conversion result valuemov ADRL_buffer,a ; save result to user defined registermov a,ADRH ; read high byte conversion result valuemov ADRH_buffer,a ; save result to user defined register::jmp start_conversion ; start next a/d conversion

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Example: using the interrupt method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov ADCR1,a ; select fSYS/8 as A/D clock and switch off VBGClr ADOFFmov a,0Fh ; setup ACERL to configure pins AN0~AN3mov ACERL,amov a,00hmov ADCR0,a ; enable and connect AN0 channel to A/D converterStart_conversion:clr START ; high pulse on START bit to initiate conversionset START ; reset A/Dclr START ; start A/Dclr ADF ; clear ADC interrupt request flagset ADE ; enable ADC interruptset EMI ; enable global interrupt:: ; ADC interrupt service routineADC_ISR:mov acc_stack,a ; save ACC to user defined memorymov a,STATUSmov status_stack,a ; save STATUS to user defined memory::mov a,ADRL ; read low byte conversion result valuemov adrl_buffer,a ; save result to user defined registermov a,ADRH ; read high byte conversion result valuemov adrh_buffer,a ; save result to user defined register::EXIT_INT_ISR:mov a,status_stackmov STATUS,a ; restore STATUS from user defined memorymov a,acc_stack ; restore ACC from user defined memoryreti

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Serial Interface Module – SIMThedevicecontainsaSerialInterfaceModule,whichincludesboththefour-lineSPIinterfaceortwo-lineI2Cinterfacetypes, toallowaneasymethodofcommunicationwithexternalperipheralhardware.Havingrelativelysimplecommunicationprotocols, theseserial interface typesallowthemicrocontroller to interface toexternalSPIorI2Cbasedhardwaresuchassensors,FlashorEEPROMmemory,etc.TheSIMinterfacepinsarepin-sharedwithotherI/OpinsandthereforetheSIMinterfacefunctionalpinsmustfirstbeselectedusingthecorrespondingpin-sharedfunctionselectionbits.Asbothinterfacetypessharethesamepinsandregisters,thechoiceofwhethertheSPIorI2CtypeisusedismadeusingtheSIMoperatingmodecontrolbits,namedSIM2~SIM0,intheSIMC0register.Thesepull-highresistorsoftheSIMpin-sharedI/Opinsareselectedusingpull-highcontrolregisterswhentheSIMfunctionisenabledandthecorrespondingpinsareusedasSIMinputpins.

SPI InterfaceTheSPIinterfaceisoftenusedtocommunicatewithexternalperipheraldevicessuchassensors,FlashMemoryorEEPROMmemorydevicesetc.OriginallydevelopedbyMotorola,thefourlineSPI interface isasynchronousserialdata interface thathasa relativelysimplecommunicationprotocolsimplifyingtheprogrammingrequirementswhencommunicatingwithexternalhardwaredevices.

Thecommunicationisfullduplexandoperatesasaslave/mastertype,wherethedevicecanbeeithermasterorslave.AlthoughtheSPIinterfacespecificationcancontrolmultipleslavedevicesfromasinglemaster,butthedeviceprovidesonlyoneSCSpin.Ifthemasterneedstocontrolmultipleslavedevicesfromasinglemaster,themastercanuseI/Opintoselecttheslavedevices.

SPI Interface OperationTheSPIinterfaceisafullduplexsynchronousserialdatalink.It isafourlineinterfacewithpinnamesSDI,SDO,SCKandSCS.PinsSDIandSDOare theSerialData InputandSerialDataOutputlines,SCKistheSerialClocklineandSCSistheSlaveSelectline.AstheSPIinterfacepinsarepin-sharedwithnormalI/OpinsandwiththeI2Cfunctionpins,theSPIinterfacepinsmustfirstbeselectedbyconfiguringthepin-sharedfunctionselectionbitsandsettingthecorrectbitsintheSIMC0andSIMC2registers.AfterthedesiredSPIconfigurationhasbeensetitcanalsobedisabledorenabledusingtheSIMENbitintheSIMC0register.Communicationbetweendevicesconnectedto theSPI interface iscarriedout inaslave/mastermodewithalldata transfer initiationsbeingimplementedbythemaster.TheMasteralsocontrolstheclocksignal.AsthedeviceonlycontainsasingleSCSpinonlyoneslavedevicecanbeutilized.TheSCSpiniscontrolledbysoftware,setCSENbitto“1”toenableSCSpinfunction,setCSENbitto“0”theSCSpinwillbefloatingstate.

TheSPIfunctioninthisdeviceoffersthefollowingfeatures:

• Fullduplexsynchronousdatatransfer

• BothMasterandSlavemodes

• LSBfirstorMSBfirstdatatransmissionmodes

• Transmissioncompleteflag

• Risingorfallingactiveclockedge

ThestatusoftheSPIinterfacepinsisdeterminedbyanumberoffactorssuchaswhetherthedeviceis in themasterorslavemodeandupontheconditionofcertaincontrolbitssuchasCSENandSIMEN.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

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SPI Master/Slave Connection

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SPI Block Diagram

SPI RegisterTherearethreeinternalregisterswhichcontroltheoveralloperationoftheSPIinterface.ThesearetheSIMDdataregisterandtwocontrolregistersSIMC0andSIMC2.

RegisterName

Bit

7 6 5 4 3 2 1 0SIMC� SIM2 SIM1 SIM� — SIMDB�C1 SIMDB�C� SIME� SPIICFSIMD D� D6 D5 D4 D3 D2 D1 D�

SIMC2 D� D6 CKPOLB CKEG MLS CSE� WCOL TRF

SIM Registers List

TheSIMDregisterisusedtostorethedatabeingtransmittedandreceived.ThesameregisterisusedbyboththeSPIandI2Cfunctions.BeforethedeviceswritedatatotheSPIbus,theactualdatatobetransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheSPIbus,thedevicecanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheSPIbusmustbemadeviatheSIMDregister.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

SIMD Register

Bit 7 6 5 4 3 2 1 0�a�e D� D6 D5 D4 D3 D2 D1 D�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR × × × × × × × ×

"×": unknownTherearealsotwocontrolregistersfortheSPIinterface,SIMC0andSIMC2.NotethattheSIMC2registeralsohasthenameSIMAwhichisusedbytheI2Cfunction.TheSIMC1registerisnotusedbytheSPIfunction,onlybytheI2Cfunction.RegisterSIMC0isusedtocontroltheenable/disablefunctionandtoset thedata transmissionclockfrequency.Althoughnotconnectedwith theSPIfunction,theSIMC0registerisalsousedtocontrolthePeripheralClockPrescaler.RegisterSIMC2isusedforothercontrolfunctionssuchasLSB/MSBselection,writecollisionflagetc.

SIMC0 Register

Bit 7 6 5 4 3 2 1 0�a�e SIM2 SIM1 SIM� — SIMDB�C1 SIMDB�C� SIME� SPIICFR/W R/W R/W R/W — R/W R/W R/W R/WPOR 1 1 1 — � � � �

Bit7~5 SIM2~SIM0:SIMOperatingModeControl000:SPImastermode;SPIclockisfSYS/4001:SPImastermode;SPIclockisfSYS/16010:SPImastermode;SPIclockisfSYS/64011:SPImastermode;SPIclockisfSUB

100:SPImastermode;SPIclockisCTMCCRPmatchfrequency/2101:SPIslavemode110:I2Cslavemode111:Unusedmode

ThesebitssetuptheoveralloperatingmodeoftheSIMfunction.AswellasselectingiftheI2CorSPIfunction,theyareusedtocontroltheSPIMaster/SlaveselectionandtheSPIMasterclockfrequency.TheSPIclockisafunctionofthesystemclockbutcanalsobechosentobesourcedfromtheCTM.If theSPISlaveModeisselectedthentheclockwillbesuppliedbyanexternalMasterdevice.

Bit4 Unimplemented,readas“0”Bit3~2 SIMDBNC1~SIMDBNC0:I2CDebounceTimeSelection

00:Nodebounce01:2systemclocksdebounce1x:4systemclocksdebounce

Bit1 SIMEN:SIMControl0:Disable1:Enable

Thebit is theoverallon/offcontrolfor theSIMinterface.WhentheSIMENbit isclearedtozerotodisabletheSIMinterface,theSDI,SDO,SCKandSCS,orSDAandSCLlineswill losetheirSPIorI2CfunctionandtheSIMoperatingcurrentwillbereducedtoaminimumvalue.WhenthebitishightheSIMinterfaceisenabled.IftheSIMisconfiguredtooperateasanSPIinterfaceviatheSIM2~SIM0bits,thecontentsoftheSPIcontrolregisterswillremainattheprevioussettingswhentheSIMENbitchangesfromlowtohighandshouldthereforebefirst initialisedbytheapplicationprogram.IftheSIMisconfiguredtooperateasanI2CinterfaceviatheSIM2~SIM0bitsandtheSIMENbitchangesfromlowtohigh,thecontentsoftheI2CcontrolbitssuchasHTXandTXAKwillremainattheprevioussettingsandshouldthereforebefirstinitialisedbytheapplicationprogramwhiletherelevantI2CflagssuchasHCF,HAAS,HBB,SRWandRXAKwillbesettotheirdefaultstates.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Bit0 SPIICF:SPIIncompletedFlag0:SPIincompletedisnotoccurred1:SPIincompletedisoccurred

TheSPIICFbitisdeterminedbySCSpin.WhenSCSpinissetto“1”,itwillcleartheSPIcounter.Meanwhile,theinterruptisoccurred,ifslavedevicedidn’tcompletedatareceived,thentheincompletedflag,SPIICF,issetto“1”.

SIMC2 Register

Bit 7 6 5 4 3 2 1 0�a�e D� D6 CKPOLB CKEG MLS CSE� WCOL TRFR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~6 UndefinedbitsThesebitscanbereadorwrittenbyusersoftwareprogram.

Bit5 CKPOLB:Determinesthebaseconditionoftheclockline0:TheSCKlinewillbehighwhentheclockisinactive1:TheSCKlinewillbelowwhentheclockisinactive

TheCKPOLBbitdeterminesthebaseconditionoftheclockline, if thebit ishigh,thentheSCKlinewillbelowwhentheclockisinactive.WhentheCKPOLBbitislow,thentheSCKlinewillbehighwhentheclockisinactive.

Bit4 CKEG:DeterminesSPISCKactiveclockedgetypeCKPOLB=00:SCKishighbaselevelanddatacaptureatSCKrisingedge1:SCKishighbaselevelanddatacaptureatSCKfallingedge

CKPOLB=10:SCKislowbaselevelanddatacaptureatSCKfallingedge1:SCKislowbaselevelanddatacaptureatSCKrisingedge

TheCKEGandCKPOLBbitsareusedtosetupthewaythattheclocksignaloutputsandinputsdataontheSPIbus.Thesetwobitsmustbeconfiguredbeforedatatransferisexecutedotherwiseanerroneousclockedgemaybegenerated.TheCKPOLBbitdeterminesthebaseconditionoftheclockline, if thebit ishigh,thentheSCKlinewillbelowwhentheclockisinactive.WhentheCKPOLBbitislow,thentheSCKlinewillbehighwhentheclockis inactive.TheCKEGbitdeterminesactiveclockedgetypewhichdependsupontheconditionofCKPOLBbit.

Bit3 MLS:SPIDatashiftorder0:LSB1:MSB

Thisisthedatashiftselectbitandisusedtoselecthowthedataistransferred,eitherMSBorLSBfirst.SettingthebithighwillselectMSBfirstandlowforLSBfirst.

Bit2 CSEN:SPISCSpinControl0:Disable1:Enable

TheCSENbitisusedasanenable/disablefortheSCSpin.Ifthisbitislow,thentheSCSpinwillbedisabledandplacedintoI/Opinortheotherfunctions.If thebit ishightheSCSpinwillbeenabledandusedasaselectpin.

Bit1 WCOL:SPIWriteCollisionflag0:Nocollision1:Collision

TheWCOLflagisusedtodetectifadatacollisionhasoccurred.IfthisbitishighitmeansthatdatahasbeenattemptedtobewrittentotheSIMDregisterduringadatatransferoperation.Thiswritingoperationwillbeignoredifdataisbeingtransferred.Thebitcanbeclearedbytheapplicationprogram.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Bit0 TRF:SPITransmit/ReceiveCompleteflag0:Dataisbeingtransferred1:SPIdatatransmissioniscompleted

TheTRFbitistheTransmit/ReceiveCompleteflagandisset“1”automaticallywhenanSPIdatatransmissioniscompleted,butmustsetto“0”bytheapplicationprogram.Itcanbeusedtogenerateaninterrupt.

SPI CommunicationAftertheSPIinterfaceisenabledbysettingtheSIMENbithigh,thenintheMasterMode,whendataiswrittentotheSIMDregister, transmission/receptionwillbeginsimultaneously.Whenthedata transfer iscomplete, theTRFflagwillbesetautomatically,butmustbeclearedusing theapplicationprogram.IntheSlaveMode,whentheclocksignalfromthemasterhasbeenreceived,anydataintheSIMDregisterwillbetransmittedandanydataontheSDIpinwillbeshiftedintotheSIMDregister.ThemastershouldoutputaSCSsignaltoenabletheslavedevicebeforeaclocksignal isprovided.Theslavedata tobe transferredshouldbewellpreparedat theappropriatemomentrelativetotheSCSsignaldependingupontheconfigurationsoftheCKPOLBbitandCKEGbit.TheaccompanyingtimingdiagramshowstherelationshipbetweentheslavedataandSCSsignalforvariousconfigurationsoftheCKPOLBandCKEGbits.TheSPIwillcontinuetofunctionevenintheIDLEMode.

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SPI Master Mode Timing

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SPI Slave Mode Timing – CKEG=0

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

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SPI Slave Mode Timing – CKEG=1

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SPI Transfer Control Flowchart

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

I2C InterfaceThe I2C interface isused to communicatewith externalperipheraldevices suchas sensors,EEPROMmemoryetc.OriginallydevelopedbyPhilips,it isatwolinelowspeedserialinterfaceforsynchronousserialdatatransfer.Theadvantageofonlytwolinesforcommunication,relativelysimplecommunicationprotocolandtheabilitytoaccommodatemultipledevicesonthesamebushasmadeitanextremelypopularinterfacetypeformanyapplications.

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I2C Master Slave Bus Connection

I2C Interface OperationTheI2Cserialinterfaceisatwolineinterface,aserialdataline,SDA,andserialclockline,SCL.Asmanydevicesmaybeconnectedtogetheronthesamebus,theiroutputsarebothopendraintypes.Forthisreasonitisnecessarythatexternalpull-highresistorsareconnectedtotheseoutputs.Notethatnochipselectlineexists,aseachdeviceontheI2CbusisidentifiedbyauniqueaddresswhichwillbetransmittedandreceivedontheI2Cbus.

WhentwodevicescommunicatewitheachotheronthebidirectionalI2Cbus,oneisknownasthemasterdeviceandoneas theslavedevice.Bothmasterandslavecantransmitandreceivedata,however, it isthemasterdevicethathasoverallcontrolofthebus.Forthesedevices,whichonlyoperatesinslavemode,therearetwomethodsoftransferringdataontheI2Cbus,theslavetransmitmodeandtheslavereceivemode.Thepull-upcontrolfunctionpin-sharedwithSCL/SDApinisstillapplicableevenifI2Cdeviceisactivatedandtherelatedinternalpull-upregistercouldbecontrolledbyitscorrespondingpull-upcontrolregister.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

I2C RegisterTherearefourcontrolregistersassociatedwiththeI2Cbus,SIMC0,SIMC1,SIMAandSIMTOCandonedataregister,SIMD.TheSIMDregister,whichisshownintheaboveSPIsection,isusedtostorethedatabeingtransmittedandreceivedontheI2Cbus.BeforethemicrocontrollerwritesdatatotheI2Cbus,theactualdatatobetransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheI2Cbus,themicrocontrollercanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheI2CbusmustbemadeviatheSIMDregister.

NotethattheSIMAregisteralsohasthenameSIMC2whichisusedbytheSPIfunction.BitSIMENandbitsSIM2~SIM0inregisterSIMC0areusedbytheI2Cinterface.TheSIMTOCregisterisusedforI2Ctime-outcontrolfunction.

RegisterName

Bit

7 6 5 4 3 2 1 0SIMC� SIM2 SIM1 SIM� — SIMDEB1 SIMDEB� SIME� SPIICFSIMC1 HCF HAAS HBB HTX TXAK SRW RCI� RXAKSIMD D� D6 D5 D4 D3 D2 D1 D�SIMA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA� D�

SIMTOC SIMTOE� SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS�

I2C Register List

SIMC0 Register

Bit 7 6 5 4 3 2 1 0�a�e SIM2 SIM1 SIM� — SIMDB�C1 SIMDB�C� SIME� SPIICFR/W R/W R/W R/W — R/W R/W R/W R/WPOR 1 1 1 — � � � �

Bit7~5 SIM2~SIM0:SIMOperatingModeControl000:SPImastermode;SPIclockisfSYS/4001:SPImastermode;SPIclockisfSYS/16010:SPImastermode;SPIclockisfSYS/64011:SPImastermode;SPIclockisfSUB

100:SPImastermode;SPIclockisCTMCCRPmatchfrequency/2101:SPIslavemode110:I2Cslavemode111:Unusedmode

ThesebitssetuptheoveralloperatingmodeoftheSIMfunction.AswellasselectingiftheI2CorSPIfunction,theyareusedtocontroltheSPIMaster/SlaveselectionandtheSPIMasterclockfrequency.TheSPIclockisafunctionofthesystemclockbutcanalsobechosentobesourcedfromtheCTM.If theSPISlaveModeisselectedthentheclockwillbesuppliedbyanexternalMasterdevice.

Bit4 Unimplemented,readas“0”Bit3~2 SIMDBNC1~SIMDBNC0:I2CDebounceTimeSelection

00:Nodebounce01:2systemclocksdebounce1x:4systemclocksdebounce

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Bit1 SIMEN:SIMControl0:Disable1:Enable

Thebit is theoverallon/offcontrolfor theSIMinterface.WhentheSIMENbit isclearedtozerotodisabletheSIMinterface,theSDI,SDO,SCKandSCS,orSDAandSCLlineswill losetheirSPIorI2CfunctionandtheSIMoperatingcurrentwillbereducedtoaminimumvalue.WhenthebitishightheSIMinterfaceisenabled.IftheSIMisconfiguredtooperateasanSPIinterfaceviatheSIM2~SIM0bits,thecontentsoftheSPIcontrolregisterswillremainattheprevioussettingswhentheSIMENbitchangesfromlowtohighandshouldthereforebefirst initialisedbytheapplicationprogram.IftheSIMisconfiguredtooperateasanI2CinterfaceviatheSIM2~SIM0bitsandtheSIMENbitchangesfromlowtohigh,thecontentsoftheI2CcontrolbitssuchasHTXandTXAKwillremainattheprevioussettingsandshouldthereforebefirstinitialisedbytheapplicationprogramwhiletherelevantI2CflagssuchasHCF,HAAS,HBB,SRWandRXAKwillbesettotheirdefaultstates.

Bit0 SPIICF:SPIIncompletedFlag0:SPIincompletedisnotoccurred1:SPIincompletedisoccurred

TheSPIICFbitisdeterminedbySCSpin.WhenSCSpinissetto“1”,itwillcleartheSPIcounter.Meanwhile,theinterruptisoccurred,ifslavedevicedidn’tcompletedatareceived,thentheincompletedflag,SPIICF,issetto”1”.

SIMC1 Register

Bit 7 6 5 4 3 2 1 0�a�e HCF HAAS HBB HTX TXAK SRW IAMWU RXAKR/W R R R R/W R/W R R/W RPOR 1 � � � � � � 1

Bit7 HCF:I2CBusdatatransfercompletionflag0:Dataisbeingtransferred1:Completionofan8-bitdatatransfer

TheHCFflag is thedata transfer flag.This flagwillbezerowhendata isbeingtransferred.Uponcompletionofan8-bitdata transfer theflagwillgohighandaninterruptwillbegenerated.

Bit6 HAAS:I2CBusaddressmatchflag0:Notaddressmatch1:Addressmatch

TheHAASflagistheaddressmatchflag.Thisflagisusedtodetermineiftheslavedeviceaddressisthesameasthemastertransmitaddress.Iftheaddressesmatchthenthisbitwillbehigh,ifthereisnomatchthentheflagwillbelow.

Bit5 HBB:I2CBusbusyflag0:I2CBusisnotbusy1:I2CBusisbusy

TheHBBflagis theI2Cbusyflag.Thisflagwillbe“1”whentheI2Cbus isbusywhichwilloccurwhenaSTARTsignalisdetected.Theflagwillbesetto“0”whenthebusisfreewhichwilloccurwhenaSTOPsignalisdetected.

Bit4 HTX:SelectI2Cslavedeviceistransmitterorreceiver0:Slavedeviceisthereceiver1:Slavedeviceisthetransmitter

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Bit3 TXAK:I2CBustransmitacknowledgeflag0:Slavesendacknowledgeflag1:Slavedonotsendacknowledgeflag

TheTXAKbitisthetransmitacknowledgeflag.Aftertheslavedevicereceiptof8-bitsofdata,thisbitwillbetransmittedtothebusonthe9thclockfromtheslavedevice.TheslavedevicemustalwayssetTXAKbitto“0”beforefurtherdataisreceived.

Bit2 SRW:I2CSlaveRead/Writeflag0:Slavedeviceshouldbeinreceivemode1:Slavedeviceshouldbeintransmitmode

TheSRWflag is the I2CSlaveRead/Write flag.This flagdetermineswhetherthemasterdevicewishes to transmitor receivedata fromthe I2Cbus.When thetransmittedaddressandslaveaddressismatch,thatiswhentheHAASflagissethigh,theslavedevicewillchecktheSRWflagtodeterminewhetheritshouldbeintransmitmodeorreceivemode.IftheSRWflagishigh,themasterisrequestingtoreaddatafromthebus,so theslavedeviceshouldbe in transmitmode.WhentheSRWflagiszero,themasterwillwritedatatothebus,thereforetheslavedeviceshouldbeinreceivemodetoreadthisdata.

Bit1 IAMWU:I2CAddressMatchWake-upControl0:Disable1:Enable–mustbeclearedbytheapplicationprogramafterwake-up

Thisbitshouldbesetto1toenabletheI2CaddressmatchwakeupfromtheSLEEPorIDLEMode.IftheIAMWUbithasbeensetbeforeenteringtheSLEEPorIDLEmodetoenabletheI2Caddressmatchwakeup,thenthisbitmustbeclearedbytheapplicationprogramafterwake-uptoensurecorrectiondeviceoperation.

Bit0 RXAK:I2CBusReceiveacknowledgeflag0:Slavereceiveacknowledgeflag1:Slavedonotreceiveacknowledgeflag

TheRXAKflag is thereceiveracknowledgeflag.WhentheRXAKflag is“0”, itmeansthataacknowledgesignalhasbeenreceivedatthe9thclock,after8bitsofdatahavebeentransmitted.Whentheslavedeviceinthetransmitmode,theslavedevicecheckstheRXAKflagtodetermineifthemasterreceiverwishestoreceivethenextbyte.Theslavetransmitterwill thereforecontinuesendingoutdatauntil theRXAKflagis“1”.Whenthisoccurs,theslavetransmitterwillreleasetheSDAlinetoallowthemastertosendaSTOPsignaltoreleasetheI2CBus.TheSIMDregisterisusedtostorethedatabeingtransmittedandreceived.ThesameregisterisusedbyboththeSPIandI2Cfunctions.BeforethedevicewritesdatatotheI2Cbus,theactualdatatobetransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheI2Cbus,thedevicecanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheI2CbusmustbemadeviatheSIMDregister.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

SIMD Register

Bit 7 6 5 4 3 2 1 0�a�e D� D6 D5 D4 D3 D2 D1 D�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR × × × × × × × ×

"×": unknown

SIMA Register

Bit 7 6 5 4 3 2 1 0�a�e A6 A5 A4 A3 A2 A1 A� —R/W R/W R/W R/W R/W R/W R/W R/W —POR � � � � � � � —

bit7~1 A6~ A0:I2CslaveaddressA6~A0istheI2Cslaveaddressbit6~bit0.TheSIMAregister isalsousedbytheSPI interfacebuthas thenameSIMC2.TheSIMAregister is the locationwhere the7-bitslaveaddressof theslavedevice isstored.Bits7~1of theSIMAregisterdefine thedeviceslaveaddress.Bit0 isnotdefined.Whenamasterdevice,which isconnected to the I2Cbus, sendsoutanaddress,whichmatchestheslaveaddressintheSIMAregister,theslavedevicewillbeselected.NotethattheSIMAregisteristhesameregisteraddressasSIMC2whichisusedbytheSPIinterface.

Bit0 UndefinedbitThisbitcanbereadorwrittenbyusersoftwareprogram.

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I2C Block Diagram

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

I2C Bus CommunicationCommunicationontheI2Cbusrequiresfourseparatesteps,aSTARTsignal,aslavedeviceaddresstransmission,adatatransmissionandfinallyaSTOPsignal.WhenaSTARTsignal isplacedontheI2Cbus,alldevicesonthebuswillreceivethissignalandbenotifiedoftheimminentarrivalofdataonthebus.ThefirstsevenbitsofthedatawillbetheslaveaddresswiththefirstbitbeingtheMSB.Iftheaddressoftheslavedevicematchesthatofthetransmittedaddress,theHAASbitintheSIMC1registerwillbesetandanI2Cinterruptwillbegenerated.Afterenteringtheinterruptserviceroutine,theslavedevicemustfirstchecktheconditionoftheHAASbittodeterminewhethertheinterruptsourceoriginatesfromanaddressmatchorfromthecompletionofan8-bitdatatransfer.Duringadatatransfer,notethatafterthe7-bitslaveaddresshasbeentransmitted,thefollowingbit,whichisthe8thbit,istheread/writebitwhosevaluewillbeplacedintheSRWbit.Thisbitwillbecheckedbytheslavedevicetodeterminewhethertogointotransmitorreceivemode.BeforeanytransferofdatatoorfromtheI2Cbus,themicrocontrollermustinitializethebus,thefollowingarestepstoachievethis:

Step 1SettheSIM2~SIM0andSIMENbitsintheSIMC0registerto“110”and“1”toenabletheI2Cbus.

Step 2WritetheslaveaddressofthedevicetotheI2CbusaddressregisterSIMA.

Step 3SettheSIMEbitoftheinterruptcontrolregistertoenabletheSIMinterrupt.

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I2C Bus Initialisation Flow Chart

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

I2C Bus Start SignalTheSTARTsignalcanonlybegeneratedbythemasterdeviceconnectedtotheI2Cbusandnotbytheslavedevice.ThisSTARTsignalwillbedetectedbyalldevicesconnectedtotheI2Cbus.Whendetected, this indicates that theI2Cbus isbusyandtherefore theHBBbitwillbeset.ASTARTconditionoccurswhenahigh to lowtransitionon theSDAline takesplacewhentheSCLlineremainshigh.

Slave AddressThetransmissionofaSTARTsignalbythemasterwillbedetectedbyalldevicesontheI2Cbus.Todeterminewhichslavedevicethemasterwishestocommunicatewith,theaddressoftheslavedevicewillbesentoutimmediatelyfollowingtheSTARTsignal.Allslavedevices,afterreceivingthis7-bitaddressdata,willcompareitwiththeirown7-bitslaveaddress.Iftheaddresssentoutbythemastermatchestheinternaladdressofthemicrocontrollerslavedevice,thenaninternalI2Cbusinterruptsignalwillbegenerated.Thenextbitfollowingtheaddress,whichisthe8thbit,definestheread/writestatusandwillbesavedtotheSRWbitoftheSIMC1register.Theslavedevicewillthentransmitanacknowledgebit,whichisalowlevel,asthe9thbit.TheslavedevicewillalsosetthestatusflagHAASwhentheaddressesmatch.

Asan I2Cbus interrupt cancome from two sources,when theprogramenters the interruptsubroutine,theHAASbitshouldbeexaminedtoseewhethertheinterruptsourcehascomefromamatchingslaveaddressorfromthecompletionofadatabytetransfer.Whenaslaveaddressismatched, thedevicemustbeplacedineither thetransmitmodeandthenwritedatatotheSIMDregister,orinthereceivemodewhereitmustimplementadummyreadfromtheSIMDregistertoreleasetheSCLline.

I2C Bus Read/Write SignalTheSRWbitintheSIMC1registerdefineswhethertheslavedevicewishestoreaddatafromtheI2CbusorwritedatatotheI2Cbus.Theslavedeviceshouldexaminethisbittodetermineifitistobeatransmitterorareceiver.IftheSRWflagis“1”thenthisindicatesthatthemasterdevicewishestoreaddatafromtheI2Cbus,thereforetheslavedevicemustbesetuptosenddatatotheI2Cbusasatransmitter.IftheSRWflagis“0”thenthisindicatesthatthemasterwishestosenddatatotheI2Cbus,thereforetheslavedevicemustbesetuptoreaddatafromtheI2Cbusasareceiver.

I2C Bus Slave Address Acknowledge SignalAfter themasterhas transmitted a calling address, any slavedeviceon the I2Cbus,whoseown internaladdressmatches thecallingaddress,mustgenerateanacknowledgesignal.Theacknowledgesignalwillinformthemasterthataslavedevicehasaccepteditscallingaddress.IfnoacknowledgesignalisreceivedbythemasterthenaSTOPsignalmustbetransmittedbythemastertoendthecommunication.WhentheHAASflagishigh,theaddresseshavematchedandtheslavedevicemustchecktheSRWflagtodetermineifitistobeatransmitterorareceiver.IftheSRWflagishigh,theslavedeviceshouldbesetuptobeatransmittersotheHTXbitintheSIMC1registershouldbesetto“1”.IftheSRWflagislow,thenthemicrocontrollerslavedeviceshouldbesetupasareceiverandtheHTXbitintheSIMC1registershouldbesetto“0”.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

I2C Bus Data and Acknowledge SignalThe transmitteddata is8-bitswideand is transmittedafter theslavedevicehasacknowledgedreceiptofitsslaveaddress.TheorderofserialbittransmissionistheMSBfirstandtheLSBlast.Afterreceiptof8-bitsofdata,thereceivermusttransmitanacknowledgesignal,level“0”,beforeitcanreceivethenextdatabyte.Iftheslavetransmitterdoesnotreceiveanacknowledgebitsignalfromthemasterreceiver, thentheslavetransmitterwillreleasetheSDAlinetoallowthemastertosendaSTOPsignaltoreleasetheI2CBus.ThecorrespondingdatawillbestoredintheSIMDregister.Ifsetupasatransmitter,theslavedevicemustfirstwritethedatatobetransmittedintotheSIMDregister.Ifsetupasareceiver,theslavedevicemustreadthetransmitteddatafromtheSIMDregister.

Whentheslavereceiver receives thedatabyte, itmustgenerateanacknowledgebit,knownasTXAK,onthe9thclock.Theslavedevice,whichissetupasatransmitterwillchecktheRXAKbitintheSIMC1registertodetermineifit istosendanotherdatabyte,ifnotthenitwillreleasetheSDAlineandawaitthereceiptofaSTOPsignalfromthemaster.

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Note:*Whenaslaveaddressismatched,thedevicesmustbeplacedineitherthetransmitmodeandthenwritedatatotheSIMDregister,orinthereceivemodewhereitmustimplementadummyreadfromtheSIMDregistertoreleasetheSCLline.

I2C Communication Timing Diagram

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

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I2C Bus ISR Flow Chart

I2C Time-out ControlInordertoreducetheI2Clockupproblemduetoreceptionoferroneousclocksources,atime-outfunctionisprovided.IftheclocksourceconnectedtotheI2Cbusisnotreceivedforawhile,thentheI2Ccircuitryandregisterswillberesetafteracertaintime-outperiod.Thetime-outcounterstartstocountonanI2Cbus“START”&“addressmatch”condition,andisclearedbyanSCLfallingedge.BeforethenextSCLfallingedgearrives,ifthetimeelapsedisgreaterthanthetime-outperiodspecifiedbytheSIMTOCregister,thenatime-outconditionwilloccur.Thetime-outfunctionwillstopwhenanI2C“STOP”conditionoccurs.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

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� � � � � � � � � �� � � � � � � � � � ��

� � � � � � �� �

� � �� � � � �

� � � � �

� � � �� � �

� � � � � � � � � � �

I2C Time-out

WhenanI2Ctime-outcounteroverflowoccurs, thecounterwillstopandtheSIMTOENbitwillbeclearedtozeroandtheSIMTOFbitwillbesethightoindicate thata time-outconditionhasoccurred.Thetime-outconditionwillalsogenerateaninterruptwhichusestheI2Cinterrruptvector.WhenanI2Ctime-outoccurs,theI2Cinternalcircuitrywillberesetandtheregisterswillberesetintothefollowingcondition:

Register After I2C Time-outSIMD� SIMA� SIMC� �o changeSIMC1 Reset to POR condition

I2C Registers after Time-out

TheSIMTOFflagcanbeclearedbytheapplicationprogram.Thereare64time-outperiodselectionswhichcanbeselectedusingtheSIMTOSbits in theSIMTOCregister.Thetime-outduration iscalculatedbytheformula:((1~64)×(32/fSUB)).Thisgivesa time-outperiodwhichrangesfromabout1msto64ms.

SIMTOC Register

Bit 7 6 5 4 3 2 1 0�a�e SIMTOE� SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7 SIMTOEN:I2CTime-outControl0:Disable1:Enable

Bit6 SIMTOF:I2CTime-outflag0:Notime-outoccurred1:Time-outoccurred

Bit5~0 SIMTOS5~SIMTOS0:I2CTime-outTimeSelectionI2CTime-outclocksourceisfSUB/32I2CTime-outtimeisgivenby:(SIMTOS[5:0]+1)×(32/fSUB)

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

UART Module Serial InterfaceThedevicecontainsanintegratedfull-duplexasynchronousserialcommunicationsUARTinterfacethatenablescommunicationwithexternaldevicesthatcontainaserialinterface.TheUARTfunctionhasmanyfeaturesandcantransmitandreceivedataseriallybytransferringaframeofdatawitheightorninedatabitsper transmissionaswellasbeingable todetecterrorswhen thedata isoverwrittenorincorrectlyframed.TheUARTfunctionpossessesitsowninternal interruptwhichcanbeusedtoindicatewhenareceptionoccursorwhenatransmissionterminates.

TheintegratedUARTfunctioncontainsthefollowingfeatures:

• Full-duplex,UniversalAsynchronousReceiverandTransmitter(UART)communication

• 8or9bitscharacterlength

• Even,oddornoparityoptions

• Oneortwostopbits

• Baudrategeneratorwith8-bitprescaler

• Parity,framing,noiseandoverrunerrordetection

• Supportforinterruptonaddressdetect(lastcharacterbit=1)

• Transmitterandreceiverenabledindependently

• 2-byteDeepFIFOReceiveDataBuffer

• Transmitandreceiveinterrupts

• TransmitandReceiveMultipleInterruptGenerationSources:♦ TransmitterEmpty♦ TransmitterIdle♦ ReceiverFull♦ ReceiverOverrun♦ AddressModeDetect♦ RXpinWake-up

UART External InterfaceTocommunicatewithanexternalserialinterface,theinternalUARThastwoexternalpinsknownasTXandRX.TheTXpinistheUARTtransmitterpin,whichcanbeusedasageneralpurposeI/Oorotherpin-sharedfunctionalpinifthepinisnotconfiguredasaUARTtransmitter,whichoccurswhentheTXENbitintheUCR2controlregisterisequaltozero.Similarly,theRXpinistheUARTreceiverpin,whichcanalsobeusedasageneralpurposeI/Oorotherpin-sharedfunctionalpin,ifthepinisnotconfiguredasareceiver,whichoccursiftheRXENbitintheUCR2registerisequaltozero.AlongwiththeUARTENbit,theTXENandRXENbits,ifset,willautomaticallysetuptheseI/Oorotherpin-sharedfunctionalpinstotheirrespectiveTXoutputandRXinputconditionsanddisableanypull-highresistoroptionwhichmayexistontheRXpin.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

UART Data Transfer SchemeTheblockdiagramshowstheoveralldatatransferstructurearrangementfortheUART.Theactualdata tobe transmittedfromtheMCUis first transferred to theTXRregisterby theapplicationprogram.Thedatawill thenbe transferredto theTransmitShiftRegisterfromwhere itwillbeshiftedout,LSBfirst,ontotheTXpinataratecontrolledbytheBaudRateGenerator.OnlytheTXRregisterismappedontotheMCUDataMemory,theTransmitShiftRegisterisnotmappedandisthereforeinaccessibletotheapplicationprogram.

DatatobereceivedbytheUARTisacceptedontheexternalRXpin,fromwhereit isshiftedin,LSBfirst, to theReceiverShiftRegisterataratecontrolledbytheBaudRateGenerator.Whentheshiftregisterisfull,thedatawillthenbetransferredfromtheshiftregistertotheinternalRXRregister,whereit isbufferedandcanbemanipulatedbytheapplicationprogram.OnlytheRXRregisterismappedontotheMCUDataMemory,theReceiverShiftRegisterisnotmappedandisthereforeinaccessibletotheapplicationprogram.

Itshouldbenotedthattheactualregisterfordatatransmissionandreception,althoughreferredtointhetext,andinapplicationprograms,asseparateTXRandRXRregisters,onlyexistsasasinglesharedregisterintheDataMemory.ThissharedregisterknownastheTXR/RXRregisterisusedforbothdatatransmissionanddatareception.

MSB LSB…………………………

T�ans�itte� Shift Registe�MSB LSB…………………………

Receive� Shift Registe�TX Pin RX Pin

Baud Rate Gene�ato�

TXR Registe� Buffe�

MCU Data Bus

RXR Registe�

CLK CLK

UART Data Transfer Scheme

UART Status and Control RegistersTherearefivecontrolregistersassociatedwiththeUARTfunction.TheUSR,UCR1andUCR2registerscontroltheoverallfunctionoftheUART,whiletheBRGregistercontrolstheBaudrate.TheactualdatatobetransmittedandreceivedontheserialinterfaceismanagedthroughtheTXR/RXRdataregisters.

RegisterName

Bit

7 6 5 4 3 2 1 0USR PERR �F FERR OERR RIDLE RXIF TIDLE TXIF

UCR1 UARTE� B�O PRE� PRT STOPS TXBRK RX8 TX8UCR2 TXE� RXE� BRGH ADDE� WAKE RIE TIIE TEIE

TXR/RXR TXRX� TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX�BRG BRG� BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG�

UART Register Summary

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

USR registerTheUSRregisteristhestatusregisterfortheUART,whichcanbereadbytheprogramtodeterminethepresentstatusoftheUART.AllflagswithintheUSRregisterarereadonly.Furtherexplanationoneachoftheflagsisgivenbelow:

Bit 7 6 5 4 3 2 1 0�a�e PERR �F FERR OERR RIDLE RXIF TIDLE TXIFR/W R R R R R R R RPOR � � � � 1 � 1 1

Bit7 PERR:Parityerrorflag0:Noparityerrorisdetected1:Parityerrorisdetected

ThePERRflagistheparityerrorflag.Whenthisreadonlyflagis“0”,itindicatesaparityerrorhasnotbeendetected.Whentheflagis“1”,itindicatesthattheparityofthereceivedwordisincorrect.ThiserrorflagisapplicableonlyifParitymode(oddoreven)isselected.TheflagcanalsobeclearedbyasoftwaresequencewhichinvolvesareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdataregister.

Bit6 NF:Noiseflag0:Nonoiseisdetected1:Noiseisdetected

TheNFflagis thenoiseflag.Whenthisreadonlyflagis"0", it indicatesnonoisecondition.Whentheflagis"1",itindicatesthattheUARThasdetectednoiseonthereceiverinput.TheNFflagissetduringthesamecycleastheRXIFflagbutwillnotbesetinthecaseofasoverrun.TheNFflagcanbeclearedbyasoftwaresequencewhichwillinvolveareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdataregister.

Bit5 FERR:Framingerrorflag0:Noframingerrorisdetected1:Framingerrorisdetected

TheFERRflagistheframingerrorflag.Whenthisreadonlyflagis“0”,itindicatesthat thereisnoframingerror.Whentheflagis“1”, it indicates thataframingerrorhasbeendetectedforthecurrentcharacter.TheflagcanalsobeclearedbyasoftwaresequencewhichwillinvolveareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdataregister.

Bit4 OERR:Overrunerrorflag0:Nooverrunerrorisdetected1:Overrunerrorisdetected

TheOERRflagistheoverrunerrorflagwhichindicateswhenthereceiverbufferhasoverflowed.Whenthisreadonlyflagis“0”,itindicatesthatthereisnooverrunerror.Whentheflagis“1”,itindicatesthatanoverrunerroroccurswhichwillinhibitfurthertransferstotheRXRreceivedataregister.Theflagisclearedbyasoftwaresequence,which isa read to thestatusregisterUSRfollowedbyanaccess to theRXRdataregister.

Bit3 RIDLE:Receiverstatus0:Datareceptionisinprogress(databeingreceived)1:Nodatareceptionisinprogress(receiverisidle)

TheRIDLEflagisthereceiverstatusflag.Whenthisreadonlyflagis“0”,itindicatesthatthereceiverisbetweentheinitialdetectionofthestartbitandthecompletionofthestopbit.Whentheflagis“1”, it indicates that thereceiver is idle.Betweenthecompletionofthestopbitandthedetectionofthenextstartbit,theRIDLEbitis“1”indicatingthattheUARTreceiverisidleandtheRXpinstaysinlogichighcondition.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Bit2 RXIF:ReceiveRXRdataregisterstatus0:RXRdataregisterisempty1:RXRdataregisterhasavailabledata

TheRXIFflagisthereceivedataregisterstatusflag.Whenthisreadonlyflagis“0”,itindicatesthattheRXRreaddataregisterisempty.Whentheflagis“1”,itindicatesthat theRXRreaddataregistercontainsnewdata.When thecontentsof theshiftregisteraretransferredtotheRXRregister,aninterruptisgeneratedifRIE=1intheUCR2register.Ifoneormoreerrorsaredetectedinthereceivedword,theappropriatereceive-relatedflagsNF,FERR,and/orPERRaresetwithinthesameclockcycle.TheRXIFflagisclearedwhentheUSRregisterisreadwithRXIFset,followedbyareadfromtheRXRregister,andiftheRXRregisterhasnodataavailable.

Bit1 TIDLE:Transmissionidle0:Datatransmissionisinprogress(databeingtransmitted)1:Nodatatransmissionisinprogress(transmitterisidle)

TheTIDLEflag isknownas the transmissioncompleteflag.Whenthis readonlyflagis“0”,it indicatesthatatransmissionisinprogress.Thisflagwillbesetto“1”whentheTXIFflagis“1”andwhenthereisnotransmitdataorbreakcharacterbeingtransmitted.WhenTIDLEisequalto“1”,theTXpinbecomesidlewiththepinstateinlogichighcondition.TheTIDLEflagisclearedbyreadingtheUSRregisterwithTIDLEsetandthenwritingtotheTXRregister.Theflagisnotgeneratedwhenadatacharacterorabreakisqueuedandreadytobesent.

Bit0 TXIF:TransmitTXRdataregisterstatus0:Characterisnottransferredtothetransmitshiftregister1:Characterhas transferred to the transmit shift register (TXRdata register is

empty)TheTXIFflagisthetransmitdataregisteremptyflag.Whenthisreadonlyflagis“0”,itindicatesthatthecharacterisnottransferredtothetransmittershiftregister.Whentheflagis“1”,it indicatesthatthetransmittershiftregisterhasreceivedacharacterfromtheTXRdataregister.TheTXIFflag isclearedbyreadingtheUARTstatusregister(USR)withTXIFsetandthenwriting to theTXRdataregister.Note thatwhentheTXENbit isset, theTXIFflagbitwillalsobesetsincethetransmitdataregisterisnotyetfull.

UCR1 registerTheUCR1registertogetherwiththeUCR2registerarethetwoUARTcontrolregistersthatareusedtosetthevariousoptionsfortheUARTfunction,suchasoverallon/offcontrol,paritycontrol,datatransferbitlengthetc.Furtherexplanationoneachofthebitsisgivenbelow:

Bit 7 6 5 4 3 2 1 0�a�e UARTE� B�O PRE� PRT STOPS TXBRK RX8 TX8R/W R/W R/W R/W R/W R/W R/W R WPOR � � � � � � x �

“x” unknownBit7 UARTEN:UARTfunctionenablecontrol

0:DisableUART.TXandRXpinsareasI/Oorotherpin-sharedfunctionalpins1:EnableUART.TXandRXpinsfunctionasUARTpins

TheUARTENbit is theUARTenablebit.Whenthisbit isequalto“0”,theUARTwillbedisabledandtheRXpinaswellastheTXpinwillbeasGeneralPurposeI/Oorotherpin-sharedfunctionalpins.Whenthebit isequalto“1”, theUARTwillbeenabledandtheTXandRXpinswillfunctionasdefinedbytheTXENandRXENenablecontrolbits.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

WhentheUARTisdisabled, itwillemptythebuffersoanycharacterremaininginthebufferwillbediscarded.Inaddition, thevalueof thebaudratecounterwillbereset.IftheUARTisdisabled,allerrorandstatusflagswillbereset.AlsotheTXEN,RXEN,TXBRK,RXIF,OERR,FERR,PERRandNFbitswillbecleared,whiletheTIDLE,TXIFandRIDLEbitswillbeset.Othercontrolbits inUCR1,UCR2andBRGregisterswillremainunaffected.IftheUARTisactiveandtheUARTENbitiscleared,allpendingtransmissionsandreceptionswillbeterminatedandthemodulewillberesetasdefinedabove.WhentheUARTisre-enabled, itwill restart in thesameconfiguration.

Bit6 BNO:Numberofdatatransferbitsselection0:8-bitdatatransfer1:9-bitdatatransfer

Thisbit isusedtoselect thedata lengthformat,whichcanhaveachoiceofeither8-bitor9-bitformat.Whenthisbitisequalto“1”,a9-bitdatalengthformatwillbeselected.Ifthebitisequalto“0”,thenan8-bitdatalengthformatwillbeselected.If9-bitdatalengthformatisselected,thenbitsRX8andTX8willbeusedtostorethe9thbitofthereceivedandtransmitteddatarespectively.

Bit5 PREN:Parityfunctionenablecontrol0:Parityfunctionisdisabled1:Parityfunctionisenabled

Thisistheparityenablebit.Whenthisbitisequalto“1”,theparityfunctionwillbeenabled.Ifthebitisequalto“0”,thentheparityfunctionwillbedisabled.Replacethemostsignificantbitpositionwithaparitybit.

Bit4 PRT:Paritytypeselectionbit0:Evenparityforparitygenerator1:Oddparityforparitygenerator

Thisbitistheparitytypeselectionbit.Whenthisbitisequalto“1”,oddparitytypewillbeselected.Ifthebitisequalto“0”,thenevenparitytypewillbeselected.

Bit3 STOPS:NumberofStopbitsselection0:Onestopbitformatisused1:Twostopbitsformatisused

Thisbitdeterminesifoneortwostopbitsaretobeused.Whenthisbitisequalto“1”,twostopbitsareused.Ifthisbitisequalto“0”,thenonlyonestopbitisused.

Bit2 TXBRK:Transmitbreakcharacter0:Nobreakcharacteristransmitted1:Breakcharacterstransmit

TheTXBRKbit is theTransmitBreakCharacterbit.Whenthisbit is“0”, therearenobreakcharactersandtheTXpinoperatesnormally.Whenthebitis“1”,therearetransmitbreakcharactersandthetransmitterwillsendlogiczeros.Whenthisbit isequalto“1”,afterthebuffereddatahasbeentransmitted,thetransmitteroutputisheldlowforaminimumofa13-bitlengthanduntiltheTXBRKbitisreset.

Bit1 RX8:Receivedatabit8for9-bitdatatransferformat(readonly)Thisbitisonlyusedif9-bitdatatransfersareused,inwhichcasethisbitlocationwillstorethe9thbitofthereceiveddataknownasRX8.TheBNObitisusedtodeterminewhetherdatatransfersarein8-bitor9-bitformat.

Bit0 TX8:Transmitdatabit8for9-bitdatatransferformat(writeonly)Thisbit isonlyusedif9-bitdata transfersareused, inwhichcasethisbit locationwillstorethe9thbitof thetransmitteddataknownasTX8.TheBNObit isusedtodeterminewhetherdatatransfersarein8-bitor9-bitformat.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

UCR2 registerTheUCR2registeristhesecondofthetwoUARTcontrolregistersandservesseveralpurposes.Oneofitsmainfunctionsistocontrolthebasicenable/disableoperationoftheUARTTransmitterandReceiveraswellasenablingthevariousUARTinterruptsources.Theregisteralsoservestocontrolthebaudratespeed,receiverwake-upenableandtheaddressdetectenable.Furtherexplanationoneachofthebitsisgivenbelow:

Bit 7 6 5 4 3 2 1 0�a�e TXE� RXE� BRGH ADDE� WAKE RIE TIIE TEIER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7 TXEN:UARTTransmitterenabledcontrol0:UARTtransmitterisdisabled1:UARTtransmitterisenabled

ThebitnamedTXENistheTransmitterEnableBit.Whenthisbitisequalto“0”,thetransmitterwillbedisabledwithanypendingdata transmissionsbeingaborted. Inadditionthebufferswillbereset.InthissituationtheTXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.If theTXENbit is equal to “1”and theUARTENbit is also equal to “1”, thetransmitterwillbeenabledandtheTXpinwillbecontrolledbytheUART.ClearingtheTXENbitduringatransmissionwillcausethedatatransmissiontobeabortedandwillresetthetransmitter.Ifthissituationoccurs,theTXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.

Bit6 RXEN:UARTReceiverenabledcontrol0:UARTreceiverisdisabled1:UARTreceiverisenabled

ThebitnamedRXENistheReceiverEnableBit.Whenthisbit isequalto“0”,thereceiverwillbedisabledwithanypendingdatareceptionsbeingaborted.Inadditionthereceivebufferswillbereset.InthissituationtheRXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.IftheRXENbitisequalto“1”andtheUARTENbitisalsoequalto“1”,thereceiverwillbeenabledandtheRXpinwillbecontrolledbytheUART.ClearingtheRXENbitduringareceptionwillcausethedatareceptiontobeabortedandwillresetthereceiver.Ifthissituationoccurs,theRXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.

Bit5 BRGH:BaudRatespeedselection0:Lowspeedbaudrate1:Highspeedbaudrate

ThebitnamedBRGHselectsthehighorlowspeedmodeoftheBaudRateGenerator.Thisbit, togetherwith thevalueplacedinthebaudrateregisterBRG,controls theBaudRateoftheUART.Ifthisbitisequalto“1”,thehighspeedmodeisselected.Ifthebitisequalto“0”,thelowspeedmodeisselected.

Bit4 ADDEN:Addressdetectfunctionenablecontrol0:Addressdetectfunctionisdisabled1:Addressdetectfunctionisenabled

ThebitnamedADDENistheaddressdetectfunctionenablecontrolbit.Whenthisbit isequal to“1”, theaddressdetectfunctionisenabled.Whenitoccurs, if the8thbit,whichcorrespondstoRX7ifBNO=0orthe9thbit,whichcorrespondstoRX8ifBNO=1,hasavalueof“1”,thenthereceivedwordwillbeidentifiedasanaddress,ratherthandata.Ifthecorrespondinginterruptisenabled,aninterruptrequestwillbegeneratedeachtimethereceivedwordhastheaddressbitset,whichisthe8thor9thbitdependingonthevalueofBNO.Iftheaddressbitknownasthe8thor9thbitofthereceivedwordis“0”withtheaddressdetectfunctionbeingenabled,aninterruptwillnotbegeneratedandthereceiveddatawillbediscarded.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Bit3 WAKE:RXpinfallingedgewake-upfunctionenablecontrol0:RXpinwake-upfunctionisdisabled1:RXpinwake-upfunctionisenabled

Thisbitenablesordisablesthereceiverwake-upfunction.Ifthisbit isequalto“1”andtheMCUis inIDLEorSLEEPmode,afallingedgeontheRXinputpinwillwake-upthedevice.PleasereferencetheUARTRXpinwake-upfunctionsindifferentoperatingmodeforthedetail.If thisbit isequalto“0”andtheMCUisinIDLEorSLEEPmode,anyedgetransitionsontheRXpinwillnotwake-upthedevice.

Bit2 RIE:Receiverinterruptenablecontrol0:Receiverrelatedinterruptisdisabled1:Receiverrelatedinterruptisenabled

Thisbitenablesordisablesthereceiverinterrupt.Ifthisbitisequalto“1”andwhenthereceiveroverrunflagOERRorreceivedataavailableflagRXIFisset,theUARTinterruptrequestflagwillbeset.Ifthisbitisequalto“0”,theUARTinterruptrequestflagwillnotbeinfluencedbytheconditionoftheOERRorRXIFflags.

Bit1 TIIE:TransmitterIdleinterruptenablecontrol0:Transmitteridleinterruptisdisabled1:Transmitteridleinterruptisenabled

Thisbitenablesordisablesthetransmitteridleinterrupt.Ifthisbitisequalto“1”andwhenthetransmitter idleflagTIDLEisset,duetoa transmitter idlecondition, theUARTinterruptrequestflagwillbeset.Ifthisbitisequalto“0”,theUARTinterruptrequestflagwillnotbeinfluencedbytheconditionoftheTIDLEflag.

Bit0 TEIE:TransmitterEmptyinterruptenablecontrol0:Transmitteremptyinterruptisdisabled1:Transmitteremptyinterruptisenabled

Thisbitenablesordisablesthetransmitteremptyinterrupt.Ifthisbitisequalto“1”andwhenthetransmitteremptyflagTXIFisset,duetoatransmitteremptycondition,theUARTinterrupt request flagwillbeset. If thisbit isequal to“0”, theUARTinterruptrequestflagwillnotbeinfluencedbytheconditionoftheTXIFflag.

TXR/RXR register

Bit 7 6 5 4 3 2 1 0�a�e TXRX� TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x

“x” unknownBit7~0 TXRX7~TXRX0:UARTTransmit/ReceiveDatabit7~bit0

BRG Register

Bit 7 6 5 4 3 2 1 0�a�e BRG� BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x

“x” unknownBit7~0 BRG7~BRG0:BaudRatevalues

Byprogramming theBRGHbit inUCR2Registerwhichallowsselectionof therelatedformuladescribedaboveandprogramming therequiredvalue in theBRGregister,therequiredbaudratecanbesetup.Note:Baudrate=fSYS/[64×(N+1)]ifBRGH=0.

Baudrate=fSYS/[16×(N+1)]ifBRGH=1.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Baud Rate GeneratorTosetupthespeedoftheserialdatacommunication,theUARTfunctioncontainsitsowndedicatedbaudrategenerator.Thebaudrate iscontrolledbyitsowninternalfreerunning8-bit timer, theperiodofwhichisdeterminedbytwofactors.ThefirstoftheseisthevalueplacedinthebaudrateregisterBRGandthesecondis thevalueof theBRGHbitwith thecontrolregisterUCR2.TheBRGHbitdecidesifthebaudrategeneratoristobeusedinahighspeedmodeorlowspeedmode,whichinturndeterminestheformulathatisusedtocalculatethebaudrate.ThevalueNintheBRGregisterwhichisusedinthefollowingbaudratecalculationformuladeterminesthedivisionfactor.NotethatNisthedecimalvalueplacedintheBRGregisterandhasarangeofbetween0and255.

UCR2 BRGH Bit 0 1Baud Rate (BR) fSYS /[64 (�+1)] fSYS /[16 (�+1)]

ByprogrammingtheBRGHbitwhichallowsselectionoftherelatedformulaandprogrammingtherequiredvalueintheBRGregister,therequiredbaudratecanbesetup.Notethatbecausetheactualbaudrateisdeterminedusingadiscretevalue,N,placedintheBRGregister,therewillbeanerrorassociatedbetweentheactualandrequestedvalue.ThefollowingexampleshowshowtheBRGregistervalueNandtheerrorvaluecanbecalculated.

Calculating the register and error valuesForaclockfrequencyof4MHz,andwithBRGHsetto“0”determinetheBRGregistervalueN,theactualbaudrateandtheerrorvalueforadesiredbaudrateof4800.

FromtheabovetablethedesiredbaudrateBR=fSYS/[64(N+1)]

Re-arrangingthisequationgivesN=[fSYS/(BR×64)]-1

GivingavalueforN=[4000000/(4800×64)]-1=12.0208

Toobtaintheclosestvalue,adecimalvalueof12shouldbeplacedintotheBRGregister.ThisgivesanactualorcalculatedbaudratevalueofBR=4000000/[64×(12+1)]=4808

Thereforetheerrorisequalto(4808-4800)/4800=0.16%

ThefollowingtablesshowactualvaluesofbaudrateanderrorvaluesforthetwovaluesofBRGH.

Baud RateK/BPS

Baud Rates for BRGH=0

fSYS = 16 MHz fSYS = 20 MHz

BRG Kbaud Error (%) BRG Kbaud Error (%)�.3 — — — — — —1.2 2�� 1.2�2 �.16 25� 1.2�2 �.162.4 1�3 2.4�4 �.16 12� 2.4�4 �.164.8 51 4.8�8 �.16 64 4.8�8 �.16�.6 25 �.615 �.16 32 �.4�� -1.36

1�.2 12 1�.231 �.16 15 1�.531 1.�338.4 6 35.�14 -6.�� � 3�.�63 1.�35�.6 3 62.5 8.51 4 62.5 8.51115.2 1 125 8.51 2 1�4.1� -�.5825� � 25� � � 312.5 25

Baud Rates and Error Values for BRGH = 0

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Rev. 1.21 138 �ove��e� ��� 2�1� Rev. 1.21 13� �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Baud RateK/BPS

Baud Rates for BRGH=1

fSYS = 16 MHz fSYS = 20 MHz

BRG Kbaud Error (%) BRG Kbaud Error (%)�.3 — — — — — —1.2 — — — — — —2.4 — — — — — —4.8 2�� 4.8�8 �.16 — — —�.6 1�3 �.615 �.16 12� �.615 �.16

1�.2 51 1�.231 �.16 64 1�.231 �.1638.4 25 38.462 �.16 32 3�.8�� -1.365�.6 16 58.824 2.12 21 56.818 -1.35115.2 8 111.11 -3.55 1� 113.636 -1.3625� 3 25� � 4 25� �

Baud Rates and Error Values for BRGH = 1

UART Setup and ControlFordatatransfer,theUARTfunctionutilizesanon-return-to-zero,morecommonlyknownasNRZ,format.Thisiscomposedofonestartbit,eightorninedatabits,andoneortwostopbits.ParityissupportedbytheUARThardware,andcanbesetuptobeeven,oddornoparity.Forthemostcommondataformat,8databitsalongwithnoparityandonestopbit,denotedas8,N,1,isusedasthedefaultsetting,whichisthesettingatpower-on.Thenumberofdatabitsandstopbits,alongwiththeparity,aresetupbyprogrammingthecorrespondingBNO,PRT,PREN,andSTOPSbitsin theUCR1register.Thebaudrateusedtotransmitandreceivedata issetupusingtheinternal8-bitbaudrategenerator,whilethedataistransmittedandreceivedLSBfirst.AlthoughtheUARTtransmitterandreceiverarefunctionallyindependent,theybothusethesamedataformatandbaudrate.Inallcasesstopbitswillbeusedfordatatransmission.

Enabling/disabling the UARTThebasicon/offfunctionoftheinternalUARTfunctioniscontrolledusingtheUARTENbitintheUCR1register.IftheUARTEN,TXENandRXENbitsareset,thenthesetwoUARTpinswillactasnormalTXoutputpinandRXinputpinrespectively.IfnodataisbeingtransmittedontheTXpin,thenitwilldefaulttoalogichighvalue.

ClearingtheUARTENbitwilldisabletheTXandRXpinsandallowthesetwopinstobeusedasnormalI/Oorotherpin-sharedfunctionalpins.WhentheUARTfunctionisdisabledthebufferwillberesettoanemptycondition,atthesametimediscardinganyremainingresidualdata.DisablingtheUARTwillalsoresettheerrorandstatusflagswithbitsTXEN,RXEN,TXBRK,RXIF,OERR,FERR,PERRandNFbeingclearedwhilebitsTIDLE,TXIFandRIDLEwillbeset.TheremainingcontrolbitsintheUCR1,UCR2andBRGregisterswillremainunaffected.IftheUARTENbitintheUCR1registerisclearedwhiletheUARTisactive,thenallpendingtransmissionsandreceptionswillbeimmediatelysuspendedandtheUARTwillberesettoaconditionasdefinedabove.IftheUARTisthensubsequentlyre-enabled,itwillrestartagaininthesameconfiguration.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Data, parity and stop bit selectionTheformatof thedata tobe transferred iscomposedofvariousfactorssuchasdatabit length,parityon/off,paritytype,addressbitsandthenumberofstopbits.ThesefactorsaredeterminedbythesetupofvariousbitswithintheUCR1register.TheBNObitcontrols thenumberofdatabitswhichcanbesettoeither8or9,thePRTbitcontrolsthechoiceofoddorevenparity,thePRENbitcontrolstheparityon/offfunctionandtheSTOPSbitdecideswhetheroneortwostopbitsaretobeused.Thefollowingtableshowsvariousformatsfordatatransmission.Theaddressbitidentifiestheframeasanaddresscharacter.Thenumberofstopbits,whichcanbeeitheroneor two, isindependentofthedatalength.

Start Bit Data Bits Address Bits Parity Bits Stop BitExample of 8-bit Data Formats

1 8 � � 11 � � 1 11 � 1 � 1

Example of 9-bit Data Formats1 � � � 11 8 � 1 11 8 1 � 1

Transmitter Receiver Data Format

Thefollowingdiagramshows the transmitandreceivewaveformsforboth8-bitand9-bitdataformats.

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �

� � �� � � � �� � �

� � � � � � � � �

� � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �

� � �� � � � �� � �

� � � � � � � � �

� � � � � � � � � � � � � � � � �

� � � �

UART transmitterDatawordlengthsofeither8or9bits,canbeselectedbyprogrammingtheBNObitintheUCR1register.WhenBNObitisset, thewordlengthwillbesetto9bits.Inthiscasethe9thbit,whichistheMSB,needstobestoredintheTX8bitintheUCR1register.AtthetransmittercoreliestheTransmitterShiftRegister,morecommonlyknownas theTSR,whosedata isobtainedfromthetransmitdataregister,whichisknownas theTXRregister.Thedata tobe transmittedis loadedintothisTXRregisterbytheapplicationprogram.TheTSRregisterisnotwrittentowithnewdatauntilthestopbitfromtheprevioustransmissionhasbeensentout.Assoonasthisstopbithasbeentransmitted,theTSRcanthenbeloadedwithnewdatafromtheTXRregister, ifit isavailable.ItshouldbenotedthattheTSRregister,unlikemanyotherregisters, isnotdirectlymappedintotheDataMemoryareaandassuch isnotavailable to theapplicationprogramfordirect read/writeoperations.AnactualtransmissionofdatawillnormallybeenabledwhentheTXENbitisset,butthedatawillnotbetransmitteduntiltheTXRregisterhasbeenloadedwithdataandthebaudrategeneratorhasdefinedashiftclocksource.However,thetransmissioncanalsobeinitiatedbyfirstloadingdataintotheTXRregister,afterwhichtheTXENbitcanbeset.Whenatransmissionofdatabegins,theTSRisnormallyempty,inwhichcaseatransfertotheTXRregisterwillresultinanimmediatetransfertotheTSR.IfduringatransmissiontheTXENbitiscleared,thetransmissionwillimmediatelyceaseandthetransmitterwillbereset.TheTXoutputpinwillthenreturntotheI/Oorotherpin-sharedfunction.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Transmitting dataWhentheUARTistransmittingdata,thedataisshiftedontheTXpinfromtheshiftregister,withthe leastsignificantbit first. In the transmitmode, theTXRregisterformsabufferbetweentheinternalbusandthetransmittershiftregister.Itshouldbenotedthatif9-bitdataformathasbeenselected,thentheMSBwillbetakenfromtheTX8bitintheUCR1register.Thestepstoinitiateadatatransfercanbesummarizedasfollows:

• MakethecorrectselectionoftheBNO,PRT,PRENandSTOPSbitstodefinetherequiredwordlength,paritytypeandnumberofstopbits.

• SetuptheBRGregistertoselectthedesiredbaudrate.

• SettheTXENbittoensurethattheTXpinisusedasaUARTtransmitterpin.

• AccesstheUSRregisterandwritethedatathatistobetransmittedintotheTXRregister.NotethatthisstepwillcleartheTXIFbit.

• Thissequenceofeventscannowberepeatedtosendadditionaldata.

ItshouldbenotedthatwhenTXIF=0,datawillbeinhibitedfrombeingwrittentotheTXRregister.ClearingtheTXIFflagisalwaysachievedusingthefollowingsoftwaresequence:

1.AUSRregisteraccess

2.ATXRregisterwriteexecution

Theread-onlyTXIFflagissetbytheUARThardwareandifsetindicatesthattheTXRregisterisemptyandthatotherdatacannowbewrittenintotheTXRregisterwithoutoverwritingthepreviousdata.IftheTEIEbitissetthentheTXIFflagwillgenerateaninterrupt.

Duringadatatransmission,awriteinstructiontotheTXRregisterwillplacethedataintotheTXRregister,whichwillbecopiedtotheshiftregisterattheendofthepresenttransmission.Whenthereisnodatatransmissioninprogress,awriteinstructiontotheTXRregisterwillplacethedatadirectlyintotheshiftregister,resultinginthecommencementofdatatransmission,andtheTXIFbitbeingimmediatelyset.Whenaframetransmissioniscomplete,whichhappensafterstopbitsaresentorafterthebreakframe,theTIDLEbitwillbeset.TocleartheTIDLEbitthefollowingsoftwaresequenceisused:

1.AUSRregisteraccess

2.ATXRregisterwriteexecution

NotethatboththeTXIFandTIDLEbitsareclearedbythesamesoftwaresequence.

Transmit breakIftheTXBRKbitissetthenbreakcharacterswillbesentonthenexttransmission.Breakcharactertransmissionconsistsofastartbit,followedby13×N‘0’bitsandstopbits,whereN=1,2,etc.IfabreakcharacteristobetransmittedthentheTXBRKbitmustbefirstsetbytheapplicationprogram,thenclearedtogeneratethestopbits.Transmittingabreakcharacterwillnotgenerateatransmitinterrupt.Notethatabreakconditionlengthisatleast13bitslong.IftheTXBRKbitiscontinuallykeptata logichighlevel thenthetransmittercircuitrywill transmitcontinuousbreakcharacters.AftertheapplicationprogramhasclearedtheTXBRKbit,thetransmitterwillfinishtransmittingthelastbreakcharacterandsubsequentlysendoutoneortwostopbits.Theautomaticlogichighsattheendofthelastbreakcharacterwillensurethatthestartbitofthenextframeisrecognized.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

UART receiverTheUARTiscapableofreceivingwordlengthsofeither8or9bits.IftheBNObitisset,thewordlengthwillbesetto9bitswiththeMSBbeingstoredintheRX8bitoftheUCR1register.AtthereceivercoreliestheReceiveSerialShiftRegister,commonlyknownastheRSR.ThedatawhichisreceivedontheRXexternalinputpin,issenttothedatarecoveryblock.Thedatarecoveryblockoperatingspeedis16timesthatofthebaudrate,whilethemainreceiveserialshifteroperatesatthebaudrate.AftertheRXpinissampledforthestopbit,thereceiveddatainRSRistransferredtothereceivedataregister,iftheregisterisempty.ThedatawhichisreceivedontheexternalRXinputpinissampledthreetimesbyamajoritydetectcircuittodeterminethelogiclevelthathasbeenplacedontotheRXpin.ItshouldbenotedthattheRSRregister,unlikemanyotherregisters,isnotdirectlymappedintotheDataMemoryareaandassuchisnotavailabletotheapplicationprogramfordirectread/writeoperations.

Receiving dataWhentheUARTreceiverisreceivingdata,thedataisseriallyshiftedinontheexternalRXinputpin,LSBfirst.Inthereadmode,theRXRregisterformsabufferbetweentheinternalbusandthereceivershiftregister.TheRXRregisterisatwobytedeepFIFOdatabuffer,wheretwobytescanbeheldintheFIFOwhileathirdbytecancontinuetobereceived.Notethattheapplicationprogrammustensure that thedata is read fromRXRbefore the thirdbytehasbeencompletelyshiftedin,otherwise this thirdbytewillbediscardedandanoverrunerrorOERRwillbesubsequentlyindicated.Thestepstoinitiateadatatransfercanbesummarizedasfollows:

• MakethecorrectselectionofBNO,PRT,PRENandSTOPSbitstodefinethewordlength,paritytypeandnumberofstopbits.

• SetuptheBRGregistertoselectthedesiredbaudrate.

• SettheRXENbittoensurethattheRXpinisusedasaUARTreceiverpin.

Atthispointthereceiverwillbeenabledwhichwillbegintolookforastartbit.

Whenacharacterisreceivedthefollowingsequenceofeventswilloccur:

• TheRXIFbitintheUSRregisterwillbesetwhenRXRregisterhasdataavailable,atleastonecharactercanberead.

• WhenthecontentsoftheshiftregisterhavebeentransferredtotheRXRregister,theniftheRIEbitisset,aninterruptwillbegenerated.

• Ifduringreception,aframeerror,noiseerror,parityerror,oranoverrunerrorhasbeendetected,thentheerrorflagscanbeset.

TheRXIFbitcanbeclearedusingthefollowingsoftwaresequence:

1.AUSRregisteraccess

2.AnRXRregisterreadexecution

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Receive breakAnybreakcharacterreceivedbytheUARTwillbemanagedasaframingerror.ThereceiverwillcountandexpectacertainnumberofbittimesasspecifiedbythevaluesprogrammedintotheBNOandSTOPSbits.Ifthebreakismuchlongerthan13bittimes,thereceptionwillbeconsideredascompleteafterthenumberofbittimesspecifiedbyBNOandSTOPS.TheRXIFbitisset,FERRisset,zerosareloadedintothereceivedataregister,interruptsaregeneratedifappropriateandtheRIDLEbitisset.Ifalongbreaksignalhasbeendetectedandthereceiverhasreceivedastartbit,thedatabitsandtheinvalidstopbit,whichsetstheFERRflag,thereceivermustwaitforavalidstopbitbefore lookingfor thenextstartbit.Thereceiverwillnotmaketheassumptionthat thebreakconditiononthelineisthenextstartbit.AbreakisregardedasacharacterthatcontainsonlyzeroswiththeFERRflagset.Thebreakcharacterwillbeloadedintothebufferandnofurtherdatawillbereceiveduntilstopbitsarereceived.ItshouldbenotedthattheRIDLEreadonlyflagwillgohighwhenthestopbitshavenotyetbeenreceived.ThereceptionofabreakcharacterontheUARTregisterswillresultinthefollowing:

• Theframingerrorflag,FERR,willbeset.

• Thereceivedataregister,RXR,willbecleared.

• TheOERR,NF,PERR,RIDLEorRXIFflagswillpossiblybeset.

Idle statusWhenthereceiverisreadingdata,whichmeansitwillbeinbetweenthedetectionofastartbitandthereadingofastopbit,thereceiverstatusflagintheUSRregister,otherwiseknownastheRIDLEflag,willhaveazerovalue.Inbetweenthereceptionofastopbitandthedetectionofthenextstartbit,theRIDLEflagwillhaveahighvalue,whichindicatesthereceiverisinanidlecondition.

Receiver interruptThereadonlyreceiveinterruptflagRXIFintheUSRregister issetbyanedgegeneratedbythereceiver.Aninterrupt isgenerated ifRIE=1,whenawordis transferredfromtheReceiveShiftRegister,RSR,totheReceiveDataRegister,RXR.AnoverrunerrorcanalsogenerateaninterruptifRIE=1.

Managing receiver errorsSeveraltypesofreceptionerrorscanoccurwithintheUARTmodule,thefollowingsectiondescribesthevarioustypesandhowtheyaremanagedbytheUART.

Overrun Error – OERR flagTheRXRregisteriscomposedofatwobytedeepFIFOdatabuffer,wheretwobytescanbeheldintheFIFOregister,whileathirdbytecancontinuetobereceived.Beforethethirdbytehasbeenentirelyshiftedin,thedatashouldbereadfromtheRXRregister.If thisisnotdone,theoverrunerrorflagOERRwillbeconsequentlyindicated.

Intheeventofanoverrunerroroccurring,thefollowingwillhappen:

• TheOERRflagintheUSRregisterwillbeset.

• TheRXRcontentswillnotbelost.

• Theshiftregisterwillbeoverwritten.

• AninterruptwillbegeneratediftheRIEbitisset.

TheOERRflagcanbeclearedbyanaccess to theUSRregisterfollowedbyareadto theRXRregister.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Noise Error – NF FlagOver-sampling isusedfordata recovery to identifyvalid incomingdataandnoise. Ifnoise isdetectedwithinaframethefollowingwilloccur:

• Thereadonlynoiseflag,NF,intheUSRregisterwillbesetontherisingedgeoftheRXIFbit.

• DatawillbetransferredfromtheShiftregistertotheRXRregister.

• Nointerruptwillbegenerated.Howeverthisbitrisesat thesametimeastheRXIFbitwhichitselfgeneratesaninterrupt.

NotethattheNFflagisresetbyaUSRregisterreadoperationfollowedbyanRXRregisterreadoperation.

Framing Error – FERR FlagThereadonlyframingerrorflag,FERR,intheUSRregister,issetifazeroisdetectedinsteadofstopbits.Iftwostopbitsareselected,bothstopbitsmustbehigh,otherwisetheFERRflagwillbeset.TheFERRflagisbufferedalongwiththereceiveddataandisclearedonanyreset.

Parity Error – PERR FlagThereadonlyparityerrorflag,PERR,intheUSRregister,issetiftheparityofthereceivedwordisincorrect.Thiserrorflagisonlyapplicableiftheparityisenabled,PREN=1,andiftheparitytype,oddorevenisselected.ThereadonlyPERRflagisbufferedalongwiththereceiveddatabytes.Itisclearedonanyreset.ItshouldbenotedthattheFERRandPERRflagsarebufferedalongwiththecorrespondingwordandshouldbereadbeforereadingthedataword.

UART Module Interrupt StructureSeveralindividualUARTconditionscangenerateaUARTinterrupt.Whentheseconditionsexist,a lowpulsewillbegeneratedtoget theattentionof themicrocontroller.Theseconditionsareatransmitterdataregisterempty, transmitter idle,receiverdataavailable,receiveroverrun,addressdetectandanRXpinwake-up.Whenanyof theseconditionsarecreated, if itscorrespondinginterruptcontrol isenabledandthestackisnotfull, theprogramwill jumpto itscorrespondinginterruptvectorwhere itcanbeservicedbefore returning to themainprogram.Fourof theseconditionshavethecorrespondingUSRregisterflagswhichwillgenerateaUARTinterruptif itsassociated interruptenablecontrolbit in theUCR2register isset.The twotransmitter interruptconditionshave theirowncorrespondingenablecontrolbits,while the two receiver interruptconditionshaveasharedenablecontrolbit.TheseenablebitscanbeusedtomaskoutindividualUARTinterruptsources.

Theaddressdetectcondition,whichisalsoaUARTinterruptsource,doesnothaveanassociatedflag,butwillgenerateaUARTinterruptwhenanaddressdetectconditionoccurs if itsfunctionisenabledbysettingtheADDENbit in theUCR2register.AnRXpinwake-up,whichisalsoaUARTinterruptsource,doesnothaveanassociatedflag,butwillgenerateaUARTinterruptifthemicrocontrolleriswokenupbyafallingedgeontheRXpin,iftheWAKEandRIEbitsintheUCRregisterareset.NotethatintheeventofanRXwake-upinterruptoccurring,therewillbeacertainperiodofdelay,commonlyknownas theSystemStart-upTime,for theoscillator torestartandstabilizebeforethesystemresumesnormaloperation.

Note that theUSRregister flagsare readonlyandcannotbeclearedorsetby theapplicationprogram,neitherwill theybeclearedwhen theprogramjumps to thecorresponding interruptservicing routine, as is the case for someof theother interrupts.The flagswill be clearedautomaticallywhencertainactionsare takenbytheUART,thedetailsofwhicharegivenintheUARTregistersection.TheoverallUARTinterruptcanbedisabledorenabledby the relatedinterruptenablecontrolbitsintheinterruptcontrolregistersofthemicrocontrollertodecidewhethertheinterruptrequestedbytheUARTmoduleismaskedoutorallowed.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Transmitter EmptyFlag TXIF

USR Register

Transmitter IdleFlag TIDLE

Receiver OverrunFlag OERR

Receiver DataAvailable RXIF

ADDEN

RX PinWake-up

WAKE 01

01

01

RX7 if BNO=0RX8 if BNO=1UCR2 Register

OR RIE 01

TIIE 01

TEIE 01

UART Interrupt Request Flag

UARF

UCR2 Register

To MCU Interrupt Controller

UART Interrupt Scheme

Address detect modeSettingtheAddressDetectModebit,ADDEN,intheUCR2register,enablesthisspecialmode.IfthisbitisenabledthenanadditionalqualifierwillbeplacedonthegenerationofaReceiverDataAvailableinterrupt,whichisrequestedbytheRXIFflag.IftheADDENbitisenabled,thenwhendataisavailable,aninterruptwillonlybegenerated, if thehighestreceivedbithasahighvalue.NotethattheMFE,UREandEMIinterruptenablebitsmustalsobeenabledforcorrect interruptgeneration.Thishighestaddressbitisthe9thbitifBNO=1orthe8thbitifBNO=0.Ifthisbitishigh,thenthereceivedwordwillbedefinedasanaddressratherthandata.ADataAvailableinterruptwillbegeneratedeverytimethelastbitofthereceivedwordisset.IftheADDENbitisnotenabled,thenaReceiverDataAvailableinterruptwillbegeneratedeachtimetheRXIFflagisset,irrespectiveofthedatalastbitstatus.Theaddressdetectmodeandparityenablearemutuallyexclusivefunctions.Thereforeiftheaddressdetectmodeisenabled,thentoensurecorrectoperation,theparityfunctionshouldbedisabledbyresettingtheparityenablebittozero.

ADDEN Bit 9 if BNO=1, Bit 8 if BNO=0 UART Interrupt Generated

�� √1 √

1� ×1 √

ADDEN Bit Function

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

UART Module Power Down and Wake-upWhenthefSYSisoff,theUARTwillceasetofunction.Allclocksourcestothemoduleareshutdown.IfthefSYSisoffwhileatransmissionisstillinprogress,thenthetransmissionwillbepauseduntiltheUARTclocksourcederivedfromthemicrocontrollerisactivated.Inasimilarway,iftheMCUenters thePowerDownModewhile receivingdata, then thereceptionofdatawill likewisebepaused.WhentheMCUentersthePowerDownMode,notethattheUSR,UCR1,UCR2,transmitandreceiveregisters,aswellastheBRGregisterwillnotbeaffected.ItisrecommendedtomakesurefirstthattheUARTdatatransmissionorreceptionhasbeenfinishedbeforethemicrocontrollerentersthePowerDownmode.

TheUARTfunctioncontainsareceiverRXpinwake-upfunction,which isenabledordisabledbytheWAKEbitintheUCR2register.Ifthisbit,alongwiththeUARTenablebit,UARTEN,thereceiverenablebit,RXENandthereceiverinterruptbit,RIE,areallsetbeforetheMCUentersthePowerDownMode,thenafallingedgeontheRXpinwillwakeuptheMCUfromthePowerDownMode.Note thatas it takescertainsystemclockcyclesafterawake-up,beforenormalmicrocontrolleroperationresumes,anydatareceivedduringthistimeontheRXpinwillbeignored.

ForaUARTwake-upinterrupttooccur,inadditiontothebitsforthewake-upbeingset,theglobalinterruptenablebit,EMI,andtheUARTinterruptenablebit,UARE,mustalsobeset.Ifthesetwobitsarenotsetthenonlyawakeupeventwilloccurandnointerruptwillbegenerated.Notealsothatasittakescertainsystemclockcyclesafterawake-upbeforenormalmicrocontrollerresumes,theUARTinterruptwillnotbegenerateduntilafterthistimehaselapsed.

InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModuleoranA/Dconverterrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.Thedevicecontainsanexternalinterruptandinternal interruptsfunctions.Theexternal interrupt isgeneratedbytheactionof theexternalINTnpins,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchastheTMs,TimeBase,EEPROM,SIM,UARTandtheA/Dconverter.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesof registers, located in theSpecialPurposeDataMemory,asshownintheaccompanying table.Thenumberof registersdependsupon thedevicechosenbut fall intothreecategories.Thefirst is theINTC0~INTC3registerswhichsetuptheprimaryinterrupts, thesecond is theMFI0~MFI2registerswhichsetup theMulti-function interrupts.Finally thereareINTEG0~INTEG1registerstosetuptheexternalinterrupttriggeredgetype.

Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestflag.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Function Enable Bit Request Flag NotesGlo�al EMI — —I�Tn Pin I�TnE I�TnF n=�~5UART UARE UARF —Ti�e Base TBnE TBnF n=� o� 1A/D Conve�te� ADE ADF —Multi-function MFnE MFnF n=�~2EEPROM DEE DEF —SIM SIME SIMF —

CTMCTMPE CTMPF

—CTMAE CTMAF

STMSTMPE STMPF

—STMAE STMAF

PTMPTMnPE PTMnPF

n=� o� 1PTMnAE PTMnAF

Interrupt Register Bit Naming Conventions

RegisterName

Bit

7 6 5 4 3 2 1 0I�TEG� I�T3S1 I�T3S� I�T2S1 I�T2S� I�T1S1 I�T1S� I�T�S1 I�T�S�I�TEG1 — — — — I�T5S1 I�T5S� I�T4S1 I�T4S�I�TC� — I�T2F I�T1F I�T�F I�T2E I�T1E I�T�E EMII�TC1 UARF I�T5F I�T4F I�T3F UARE I�T5E I�T4E I�T3EI�TC2 ADF MF2F MF1F MF�F ADE MF2E MF1E MF�EI�TC3 SIMF DEF TB1F TB�F SIME DEE TB1E TB�EMFI� — — CTMAF CTMPF — — CTMAE CTMPEMFI1 LVF — STMAF STMPF LVE — STMAE STMPEMFI2 PTM1AF PTM1PF PTM�AF PTM�PF PTM1AE PTM1PE PTM�AE PTM�PE

Interrupt Register Contents

INTEG0 Register

Bit 7 6 5 4 3 2 1 0�a�e I�T3S1 I�T3S� I�T2S1 I�T2S� I�T1S1 I�T1S� I�T�S1 I�T�S�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7~6 INT3S1, INT3S0:DefinesINT3interruptactiveedge00:DisabledInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt

Bit5~4 INT2S1, INT2S0:DefinesINT2interruptactiveedge00:DisabledInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt

Bit3~2 INT1S1, INT1S0:DefinesINT1interruptactiveedge00:DisabledInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Bit1~0 INT0S1, INT0S0:DefinesINT0interruptactiveedge00:DisabledInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt

INTEG1 Register

Bit 7 6 5 4 3 2 1 0�a�e — — — — I�T5S1 I�T5S� I�T4S1 I�T4S�R/W — — — — R/W R/W R/W R/WPOR — — — — � � � �

Bit7~4 Unimplemented,readas"0"Bit3~2 INT5S1, INT5S0:DefinesINT5interruptactiveedge

00:DisabledInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt

Bit1~0 INT4S1, INT4S0:DefinesINT4interruptactiveedge00:DisabledInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt

INTC0 Register

Bit 7 6 5 4 3 2 1 0�a�e — I�T2F I�T1F I�T�F I�T2E I�T1E I�T�E EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — � � � � � � �

Bit7 Unimplemented,readas"0"Bit6 INT2F:INT2InterruptRequestFlag

0:Norequest1:Interruptrequest

Bit5 INT1F:INT1InterruptRequestFlag0:Norequest1:Interruptrequest

Bit4 INT0F:INT0InterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 INT2E:INT2InterruptControl0:Disable1:Enable

Bit2 INT1E:INT1InterruptControl0:Disable1:Enable

Bit1 INT0E:INT0InterruptControl0:Disable1:Enable

Bit0 EMI:GlobalInterruptControl0:Disable1:Enable

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

INTC1 Register

Bit 7 6 5 4 3 2 1 0�a�e UARF I�T5F I�T4F I�T3F UARE I�T5E I�T4E I�T3ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7 UARF:UARTInterruptRequestFlag0:Norequest1:Interruptrequest

Bit6 INT5F:INT5InterruptRequestFlag0:Norequest1:Interruptrequest

Bit5 INT4F:INT4InterruptRequestFlag0:Norequest1:Interruptrequest

Bit4 INT3F:INT3InterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 UARE:UARTInterruptControl0:Disable1:Enable

Bit2 INT5E:INT5InterruptControl0:Disable1:Enable

Bit1 INT4E:INT4InterruptControl0:Disable1:Enable

Bit0 INT3E:INT3InterruptControl0:Disable1:Enable

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

INTC2 Register

Bit 7 6 5 4 3 2 1 0�a�e ADF MF2F MF1F MF�F ADE MF2E MF1E MF�ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7 ADF:A/DConverterInterruptRequestFlag0:Norequest1:Interruptrequest

Bit6 MF2F:Multi-function2InterruptRequestFlag0:Norequest1:Interruptrequest

Bit5 MF1F:Multi-function1InterruptRequestFlag0:Norequest1:Interruptrequest

Bit4 MF0F:Multi-function0InterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 ADE:A/DConverterInterruptControl0:Disable1:Enable

Bit2 MF2E:Multi-function2InterruptControl0:Disable1:Enable

Bit1 MF1E:Multi-function1InterruptControl0:Disable1:Enable

Bit0 MF0E:Multi-function0InterruptControl0:Disable1:Enable

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

INTC3 Register

Bit 7 6 5 4 3 2 1 0�a�e SIMF DEF TB1F TB�F SIME DEE TB1E TB�ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7 SIMF:SerialInterfaceModuleInterruptRequestFlag0:Norequest1:Interruptrequest

Bit6 DEF:DataEEPROMInterruptRequestFlag0:Norequest1:Interruptrequest

Bit5 TB1F :TimeBase1InterruptRequestFlag0:Norequest1:Interruptrequest

Bit4 TB0F:TimeBase0InterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 SIME:SerialInterfaceModuleInterruptControl0:Disable1:Enable

Bit2 DEE:DataEEPROMInterruptControl0:Disable1:Enable

Bit1 TB1E :TimeBase1InterruptControl0:Disable1:Enable

Bit0 TB0E:TimeBase0InterruptControl0:Disable1:Enable

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

MFI0 Register

Bit 7 6 5 4 3 2 1 0�a�e — — CTMAF CTMPF — — CTMAE CTMPER/W — — R/W R/W — — R/W R/WPOR — — � � — — � �

Bit7~6 Unimplemented,readas"0"Bit5 CTMAF:CTMComparatorAmatchinterruptrequestflag

0:Norequest1:Interruptrequest

Bit4 CTMPF:CTMComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas"0"Bit1 CTMAE:CTMComparatorAmatchinterruptcontrol

0:Disable1:Enable

Bit0 CTMPE:CTMComparatorPmatchinterruptcontrol0:Disable1:Enable

MFI1 Register

Bit 7 6 5 4 3 2 1 0�a�e LVF — STMAF STMPF LVE — STMAE STMPER/W R/W — R/W R/W R/W — R/W R/WPOR � — � � � — � �

Bit7 LVF:LVDinterruptrequestflag0:Norequest1:Interruptrequest

Bit6 Unimplemented,readas"0"Bit5 STMAF:STMComparatorAmatchinterruptrequestflag

0:Norequest1:Interruptrequest

Bit4 STMPF:STMComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 LVE:LVDinterruptcontrol0:Disable1:Enable

Bit2 Unimplemented,readas"0"Bit1 STMAE:STMComparatorAmatchinterruptcontrol

0:Disable1:Enable

Bit0 STMPE:STMComparatorPmatchinterruptcontrol0:Disable1:Enable

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

MFI2 Register

Bit 7 6 5 4 3 2 1 0�a�e PTM1AF PTM1PF PTM�AF PTM�PF PTM1AE PTM1PE PTM�AE PTM�PER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7 PTM1AF:PTM1ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit6 PTM1PF:PTM1ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit5 PTM0AF:PTM0ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit4 PTM0PF:PTM0ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 PTM1AE:PTM1ComparatorAmatchinterruptcontrol0:Disable1:Enable

Bit2 PTM1PE:PTM1ComparatorPmatchinterruptcontrol0:Disable1:Enable

Bit1 PTM0AE:PTM0ComparatorAmatchinterruptcontrol0:Disable1:Enable

Bit0 PTM0PE:PTM0ComparatorPmatchinterruptcontrol0:Disable1:Enable

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMComparatorPorComparatorAmatchorA/Dconversioncompletionetc, therelevant interruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea“JMP”whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha“RETI”,whichretrieves theoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagrams with theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

INT0 Pin

EEPROM

INT0F

DEF

INT0E

DEE

EMI 04H

EMI 20H

EMI 24H

Time Base 0 TB0F TB0E

PTM0P PTM0PF PTM0PE

EMI 30H

Interrupt Name

Request Flags

Enable Bits

Master Enable Vector

EMI auto disabled in ISR

PriorityHigh

Low

CTMP CTMPF CTMPE

CTMA CTMAF CTMAE M. Funct. 0 MF0F MF0E

Interrupts contained within Multi-Function Interrupts

xxE Enable Bits

xxF Request Flag, auto reset in ISR

LegendxxF Request Flag, no auto reset in ISR

EMI 34H

EMI 38H

M. Funct. 1 MF1F MF1E

Time Base 1 TB1F TB1E

PTM0A PTM0AF PTM0AEA/D ADF ADE EMI 2CH

EMI 28H

PTM1P PTM1PF PTM1PE

M. Funct. 2 MF2F MF2E

PTM1A PTM1AF PTM1AE

STMP STMPF STMPE

STMA STMAF STMAE

INT1 Pin INT1F INT1E EMI 08H

INT2 Pin INT2F INT2E EMI 0CH

INT3 Pin INT3F INT3E EMI 10H

INT4 Pin INT4F INT4E EMI 14H

INT5 Pin INT5F INT5E EMI 18H

SIM SIMF SIME EMI 3CH

EMI 1CHUART UARF UARE

LVD LVF LVE

Interrupt Structure

External InterruptTheexternal interrupt iscontrolledbysignal transitionson thepins INT0~INT5.Anexternalinterrupt requestwill takeplacewhen theexternal interrupt request flag, INTnF, isset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternalinterruptpin.Toallowtheprogramtobranchtotheinterruptvectoraddress, theglobal interruptenablebit,EMI,andtheexternal interruptenablebit, INTnE,mustfirstbeset.Additionallythecorrect interruptedge typemustbeselectedusing the INTEGnregister toenable theexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinispin-sharedwithanI/Opin,itcanonlybeconfiguredasexternalinterruptpinifitsexternalinterruptenablebitinthecorrespondinginterruptregisterhasbeenset.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,willtakeplace.Whentheinterruptisserviced,theexternalinterruptrequestflag,INTnF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatthepull-highresistorselectionontheexternalinterruptpinwillremainvalidevenifthepinisusedasanexternalinterruptinput.

TheINTEG0~INTEG1registersareused toselect the typeofactiveedge thatwill trigger theexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEG0~INTEG1registerscanalsobeusedtodisabletheexternalinterruptfunction.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Multi-function InterruptWithin thisdevice thereareup to threeMulti-functioninterrupts.Unlike theother independentinterrupts, theseinterruptshavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namelytheTMInterruptsandLVDinterrupt.

AMulti-functioninterruptrequestwilltakeplacewhenanyoftheMulti-functioninterruptrequestflags,MF0F~MF2Fareset.TheMulti-functioninterruptflagswillbesetwhenanyoftheirincludedfunctionsgenerateaninterruptrequestflag.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,whentheMulti-functioninterruptisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecalltooneoftheMulti-functioninterruptvectorswilltakeplace.Whentheinterruptisserviced,therelatedMulti-FunctionrequestflagwillbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

However, itmustbenotedthat,althoughtheMulti-functionInterruptflagswillbeautomaticallyresetwhentheinterruptisserviced,therequestflagsfromtheoriginalsourceoftheMulti-functioninterrupts,namelytheTMInterruptsandLVDinterrupt,willnotbeautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.

A/D Converter InterruptThedevicecontainsanA/Dconverterwhichhasitsownindependentinterrupt.TheA/DConverterInterruptiscontrolledbytheterminationofanA/Dconversionprocess.AnA/DConverterInterruptrequestwill takeplacewhentheA/DConverterInterruptrequestflag,ADF, isset,whichoccurswhentheA/Dconversionprocessfinishes.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,ADE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/Dconversionprocesshasended,asubroutinecalltotheA/DConverterInterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,ADF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Time Base InterruptsThefunctionoftheTimeBaseInterruptsistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromtheirrespectivetimerfunctions.Whenthesehappens their respective interrupt request flags,TB0ForTB1Fwillbeset.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMIandTimeBaseenablebits,TB0EorTB1E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecall totheirrespectivevectorlocationswilltakeplace.Whentheinterruptisserviced,therespectiveinterruptrequestflag,TB0ForTB1F,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.TheirclocksourcesoriginatefromtheinternalclocksourcefTB.ThisfTB inputclockpasses throughadivider, thedivisionratioofwhich isselectedbyprogrammingtheappropriatebits in theTBCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcethatgeneratesfTB,whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromseveraldifferentsources,asshownintheSystemOperatingModesection.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

TBC Register

Bit 7 6 5 4 3 2 1 0�a�e TBO� TBCK TB11 TB1� LXTLP TB�2 TB�1 TB��R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � 1 1 � 1 1 1

Bit7 TBON:TB0andTB1Controlbit0:Disable1:Enable

Bit6 TBCK:SelectfTBClock0:fTBC1:fSYS/4

Bit5~4 TB11 ~ TB10:SelectTimeBase1Time-outPeriod00:4096/fTB01:8192/fTB10:16384/fTB11:32768/fTB

Bit3 LXTLP:LXTLowPowerModecontrol0:Disable(QuickStartMode)1:Enable(LowPowerMode)

Bit2~0 TB02 ~ TB00:SelectTimeBase0Time-outPeriod000:28/fTB001:29/fTB010:210/fTB011:211/fTB100:212/fTB101:213/fTB110:214/fTB111:215/fTB

Time Base 1 InterruptLIRC

MUX

fSYS/4

fTBC

fTB

÷212~215

TB11~TB10

TBCK bit

LXTMUX

Configuration Option

Time Base 0 Interrupt÷28~215

TB02~TB00

Time Base Interrupt

Serial Interface Module InterruptsASIMInterruptrequestwill takeplacewhentheSIMInterruptrequestflag,SIMF,isset,whichoccurswhenabyteofdatahasbeenreceivedor transmittedbytheSIMinterface.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andtheSerialInterfaceInterruptenablebit,SIME,mustfirstbeset.Whentheinterruptisenabled,thestack isnotfullandabyteofdatahasbeentransmittedorreceivedbytheSIMinterface,asubroutinecalltotherespectiveInterruptvector,willtakeplace.Whentheinterruptisserviced,therespectiveinterruptrequestflag,SIMF,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

EEPROM InterruptAnEEPROMInterruptrequestwilltakeplacewhentheEEPROMInterruptrequestflag,DEF,isset,whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andEEPROMInterruptenablebit,DEE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMWritecycleends,asubroutinecalltotherespectiveEEPROMInterruptvector,willtakeplace.WhentheEEPROMInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,andtheEEPROMinterruptrequestflag,DEF,willalsobeautomaticallycleared.

TM InterruptsTheCompact,StandardandPeriodicTypeTMseachhastwointerrupts.AlloftheTMinterruptsarecontainedwithintheMulti-functionInterrupts.ForeachoftheCompact,StandardandPeriodicTypeTMstherearetwointerruptrequestflagsxTMnPFandxTMnAFandtwoenablebitsxTMnPEandxTMnAE.ATMinterruptrequestwilltakeplacewhenanyoftheTMrequestflagsareset,asituationwhichoccurswhenaTMcomparatorPorcomparatorAmatchsituationhappens.

Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtherespectiveTMInterruptenablebit,andassociatedMulti-functioninterruptenablebit,MFnF,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecall to therelevantTMInterruptvector locations,will takeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMFnFflagwillbeautomaticallycleared.AstheTMinterruptrequestflagswillnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.

LVD Interrupt TheLowVoltageDetector Interrupt iscontainedwithin theMulti-function Interrupt.AnLVDInterruptrequestwill takeplacewhentheLVDInterruptrequestflag,LVF, isset,whichoccurswhentheLowVoltageDetectorfunctiondetectsalowpowersupplyvoltage.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,LowVoltageInterruptenablebit,LVE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowvoltageconditionoccurs,asubroutinecalltotheMulti-functionInterruptvectorwilltakeplace.WhentheLowVoltageInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheLVFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

UART InterruptSeveralindividualUARTconditionscangenerateaUARTinterrupt.Whentheseconditionsexist,a lowpulsewillbegeneratedtoget theattentionof themicrocontroller.Theseconditionsareatransmitterdataregisterempty, transmitter idle,receiverdataavailable,receiveroverrun,addressdetectandanRXpinwake-up.Toallowtheprogramtobranchtotherespectiveinterruptvectoraddresses, theglobalinterruptenablebit,EMI,andUARTinterruptenablebit,UARE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanyoftheseconditionsarecreated,asubroutinecall totheUARTInterruptvectorwill takeplace.Whentheinterruptisserviced,theUARTInterruptflag,UARF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.However, theUSRregisterflagswillbeclearedautomaticallywhencertainactionsaretakenbytheUART,thedetailsofwhicharegivenintheUARTsection.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpin,alowpowersupplyvoltageorcomparatorinputchangemaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptserviceroutineisexecuted,asonlytheMulti-functioninterruptrequestflags,MF0F~MF2F,willbeautomaticallycleared, the individualrequestflagfor thefunctionneeds tobeclearedbytheapplicationprogram.

It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.

Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Software LCD DriverThedeviceshavethecapabilityofdrivingexternalLCDpanels.ThecommonpinsforLCDdriving,SCOM0~SCOM5,andsegmentpins,SSEG0~SSEG29,arepinsharedwithcertainpinontheI/Oports.TheLCDsignals(COMandSEG)aregeneratedusingtheapplicationprogram.

LCD operationAnexternalLCDpanelcanbedrivenusingthisdevicebyconfiguring theI/OpinsascommonpinsandconfiguringtheI/Opinsassegmentpins.TheLCDdriverfunctioniscontrolledusingtheSLCDC0~SLCDC4registerswhichinadditiontocontrollingtheoverallon/offfunction,LCDbiascurrentsetupfunctionalsocontrolsthepinfunctionselection.ThisenablestheLCDCOMandSEGdrivertogeneratethenecessaryVSS,(1/3)VDD,(2/3)VDDvoltageandVDD levelsforLCD1/3biasoperation.

TheLCDENbit in theSLCDC0register is theoverallmastercontrol for theLCDdriver.TheLCDSCOMnpinisselectedtobeusedforLCDdrivingbythecorrespondingpin-sharedfunctionselectionbits.NotethatthePortControlregisterdoesnotneedtofirstsetupthepinsasoutputstoenabletheLCDdriveroperation.

VDD

VSS

LCD Voltage Select Circuit

AnalogSwitch

VDD

SCOM0

SCOM5

SSEG0

SSEG29

VSS

VDD

(2/3)VDD

(1/3)VDD

VSS

LCD Driver structure

LCD Control RegistersTheLCDCOMdriverenablesarangeofselectionstobeprovidedtosuit therequirementoftheLCDpanelwhicharebeingused.Thebiascurrentchoice is implementedusing theISEL1andISEL0bitsintheSLCDC0register,theFRAMEbitisusedtoselecttheoutputframe.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

SLCDC0 Register

Bit 7 6 5 4 3 2 1 0�a�e FRAME ISEL1 ISEL� LCDE� COM3E� COM2E� COM1E� COM�E�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7 FRAME:Outputframe0orframe10:Frame01:Frame1

Bit6~5 ISEL1~ISEL0:LCDbiascurrentselection(VDD=5V)00:8.3μA01:16.7μA10:50μA11:100μA

Bit4 LCDEN:SCOMandSSEGmoduleon/offcontrol0:Off1:On

SCOMnandSSEGmcanbeenablebyCOMnENandSEGmENifLCDEN=1IfLCDEN=0,SCOMnandSSEGmoutputVSS

WhenLCDENisset, itwill turnon theDCpathofresistor togenerateLCDBiasvoltage.

Bit3 COM3EN:LCDorotherfunctionselection0:Otherfunction1:SCOM3/SSEG3

Bit2 COM2EN:LCDorotherfunctionselection0:Otherfunction1:SCOM2/SSEG2

Bit1 COM1EN:LCDorotherfunctionselection0:Otherfunction1:SCOM1/SSEG1

Bit0 COM0EN:LCDorotherfunctionselection0:Otherfunction1:SCOM0/SSEG0

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

SLCDC1 Register

Bit 7 6 5 4 3 2 1 0�a�e COM5E� COM4E� COMSEGS5 COMSEGS4 COMSEGS3 COMSEGS2 COMSEGS1 COMSEGS�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7 COM5EN:LCDorotherfunctionselection0:Otherfunction1:SCOM5/SSEG5

Bit6 COM4EN:LCDorotherfunctionselection0:Otherfunction1:SCOM4/SSEG4

Bit5 COMSEGS5:SCOM5orSSEG5selection0:SCOM51:SSEG5

Bit4 COMSEGS4:SCOM4orSSEG4selection0:SCOM41:SSEG4

Bit3 COMSEGS3:SCOM3orSSEG3selection0:SCOM31:SSEG3

Bit2 COMSEGS2:SCOM2orSSEG2selection0:SCOM21:SSEG2

Bit1 COMSEGS1:SCOM1orSSEG1selection0:SCOM11:SSEG1

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

SLCDC2 Register

Bit 7 6 5 4 3 2 1 0�a�e SEG13E� SEG12E� SEG11E� SEG1�E� SEG�E� SEG8E� SEG�E� SEG6E�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7 SEG13EN:SSEG13functioncontrol0:Disable1:Enable

Bit6 SEG12EN:SSEG12functioncontrol0:Disable1:Enable

Bit5 SEG11EN:SSEG11functioncontrol0:Disable1:Enable

Bit4 SEG10EN:SSEG10functioncontrol0:Disable1:Enable

Bit3 SEG9EN:SSEG9functioncontrol0:Disable1:Enable

Bit2 SEG8EN:SSEG8functioncontrol0:Disable1:Enable

Bit1 SEG7EN:SSEG7functioncontrol0:Disable1:Enable

Bit0 SEG6EN:SSEG6functioncontrol0:Disable1:Enable

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

SLCDC3 Register

Bit 7 6 5 4 3 2 1 0�a�e SEG21E� SEG2�E� SEG1�E� SEG18E� SEG1�E� SEG16E� SEG15E� SEG14E�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7 SEG21EN:SSEG21functioncontrol0:Disable1:Enable

Bit6 SEG20EN:SSEG20functioncontrol0:Disable1:Enable

Bit5 SEG19EN:SSEG19functioncontrol0:Disable1:Enable

Bit4 SEG18EN:SSEG18functioncontrol0:Disable1:Enable

Bit3 SEG17EN:SSEG17functioncontrol0:Disable1:Enable

Bit2 SEG16EN:SSEG16functioncontrol0:Disable1:Enable

Bit1 SEG15EN:SSEG15functioncontrol0:Disable1:Enable

Bit0 SEG14EN:SSEG14functioncontrol0:Disable1:Enable

Note:SSEG14,SSEG15sharethepinswithOSC1/XT1,OSC2/XT2functions,ifselecttheOSC2/OSC1orXT2/XT1pinfunction,thentheSEG14,SEG15havenoactionsevenifthefunctionsareenabled.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

SLCDC4 Register

Bit 7 6 5 4 3 2 1 0�a�e SEG2�E� SEG28E� SEG2�E� SEG26E� SEG25E� SEG24E� SEG23E� SEG22E�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR � � � � � � � �

Bit7 SEG29EN:SSEG29functioncontrol0:Disable1:Enable

Bit6 SEG28EN:SSEG28functioncontrol0:Disable1:Enable

Bit5 SEG27EN:SSEG27functioncontrol0:Disable1:Enable

Bit4 SEG26EN:SSEG26functioncontrol0:Disable1:Enable

Bit3 SEG25EN:SSEG25functioncontrol0:Disable1:Enable

Bit2 SEG24EN:SSEG24functioncontrol0:Disable1:Enable

Bit1 SEG23EN:SSEG23functioncontrol0:Disable1:Enable

Bit0 SEG22EN:SSEG22functioncontrol0:Disable1:Enable

LCD waveformTheaccompanyingwaveformdiagramshowsatypical1/3BiasLCDwaveformgeneratedusingtheapplicationprogram.Notethatthedepictionofa"1"inthediagramillustratesanilluminatedLCDpixel.TheCOMsignalpolaritygeneratedonpinsSCOMn,whether0or1,aregeneratedusingthecorrespondingI/Odataregisters.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

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1/3 Bias LCD Waveform

AcyclicLCDwaveformincludestwoframes,knownasFrame0andFrame1whichisselectedbytheFRAMEbitintheSLCDC0register.Thefollowingoffersafunctionalexplanation.

ToselectFrame0cleartheFRAMEbitto0.

Inframe0,theCOMsignaloutputcanhaveavalueofVDD,orhaveaVbiasvalueof1/3VDD(SEG_L).TheSEGsignalcanhaveavalueofVSS,orhaveaVbiasvalueof2/3VDD(SEG_H).

Inframe1,theCOMsignaloutputcanhaveavalueofVSS,orhaveaVbiasvalueof2/3VDD(SEG_H).TheSEGsignalcanhaveavalueofVDDhaveaVbiasvalueof1/3VDD(SEG_L).

TheSCOM0~SCOMnwaveformiscontrolledbytheapplicationprogramusingtheFRAMEbit,and thecorrespondingI/Odata register for therespectiveSCOMpin todeterminewhether theSCOM0~SCOMnoutputhasavalueofeitherVDD,VSSorVbias.TheSSEG0~SSEGmwaveformiscontrolledinasimilarwayusingtheFRAMEbitandthecorrespondingI/OdataregisterfortherespectiveSSEGpintodeterminewhethertheSSEG0~SSEGnoutputhasavalueofeitherVDD,VSS

orVbias.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Low Voltage Detector – LVDEachdevicehasaLowVoltageDetectorfunction,alsoknownasLVD.Thisenabledthedevicetomonitorthepowersupplyvoltage,VDD,andprovideawarningsignalshoulditfallbelowacertainlevel.Thisfunctionmaybeespeciallyusefulinbatteryapplicationswherethesupplyvoltagewillgraduallyreduceasthebatteryages,asitallowsanearlywarningbatterylowsignaltobegenerated.TheLowVoltageDetectoralsohasthecapabilityofgeneratinganinterruptsignal.

LVD RegisterTheLowVoltageDetectorfunctioniscontrolledusingasingleregisterwiththenameLVDC.Threebits inthisregister,VLVD2~VLVD0,areusedtoselectoneofeightfixedvoltagesbelowwhichalowvoltageconditionwillbedetermined.AlowvoltageconditionisindicatedwhentheLVDObitisset.IftheLVDObitislow,thisindicatesthattheVDDvoltageisabovethepresetlowvoltagevalue.TheLVDENbit isusedtocontrol theoverallon/offfunctionof thelowvoltagedetector.Settingthebithighwillenablethelowvoltagedetector.Clearingthebittozerowillswitchofftheinternallowvoltagedetectorcircuits.Asthelowvoltagedetectorwillconsumeacertainamountofpower,itmaybedesirabletoswitchoffthecircuitwhennotinuse,animportantconsiderationinpowersensitivebatterypoweredapplications.

LVDC Register

Bit 7 6 5 4 3 2 1 0�a�e — — LVDO LVDE� — VLVD2 VLVD1 VLVD�R/W — — R R/W — R/W R/W R/WPOR — — � � — � � �

Bit7~6 Unimplemented,readas"0"Bit5 LVDO:LVDOutputFlag

0:NoLowVoltageDetect1:LowVoltageDetect

Bit4 LVDEN:LowVoltageDetectorControl0:Disable1:Enable

Bit3 Unimplemented,readas“0”Bit2~0 VLVD2~VLVD0:SelectLVDVoltage

000:2.0V001:2.2V010:2.4V011:2.7V100:3.0V101:3.3V110:3.6V111:4.0V

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

LVD OperationTheLowVoltageDetectorfunctionoperatesbycomparingthepowersupplyvoltage,VDD,withapre-specifiedvoltagelevelstoredintheLVDCregister.Thishasarangeofbetween2.0Vand4.0V.Whenthepowersupplyvoltage,VDD,fallsbelowthispre-determinedvalue,theLVDObitwillbesethighindicatinga lowpowersupplyvoltagecondition.TheLowVoltageDetectorfunctionissuppliedbyareferencevoltagewhichwillbeautomaticallyenabled.WhenthedeviceispowereddownthelowvoltagedetectorwillremainactiveiftheLVDENbitishigh.AfterenablingtheLowVoltageDetector,atimedelaytLVDSshouldbeallowedforthecircuitrytostabilisebeforereadingtheLVDObit.NotealsothatastheVDDvoltagemayriseandfallratherslowly,atthevoltagenearsthatofVLVD,theremaybemultiplebitLVDOtransitions.

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LVD Operation

TheLowVoltageDetectoralsohasitsowninterruptwhichiscontainedwithinoneoftheMulti-functioninterrupts,providinganalternativemeansoflowvoltagedetection,inadditiontopollingtheLVDObit.TheinterruptwillonlybegeneratedafteradelayoftLVDaftertheLVDObithasbeensethighbyalowvoltagecondition.WhenthedeviceispowereddowntheLowVoltageDetectorwillremainactiveiftheLVDENbitishigh.Inthiscase,theLVFinterruptrequestflagwillbeset,causinganinterrupttobegeneratedifVDDfallsbelowthepresetLVDvoltage.Thiswillcausethedevicetowake-upfromtheSLEEPMode,howeveriftheLowVoltageDetectorwakeupfunctionisnotrequiredthentheLVFflagshouldbefirstsethighbeforethedeviceenterstheSLEEPMode.

WhenLVDfunctionisenabled,itisrecommencedtoclearLVDflagfirst,andthenenablesinterruptfunctiontoavoidmistakeaction.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Configuration OptionConfigurationoptionsrefertocertainoptionswithintheMCUthatareprogrammedintothedeviceduringtheprogrammingprocess.Duringthedevelopmentprocess,theseoptionsareselectedusingtheHT-IDEsoftwaredevelopment tools.Astheseoptionsareprogrammedintothedeviceusingthehardwareprogrammingtools,once theyareselectedtheycannotbechangedlaterusingtheapplicationprogram.Alloptionsmustbedefinedforpropersystemfunction,thedetailsofwhichareshowninthetable.

No. OptionsOscillator Option

1

High Speed/Low Speed Syste� Oscillato� Selection – fOSC:HIRC+LIRCHIRC+LXTHXT+LIRC

Application Circuit

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe“CLRPCL”or“MOVPCL,A”.Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofseveralkindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsistoreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandless than0forsubtraction.Theincrementanddecrement instructionssuchasINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction“RET”inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe“SET[m].i”or“CLR[m].i”instructionsrespectively.Thefeatureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe“HALT”instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Instruction Set SummaryTheinstructionsrelated to thedatamemoryaccess in thefollowingtablecanbeusedwhenthedesireddatamemoryislocatedinDataMemorysector0.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A�[�] Add Data Me�o�y to ACC 1 Z� C� AC� OV� SCADDM A�[�] Add ACC to Data Me�o�y 1�ote Z� C� AC� OV� SCADD A�x Add i��ediate data to ACC 1 Z� C� AC� OV� SCADC A�[�] Add Data Me�o�y to ACC with Ca��y 1 Z� C� AC� OV� SCADCM A�[�] Add ACC to Data �e�o�y with Ca��y 1�ote Z� C� AC� OV� SCSUB A�x Su�t�act i��ediate data f�o� the ACC 1 Z� C� AC� OV� SC� CZSUB A�[�] Su�t�act Data Me�o�y f�o� ACC 1 Z� C� AC� OV� SC� CZSUBM A�[�] Su�t�act Data Me�o�y f�o� ACC with �esult in Data Me�o�y 1�ote Z� C� AC� OV� SC� CZSBC A�x Su�t�act i��ediate data f�o� ACC with Ca��y 1 Z� C� AC� OV� SC� CZSBC A�[�] Su�t�act Data Me�o�y f�o� ACC with Ca��y 1 Z� C� AC� OV� SC� CZSBCM A�[�] Su�t�act Data Me�o�y f�o� ACC with Ca��y� �esult in Data Me�o�y 1�ote Z� C� AC� OV� SC� CZDAA [�] Deci�al adjust ACC fo� Addition with �esult in Data Me�o�y 1�ote CLogic OperationA�D A�[�] Logical A�D Data Me�o�y to ACC 1 ZOR A�[�] Logical OR Data Me�o�y to ACC 1 ZXOR A�[�] Logical XOR Data Me�o�y to ACC 1 ZA�DM A�[�] Logical A�D ACC to Data Me�o�y 1�ote ZORM A�[�] Logical OR ACC to Data Me�o�y 1�ote ZXORM A�[�] Logical XOR ACC to Data Me�o�y 1�ote ZA�D A�x Logical A�D i��ediate Data to ACC 1 ZOR A�x Logical OR i��ediate Data to ACC 1 ZXOR A�x Logical XOR i��ediate Data to ACC 1 ZCPL [�] Co�ple�ent Data Me�o�y 1�ote ZCPLA [�] Co�ple�ent Data Me�o�y with �esult in ACC 1 ZIncrement & DecrementI�CA [�] Inc�e�ent Data Me�o�y with �esult in ACC 1 ZI�C [�] Inc�e�ent Data Me�o�y 1�ote ZDECA [�] Dec�e�ent Data Me�o�y with �esult in ACC 1 ZDEC [�] Dec�e�ent Data Me�o�y 1�ote ZRotateRRA [�] Rotate Data Me�o�y �ight with �esult in ACC 1 �oneRR [�] Rotate Data Me�o�y �ight 1�ote �oneRRCA [�] Rotate Data Me�o�y �ight th�ough Ca��y with �esult in ACC 1 CRRC [�] Rotate Data Me�o�y �ight th�ough Ca��y 1�ote CRLA [�] Rotate Data Me�o�y left with �esult in ACC 1 �oneRL [�] Rotate Data Me�o�y left 1�ote �oneRLCA [�] Rotate Data Me�o�y left th�ough Ca��y with �esult in ACC 1 CRLC [�] Rotate Data Me�o�y left th�ough Ca��y 1�ote C

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Mnemonic Description Cycles Flag AffectedData MoveMOV A�[�] Move Data Me�o�y to ACC 1 �oneMOV [�]�A Move ACC to Data Me�o�y 1�ote �oneMOV A�x Move i��ediate data to ACC 1 �oneBit OperationCLR [�].i Clea� �it of Data Me�o�y 1�ote �oneSET [�].i Set �it of Data Me�o�y 1�ote �oneBranch OperationJMP add� Ju�p unconditionally 2 �oneSZ [�] Skip if Data Me�o�y is ze�o 1�ote �oneSZA [�] Skip if Data Me�o�y is ze�o with data �ove�ent to ACC 1�ote �oneSZ [�].i Skip if �it i of Data Me�o�y is ze�o 1�ote �oneS�Z [�] Skip if Data Me�o�y is not ze�o 1�ote �oneS�Z [�].i Skip if �it i of Data Me�o�y is not ze�o 1�ote �oneSIZ [�] Skip if inc�e�ent Data Me�o�y is ze�o 1�ote �oneSDZ [�] Skip if dec�e�ent Data Me�o�y is ze�o 1�ote �oneSIZA [�] Skip if inc�e�ent Data Me�o�y is ze�o with �esult in ACC 1�ote �oneSDZA [�] Skip if dec�e�ent Data Me�o�y is ze�o with �esult in ACC 1�ote �oneCALL add� Su��outine call 2 �oneRET Retu�n f�o� su��outine 2 �oneRET A�x Retu�n f�o� su��outine and load i��ediate data to ACC 2 �oneRETI Retu�n f�o� inte��upt 2 �oneTable Read OperationTABRD [�] Read ta�le to TBLH and Data Me�o�y 2�ote �oneTABRDL [�] Read ta�le (last page) to TBLH and Data Me�o�y 2�ote �oneITABRD [�] Increment table pointer TBLP first and Read table to TBLH and Data Memory 2�ote �one

ITABRDL [�] Increment table pointer TBLP first and Read table (last page) to TBLH and Data Me�o�y 2�ote �one

Miscellaneous�OP �o ope�ation 1 �oneCLR [�] Clea� Data Me�o�y 1�ote �oneSET [�] Set Data Me�o�y 1�ote �oneCLR WDT Clea� Watchdog Ti�e� 1 TO� PDFSWAP [�] Swap ni��les of Data Me�o�y 1�ote �oneSWAPA [�] Swap ni��les of Data Me�o�y with �esult in ACC 1 �oneHALT Ente� powe� down �ode 1 TO� PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthenuptothreecyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.Forthe“CLRWDT”instructiontheTOandPDFflagsmaybeaffectedbytheexecutionstatus.TheTOandPDFflagsareclearedafterthe“CLRWDT”instructionsisexecuted.OtherwisetheTOandPDFflagsremainunchanged.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Extended Instruction SetTheextendedinstructionsareusedtosupport thefullrangeaddressaccessfor thedatamemory.When theaccesseddatamemory is located inanydatamemorysectionsexcept sector0, theextendedinstructioncanbeusedtoaccessthedatamemoryinsteadofusingtheindirectaddressingaccesstoimprovetheCPUfirmwareperformance.

Mnemonic Description Cycles Flag AffectedArithmeticLADD A�[�] Add Data Me�o�y to ACC 2 Z� C� AC� OV� SCLADDM A�[�] Add ACC to Data Me�o�y 2�ote Z� C� AC� OV� SCLADC A�[�] Add Data Me�o�y to ACC with Ca��y 2 Z� C� AC� OV� SCLADCM A�[�] Add ACC to Data �e�o�y with Ca��y 2�ote Z� C� AC� OV� SCLSUB A�[�] Su�t�act Data Me�o�y f�o� ACC 2 Z� C� AC� OV� SC� CZLSUBM A�[�] Su�t�act Data Me�o�y f�o� ACC with �esult in Data Me�o�y 2�ote Z� C� AC� OV� SC� CZLSBC A�[�] Su�t�act Data Me�o�y f�o� ACC with Ca��y 2 Z� C� AC� OV� SC� CZLSBCM A�[�] Su�t�act Data Me�o�y f�o� ACC with Ca��y� �esult in Data Me�o�y 2�ote Z� C� AC� OV� SC� CZLDAA [�] Deci�al adjust ACC fo� Addition with �esult in Data Me�o�y 2�ote CLogic OperationLA�D A�[�] Logical A�D Data Me�o�y to ACC 2 ZLOR A�[�] Logical OR Data Me�o�y to ACC 2 ZLXOR A�[�] Logical XOR Data Me�o�y to ACC 2 ZLA�DM A�[�] Logical A�D ACC to Data Me�o�y 2�ote ZLORM A�[�] Logical OR ACC to Data Me�o�y 2�ote ZLXORM A�[�] Logical XOR ACC to Data Me�o�y 2�ote ZLCPL [�] Co�ple�ent Data Me�o�y 2�ote ZLCPLA [�] Co�ple�ent Data Me�o�y with �esult in ACC 2 ZIncrement & DecrementLI�CA [�] Inc�e�ent Data Me�o�y with �esult in ACC 2 ZLI�C [�] Inc�e�ent Data Me�o�y 2�ote ZLDECA [�] Dec�e�ent Data Me�o�y with �esult in ACC 2 ZLDEC [�] Dec�e�ent Data Me�o�y 2�ote ZRotateLRRA [�] Rotate Data Me�o�y �ight with �esult in ACC 2 �oneLRR [�] Rotate Data Me�o�y �ight 2�ote �oneLRRCA [�] Rotate Data Me�o�y �ight th�ough Ca��y with �esult in ACC 2 CLRRC [�] Rotate Data Me�o�y �ight th�ough Ca��y 2�ote CLRLA [�] Rotate Data Me�o�y left with �esult in ACC 2 �oneLRL [�] Rotate Data Me�o�y left 2�ote �oneLRLCA [�] Rotate Data Me�o�y left th�ough Ca��y with �esult in ACC 2 CLRLC [�] Rotate Data Me�o�y left th�ough Ca��y 2�ote CData MoveLMOV A�[�] Move Data Me�o�y to ACC 2 �oneLMOV [�]�A Move ACC to Data Me�o�y 2�ote �oneBit OperationLCLR [�].i Clea� �it of Data Me�o�y 2�ote �oneLSET [�].i Set �it of Data Me�o�y 2�ote �one

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Mnemonic Description Cycles Flag AffectedBranchLSZ [�] Skip if Data Me�o�y is ze�o 2�ote �oneLSZA [�] Skip if Data Me�o�y is ze�o with data �ove�ent to ACC 2�ote �oneLS�Z [�] Skip if Data Me�o�y is not ze�o 2�ote �oneLSZ [�].i Skip if �it i of Data Me�o�y is ze�o 2�ote �oneLS�Z [�].i Skip if �it i of Data Me�o�y is not ze�o 2�ote �oneLSIZ [�] Skip if inc�e�ent Data Me�o�y is ze�o 2�ote �oneLSDZ [�] Skip if dec�e�ent Data Me�o�y is ze�o 2�ote �oneLSIZA [�] Skip if inc�e�ent Data Me�o�y is ze�o with �esult in ACC 2�ote �oneLSDZA [�] Skip if dec�e�ent Data Me�o�y is ze�o with �esult in ACC 2�ote �oneTable ReadLTABRD [�] Read ta�le to TBLH and Data Me�o�y 3�ote �oneLTABRDL [�] Read ta�le (last page) to TBLH and Data Me�o�y 3�ote �oneLITABRD [�] Increment table pointer TBLP first and Read table to TBLH and Data Memory 3�ote �one

LITABRDL [�] Increment table pointer TBLP first and Read table (last page) to TBLH and Data Me�o�y 3�ote �one

MiscellaneousLCLR [�] Clea� Data Me�o�y 2�ote �oneLSET [�] Set Data Me�o�y 2�ote �oneLSWAP [�] Swap ni��les of Data Me�o�y 2�ote �oneLSWAPA [�] Swap ni��les of Data Me�o�y with �esult in ACC 2 �one

Note:1.Fortheseextendedskipinstructions,iftheresultofthecomparisoninvolvesaskipthenuptofourcyclesarerequired,ifnoskiptakesplacetwocyclesisrequired.

2.AnyextendedinstructionwhichchangesthecontentsofthePCLregisterwillalsorequirethreecyclesforexecution.

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C,SC

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ

SBC A, x SubtractimmediatedatafromACCwithCarryDescription Theimmediatedataandthecomplementofthecarryflagaresubtractedfromthe Accumulator.TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionis negative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflag willbesetto1.Operation ACC←ACC-[m]-CAffectedflag(s) OV,Z,AC,C,SC,CZ

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifDataMemoryisnot0Description IfthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisrequiresthe insertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SNZ [m] SkipifDataMemoryisnot0Description IfthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisrequiresthe insertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C,SC,CZ

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

TABRD [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

ITABRD [m] IncrementtablepointerlowbytefirstandreadtabletoTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthentheprogramcodeaddressedbythe tablepointer(TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbyte movedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

ITABRDL [m] Incrementtablepointerlowbytefirstandreadtable(lastpage)toTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthenthelowbyteoftheprogramcode (lastpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryand thehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Extended Instruction DefinitionTheextendedinstructionsareusedtodirectlyaccessthedatastoredinanydatamemorysections.

LADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC

LADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC

LADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC

LADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC

LAND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

LANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

LCLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

LCLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

LCPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

LCPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

LDAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

LDEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

LDECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

LINC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

LINCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

LMOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

LMOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

LOR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

LORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

LRL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

LRLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

LRLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

LRLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

LRR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

LRRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

LRRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

LRRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

LSBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ

LSBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

LSDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

LSDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

LSET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

LSET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

LSIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

LSIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

LSNZ [m].i SkipifDataMemoryisnot0Description IfthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisrequiresthe insertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

LSNZ [m] SkipifDataMemoryisnot0Description IfthecontentofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.As thisrequirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisa twocycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]≠0Affectedflag(s) None

LSUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ

LSUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ

LSWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

LSWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

LSZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

LSZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

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HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

LSZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

LTABRD [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

LTABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

LITABRD [m] IncrementtablepointerlowbytefirstandreadtabletoTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthentheprogramcodeaddressedbythe tablepointer(TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbyte movedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)

Affectedflag(s) None

LITABRDL [m] Incrementtablepointerlowbytefirstandreadtable(lastpage)toTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthenthelowbyteoftheprogramcode (lastpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryand thehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

LXOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

LXORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

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Rev. 1.21 1�2 �ove��e� ��� 2�1� Rev. 1.21 1�3 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Package Information

Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthePackage/CartonInformation.

Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.

• PackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)

• TheOperationInstructionofPackingMaterials

• Cartoninformation

Page 193: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 1�2 �ove��e� ��� 2�1� Rev. 1.21 1�3 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

28-pin SOP (300mil) Outline Dimensions

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SymbolDimensions in inch

Min. Nom. Max.A — �.4�6 BSC —B — �.2�5 BSC —C �.�12 — �.�2�C’ — �.��5 BSC —D — — �.1�4E — �.�5� BSC —F �.��4 — �.�12G �.�16 — �.�5�H �.��8 — �.�13α �° — 8°

SymbolDimensions in mm

Min. Nom. Max.A — 1�.3� BSC —B — �.5� BSC —C �.31 — �.51C’ — 1�.� BSC —D — — 2.65E — 1.2� BSC —F �.1� — �.3�G �.4� — 1.2�H �.2� — �.33α �° — 8°

Page 194: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 1�4 �ove��e� ��� 2�1� Rev. 1.21 1�5 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

28-pin SSOP (150mil) Outline Dimensions

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SymbolDimensions in inch

Min. Nom. Max.A — �.236 BSC —B — �.154 BSC —C �.��8 — �.�12 C’ — �.3�� BSC —D — — �.�6� E — �.�25 BSC —F �.��4 — �.�1� G �.�16 — �.�5� H �.��4 — �.�1�α �° — 8°

SymbolDimensions in mm

Min. Nom. Max.A — 6.� BSC —B — 3.� BSC —C �.2� — �.3� C’ — �.� BSC —D — — 1.�5 E — �.635 BSC —F �.1� — �.25 G �.41 — 1.2� H �.1� — �.25 α �° — 8°

Page 195: A/D Flash MCU with EEPROM · CPU Features • Operating Voltage ... Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile

Rev. 1.21 1�4 �ove��e� ��� 2�1� Rev. 1.21 1�5 �ove��e� ��� 2�1�

HT66F488/HT66F489A/D Flash MCU with EEPROM

HT66F488/HT66F489A/D Flash MCU with EEPROM

Copy�ight© 2�1� �y HOLTEK SEMICO�DUCTOR I�C.

The info��ation appea�ing in this Data Sheet is �elieved to �e accu�ate at the ti�e of pu�lication. Howeve�� Holtek assu�es no �esponsi�ility a�ising f�o� the use of the specifications described. The applications mentioned herein are used solely fo� the pu�pose of illust�ation and Holtek �akes no wa��anty o� �ep�esentation that such applications will �e suita�le without fu�the� �odification� no� �eco��ends the use of its p�oducts fo� application that �ay p�esent a �isk to hu�an life due to �alfunction o� othe�wise. Holtek's p�oducts a�e not autho�ized fo� use as c�itical co�ponents in life suppo�t devices o� syste�s. Holtek �ese�ves the �ight to alte� its products without prior notification. For the most up-to-date information, please visit ou� we� site at http://www.holtek.co�.tw.