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Adoption of single-sided adhesive tape to improve thermal-cycling reliability in plastically-encapsulated semiconductor devices Seong-Min Lee * Department of Materials Science and Engineering, University of Incheon, 12-1 Songdo-dong, Yeonsu-gu, Incheon 406-772, Republic of Korea article info Article history: Received 29 June 2010 Received in revised form 4 February 2011 Accepted 14 March 2011 Available online 21 March 2011 Keywords: Tape Lead-on-chip Adhesive layer Thermal-cycling Reliability abstract A more advanced tape structure was designed to improve the thermal-cycling reliability of the semi- conductor devices packaged using the LOC die attach technique. The thermal-cycling test indicates that the replacement of the conventional DSAT by the advanced SSAT is very effective for suppressing the propagation of the pre-existing cracks induced at the device edge prior to the reliability test. This is because the complete elimination of the lower-sided adhesive layer can reduce the thermal-cycling induced stress level on the device pattern. Herein, the removal of the lower-sided adhesive layer indi- cates its substitution with the base layer with many through-holes, which will be inltrated by the single-sided adhesive material due to capillary action. Thus, if a base layer having a value of CTE close to silicon is adopted, the thermal-cycling reliability of corresponding semiconductor devices will be maximized due to much reduced thermal displacement-induced stress level. Consequently, the present work suggests that the use of a single-sided adhesive tape might offer greater reliability range for the structural modication or material selection of the active pattern in plastic packages. Ó 2011 Elsevier B.V. All rights reserved. 1. Introduction A very ductile double-sided adhesive tape has been used for the mounting of a lead-frame on the active surface of the semi- conductor device packaged by the LOC (Lead-on-Chip) technique [1e 7]. However, it has been reported that the tape (a ¼ 25 ppm/ C) results in many thermal cycling-induced reliability problems due to its large thermal expansion compared to the silicon device (a ¼ 2.3 ppm/ C) [1,2]. Thus, in this work, the double-sided adhe- sive tape is replaced by a newly invented tape for fundamentally solving tape-induced reliability problems in plastically-encapsu- lated semiconductor devices [6]. The conventional tape structure consists of one hard base layer sandwiched by two ductile adhesive layers. The upper adhesive layer adheres to the lead-frame and the lower adhesive layer adheres to the silicon device. The adhesive layer has a very large thermal expansion coefcient of approxi- mately 50 ppm/ C. It has been known that the lower adhesive layer, which is directly attached on the device pattern, causes various thermal mismatch-induced reliability problems [1,2]. In order to solve fundamentally such adhesive-related reliability problems, the author invented an advanced tape structure [6]. In the newly invented tape, the trouble-shooting lower adhesive layer is completely excluded, and instead the base layer is designed to have many through-holes. Then, the adhesion between the base layer and the device pattern is done by the adhesive lling through- holes. The newly invented tape is called a single-sided adhesive tape. This work represents how effectively the single-sided adhesive tape contributes to the improvement of thermal cycling- induced reliability of semiconductor devices with the LOC pack- aging structure. 2. Experiments All of the test devices were prepared through conventional VLSI circuit fabrication. Al alloys containing 1% Si were sputter- deposited to a thickness of 0.8 mm on thermally grown oxide (SiO 2 ) and then passivated by the PECVD (Plasma-Enhanced- Chemical Vapor Deposition) technique [2]. Passivation materials consist of Si 3 N 4 of 4000 A in thickness. Many devices were assembled in plastically-encapsulated packages utilizing an LOC die attach technique, as shown in Fig. 1 [1]. The silicon device size was 5.5 mm 11 mm 0.2 mm and its package dimension was 6.5 mm 13 mm 0.5 mm. In this LOC structure, the Fe-Ni lead- frame of 150 um in thickness is mounted on the top surface of each device using the double-sided adhesive tape of 60 mm in thickness and the single-sided adhesive tape of 40 mm in thickness, respec- tively. The attachment of the lead-frame with a tape on the top surface of each device was done at a temperature little higher than * Tel.: þ82 32 835 8276; fax: þ82 32 835 0778. E-mail address: [email protected]. Contents lists available at ScienceDirect Current Applied Physics journal homepage: www.elsevier.com/locate/cap 1567-1739/$ e see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.cap.2011.03.046 Current Applied Physics 11 (2011) S396eS399

Adoption of single-sided adhesive tape to improve thermal-cycling reliability in plastically-encapsulated semiconductor devices

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Current Applied Physics 11 (2011) S396eS399

Contents lists avai

Current Applied Physics

journal homepage: www.elsevier .com/locate/cap

Adoption of single-sided adhesive tape to improve thermal-cycling reliability inplastically-encapsulated semiconductor devices

Seong-Min Lee*

Department of Materials Science and Engineering, University of Incheon, 12-1 Songdo-dong, Yeonsu-gu, Incheon 406-772, Republic of Korea

a r t i c l e i n f o

Article history:Received 29 June 2010Received in revised form4 February 2011Accepted 14 March 2011Available online 21 March 2011

Keywords:TapeLead-on-chipAdhesive layerThermal-cyclingReliability

* Tel.: þ82 32 835 8276; fax: þ82 32 835 0778.E-mail address: [email protected].

1567-1739/$ e see front matter � 2011 Elsevier B.V.doi:10.1016/j.cap.2011.03.046

a b s t r a c t

A more advanced tape structure was designed to improve the thermal-cycling reliability of the semi-conductor devices packaged using the LOC die attach technique. The thermal-cycling test indicates thatthe replacement of the conventional DSAT by the advanced SSAT is very effective for suppressing thepropagation of the pre-existing cracks induced at the device edge prior to the reliability test. This isbecause the complete elimination of the lower-sided adhesive layer can reduce the thermal-cyclinginduced stress level on the device pattern. Herein, the removal of the lower-sided adhesive layer indi-cates its substitution with the base layer with many through-holes, which will be infiltrated by thesingle-sided adhesive material due to capillary action. Thus, if a base layer having a value of CTE close tosilicon is adopted, the thermal-cycling reliability of corresponding semiconductor devices will bemaximized due to much reduced thermal displacement-induced stress level. Consequently, the presentwork suggests that the use of a single-sided adhesive tape might offer greater reliability range for thestructural modification or material selection of the active pattern in plastic packages.

� 2011 Elsevier B.V. All rights reserved.

1. Introduction

A very ductile double-sided adhesive tape has been used for themounting of a lead-frame on the active surface of the semi-conductor device packaged by the LOC (Lead-on-Chip) technique[1e7]. However, it has been reported that the tape (a ¼ 25 ppm/�C)results in many thermal cycling-induced reliability problems due toits large thermal expansion compared to the silicon device(a ¼ 2.3 ppm/�C) [1,2]. Thus, in this work, the double-sided adhe-sive tape is replaced by a newly invented tape for fundamentallysolving tape-induced reliability problems in plastically-encapsu-lated semiconductor devices [6]. The conventional tape structureconsists of one hard base layer sandwiched by two ductile adhesivelayers. The upper adhesive layer adheres to the lead-frame and thelower adhesive layer adheres to the silicon device. The adhesivelayer has a very large thermal expansion coefficient of approxi-mately 50 ppm/�C. It has been known that the lower adhesive layer,which is directly attached on the device pattern, causes variousthermal mismatch-induced reliability problems [1,2]. In order tosolve fundamentally such adhesive-related reliability problems, theauthor invented an advanced tape structure [6]. In the newlyinvented tape, the trouble-shooting lower adhesive layer is

All rights reserved.

completely excluded, and instead the base layer is designed to havemany through-holes. Then, the adhesion between the base layerand the device pattern is done by the adhesive filling through-holes. The newly invented tape is called a single-sided adhesivetape. This work represents how effectively the single-sidedadhesive tape contributes to the improvement of thermal cycling-induced reliability of semiconductor devices with the LOC pack-aging structure.

2. Experiments

All of the test devices were prepared through conventionalVLSI circuit fabrication. Al alloys containing 1% Si were sputter-deposited to a thickness of 0.8 mm on thermally grown oxide(SiO2) and then passivated by the PECVD (Plasma-Enhanced-Chemical Vapor Deposition) technique [2]. Passivation materialsconsist of Si3N4 of 4000 �A in thickness. Many devices wereassembled in plastically-encapsulated packages utilizing an LOCdie attach technique, as shown in Fig. 1 [1]. The silicon device sizewas 5.5 mm � 11 mm � 0.2 mm and its package dimension was6.5 mm � 13 mm � 0.5 mm. In this LOC structure, the Fe-Ni lead-frame of 150 um in thickness is mounted on the top surface of eachdevice using the double-sided adhesive tape of 60 mm in thicknessand the single-sided adhesive tape of 40 mm in thickness, respec-tively. The attachment of the lead-frame with a tape on the topsurface of each device was done at a temperature little higher than

Page 2: Adoption of single-sided adhesive tape to improve thermal-cycling reliability in plastically-encapsulated semiconductor devices

Lead-frameSilicon chip Tape

Fig. 1. Schematics showing the cross-sectional view of the LOC package structure.

Table 2Information on tape materials.

Materials Coefficient of thermalexpansion (ppm/�C)

Adhesive layer Enhanced polyimide 50Base layer Reinforced resin 20

S.-M. Lee / Current Applied Physics 11 (2011) S396eS399 S397

200 �C. For the single-sided adhesive tape structure, the attachmenttemperature was set to allow adhesive materials effectively to fillinto the through-holes of the base layer. The density of holes(of 10 mm in diameter) in the base layer was about 10%.

In order to investigate the effect of tape structure change on thethermal-cycling reliability of the device pattern, all device patternson the wafer scribe region were designed such that they would beeasily exposed to sawing-induced damage. That is, all wafers weremechanically sawed in order to induce pre-existing cracks along theedge regions of diced devices. The position of these cracks corre-sponded to the saw-blade contact region. Thermal cycling-inducedstresses would concentrate themselves initially in the vicinity ofthese cracks. The cracks could propagate into the inside of thedevices due to a difference in thermal expansion between the tapeand the silicon device during thermal-cycling. Devices, with similarpre-determined crack length of 10 mm,were selected prior to all testsand then, were classified into 3-groups. A-group was not plasticallyencapsulated (i.e. all specimens in this group have no tape), B-groupwas packaged with the single-sided adhesive tape, and C-groupwas assembled with the double-sided adhesive tape. See Table 1.The information on tape materials is also shown in Table 2.

The resulting test specimens underwent thermal displacement-induced fatigue at a temperature range of �65/150 �C withina 30 min time period, as shown in Fig. 2. For each set of experi-ments, nominally identical specimens were placed in the thermal-cycling chamber. Once the pre-determined number of thermalcycles (i.e. 200, 400, 600, 800, 1000 cycles) was reached, the cor-responding specimens were decapsulated and inspected under anoptical and scanning electron microscopes (OM and SEM) toidentify crack lengths.

3. Results

The schematic drawing of two different tape structures is shownin Fig. 3. The conventional DSAT (Double-Sided Adhesive Tape)structure with one base layer, both of whose surfaces are coveredby adhesive materials, is illustrated in Fig. 3a. The SSAT (Single-Sided Adhesive Tape) structure with one base layer, whose singleside is coated with adhesive materials, is represented in Fig. 3b. Ingeneral, the adhesive material has much greater coefficient inthermal expansion than the silicon device, by greater than 25-fold[1]. Hence, if the adhesive layer is directly attached to the activepattern of the silicon device, it can result in a very large thermalmismatch-induced stress on the pattern during thermal-cycling[1]. On the other hand, in the case of a single-sided adhesive tape,the mounting of the lead-frame on the active pattern is done by theadhesive material occupying the through-holes of its base layer.The resulting thermal expansion of the adhesive can be effectivelyaccommodated by the hard base during thermal cycling. As a result,

Table 1Classification of test specimens.

Plastically-encapsulation Pre-existing cracklength (mm)

Tape structure

A-group No w10 NoneB-group Yes w10 SSATC-group Yes w10 DSAT

the stress level is expected to be lower on the active pattern of thedevice with the single-sided adhesive tape. Based on this idea,3-groups of the devices with the pre-existing cracks of approxi-mately 10 mm in length, which result from wafer sawing, werethermally cycled to investigate how effectively the absence of thetape or the modification of the tape structure prevents the propa-gation of the pre-existing cracks. The crack length in the semi-conductor pattern layers was estimated as a function of thermalcycles for each group. Measured crack length as a function of thenumber of thermal cycles, as shown in Fig. 4, indicates that there isno evidence for the growth of the pre-existing cracks in A-group(which has no tape) even after 1000 cycles. On the other hands, thepropagation of the pre-existing crackswas observed for B-group andC-group after thermal-cycling, both of whose devices are plasticallyencapsulated with tapes (SSAT or DSAT). Now, note that largervariations (due to rapid crack growth) were observed at the latterstages of the thermal-cycling tests only for C-group. Such high crack-propagation rates (in C-group) should be due to the large thermalcontraction of the lower adhesion (50 ppm/�C) of the DSAT, whichhas a much larger thermal expansion coefficient than the silicondevice (2.3 ppm/�C). Thus, replacement of the lower adhesive witha base layer with a lower CTE (Coefficient of Thermal Expansion), asshown in Fig. 3b, should reduce the crack growth rate.

The edge regions of the devices of each group after 1000 thermalcycles are shown in Fig. 5. From Fig. 5a, the pre-existing cracks oflengths of 10 mm, which result from wafer sawing, are apparent.Fig. 5b shows that even though larger cracks at a length range of30e40 mmwere investigated in B-group, the damage aspect in thedevice pattern of C-group was quite different from that of B-group.That is, in the deviceswith theDSAT (C-group), the edge patternwasalmost peeled off to expose its underlying layer, as shown in Fig. 5c,while no evidence of such severe damage was found in the devicepatternwith the SSAT (B-group). In the devices of C-group, the tip ofthe pre-existing cracks would be probable sites for stress

Fig. 2. Thermal cycling profile.

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Fig. 3. Schematics showing two different tape structures: a) double-sided adhesivetape, and b) single-sided adhesive tape.

S.-M. Lee / Current Applied Physics 11 (2011) S396eS399S398

concentration during the thermal deformation of the lower adhe-sive. Thismicroscopic examination clearly indicates that the deviceswith the SSAT (B-group) is less likely to be exposed to potentialthermal cycling-induceddamage than thatwith theDSAT (C-group).

4. Discussion

It can be qualitatively estimated how much the adoption ofa SSAT instead of a DSAT reduces the thermal displacement-induced stress induced on the device pattern of a silicon chipduring the cooling portion of thermal-cycling [6]. Imagine that a

Fig. 4. Measured crack length as a function of the number of thermal cycles: A-grouprepresents devices with no tape, and B-group indicates devices with SSAT, and C-groupincludes devices with DSAT.

Fig. 5. Scanning electron micrographs showing the edge regions of the devices after1000 thermal cycles: a) A-group (with no tape), and b) B-group (with SSAT), and c) C-group (with DSAT).

thin film is sandwiched between a tape and a silicon chip. Then, theshear stress due to the thermal difference between the tape and itsunderlying silicon is theoretically estimated as in the following [1].

s ¼ ða2 � a1ÞTGsinhb c t

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiGt

�1

E1t1þ 1E2t2

�s !coshb L

(1)

where, c ¼ distance from the pattern center; L ¼ silicon length;(a2ea1) ¼ difference in the coefficient of thermal expansionbetween tape and silicon; E1 ¼ elastic modulus of silicon;E2 ¼ elastic modulus of tape; t1 ¼ silicon thickness; t2 ¼ tape

Page 4: Adoption of single-sided adhesive tape to improve thermal-cycling reliability in plastically-encapsulated semiconductor devices

S.-M. Lee / Current Applied Physics 11 (2011) S396eS399 S399

thickness; t ¼ pattern thickness; G ¼ shear modulus of pattern;

T ¼ temperature; b ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiGt

1

E1t1þ 1E2t2

!vuutWe see from this equation that the magnitude of the maximum

shear stress induced at the edge of the device pattern (where pre-existing cracks exist) depends on various factors such as thethermal expansion coefficient of each layer, layer thickness, elasticmodulus of each layer and so on. One of the most important factorsin determining the magnitude of the maximum shear stress is thethermal expansion mismatch between the tape and the silicondevice. The thermal expansion coefficient of the base film of thetape generally has a value several times lower than that of theadhesive layer. Thus, it is clear that the replacement of the lower-sided adhesive layer by the base layer will reduce the shear stresslevel due to much lower thermal expansion mismatch. In otherwords, if the base layer has a much lower value in the coefficient ofthermal expansion (abase ¼ 5 � 10�6/�C), the corresponding devicepatterns would be subjected to much less tape-induced stress.Since it is not technically difficult for the base layer to have a muchlower value in the coefficient of thermal expansion, the thermalcycling-induced reliability of the device would be maximized bythe adoption of the SSAT. In addition, in the SSAT structure,a decrease in total tape thickness due to the exclusion of the lower-sided adhesive layer can offset an increase in elastic modulusresulting from its replacement by the harder base film.

5. Summary

In this work, all wafers were mechanically sawed in order toinduce pre-existing cracks (approximately of 10 mm in length) alongthe edge regions of diced devices. Thermal cycling-induced stresseswould concentrate themselves initially in the vicinity of these

cracks. Consequently, the cracks could propagate into the inside ofthe devices due to a difference in thermal expansion between thetape and the silicon device during thermal-cycling. Measured cracklength as a function of the number of thermal cycles showed thatthe growth of the pre-existing cracks was not observed in thedevices of A-group (which has no tape) after 1000 thermal cycles.Even through A-group (with no tape) reveals excellent thermal-cycling reliability, it can also cause severe adhesion problems inmounting a lead-frame on a chip surface. Thus, A-group cannot beapplied to real industry. On the other hand, a 4-fold increase incrack length was observed for B-group (with SSAT), while cracklength was increased up approximately to 20efold for C-group(with DSAT). The present experimental result clearly indicates thatcrack propagation could be restricted by manipulating tape struc-ture. In other words, the thermal cycling-induced crack propaga-tion rate could be retarded by the exclusion of the lower adhesivelayer of the DSAT. Thus, the adoption of the SSAT instead of theDSAT would prevent the propagation of a sawing-induced damageinto the inside active pattern to protect reliability degradation. Inbrief, the adoption of the newly designed SSAT might ensure moreimproved reliability in the plastically-encapsulated semiconductordevices, packaged by the lead-on-chip die attach technique.

References

[1] S.M. Lee, J.H. Lee, S.Y. Oh, H.K. Chung, Proceedings of the IEEE ECTC (1995) 455.[2] S.M. Lee, Y.K. Jang, Y.W. Chung, S.M. Sim, K.W. Lee, B.K. Hwang, Mater. Res. Soc.

Symp. Proceedings (1998) p. 427.[3] L.T. Manzione, Plastic Packaging of Microelectronic Devices. Van Nostrand

Reinhold, New York (, 1990, p. 87.[4] S.M. Lee, K.W. Lee, Jpn. J. Appl. Phys. 35 (1996) p. 5465.[5] R.R. Tummala, Fundamentals of Microsystems Packaging. MacGraw-Hill, New

York, 2001, p. 280.[6] S.M. Lee, Lead Frame Design to Improve Thermal Cycling Reliability Korean

Patent No. 10e0201912 (2003).[7] S.M. Lee, Jpn. J. Appl. Phys. 43 (2004) L1068.