Advanced Computer Architecture Lecture 10

Spring 2006

Lillevik 437s06-l10 1University of Portland School of Engineering

EE 437

Advanced ComputerArchitecture

Lecture 10

Project 3 reviews

Project 4 introduction

DMA controller

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Project 3 team reviews

• Team Cat

• Team Dog

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Project 4 overview

• Objective: design a round-robin arbiter for a four-CPU system

• System– Contains four unique CPU models (CPU0,

CPU1, CPU2, CPU3) and programs (pgm0, pgm1, pgm2, pgm3)

– Four bus requests (Breq0, Breq1, Breq2, Breq3)– Four bus grants (Bgnt0, Bgnt1, Bgnt2, Bgnt3)

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Project 4 system

Arbiter

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Project 4 state diagram

00

10

11

01

GBC

D

E

F

HA

Arbiter similar to Grey code counter

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Project 4 program

CPU0

nop

NOTE: Addresses 0, 1 code will change for each CPU

EXAMPLE: CPU 3 will execute 0xa1003

Each CPU writes to Port 10, twice

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Find expected behavior?

• Zero gets bus first

• Writes 0 into Port 10

• CPU 1 gets bus, writes 1 to Port 10

• CPU 3

• CPU 2

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Project 4 trace

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Hard drive DMA

• Assumptions– Operation: Input, or read disk, or read file– HD buffer: represent with a ROM

• Initialization commands– Port 1: start address– Port 2: word count– Port 4: start

• Design contains 5 sections

Project 5

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DMA hardware view

n words n words

adr X

adr X+(n-1)

Memory

I/O device

buffer

System bus adr 0

adr (n-1)

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HD system schematic

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Memory schematic

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DMA controller architecture

Counts up from zero

Counts down to zero Preset counter

Word

Count

Data

Buffer

Memory

Address

Buffer

Address

Control

D

A

C

Xcvr

Xcvr

Xcvr

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Buffer address block

Buffer

Address

BAclr

BAinc

BAdr

BA counts from zero up to N-1

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Data buffer block

Data

Buffer

(ROM)

Data

Ben

BAdr

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Word count block

Word

Count

Data

WCload

WCdecZero

WC counts down from N-1 to zero

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Memory address block

Memory

AddressA

MA counts up from X to X+(N-1)

D

MAload

MAinc

Ben

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Updated block diagram

Word

Count

Data

Buffer

Memory

Address

Buffer

Address

Control

D

A

C

Xcvr

Xcvr

Xcvr

Port1Port2

BAclr

BAinc

WCdec

MAincZero

Ben

Ben

Ben

Cou

nt

one section

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Control section

• Objective: decode the Port instructions, request bus, transfer data across the bus, coordinate the sequence of the other blocks, interrupt CPU when done

• Role– Contains three subsections: decoder, counters,

bus I/F– Bus I/F or FSM similar to CPU model

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Control 1: decode

• Objective: respond to CPU (I/O write) commands– Port 1: start address on D bus– Port 2: word count on D bus– Port 4: start (D bus ignored)

• Role: create signals to load the MA counter, load WC counter, start DMA

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Control section block 1

Decode

LogicC

A Port1 (MAload)

Port2 (WCload)

Port4 (Start)

Decode

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Control 2: counters

• Objective: look for start signal, enter a sequence, repeat, stop when done (WC= =0)

• Role: manipulate the three counters (buffer address, word count, memory address)

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Enables

Start

BAclr

BAinc

WCdec

MAincZero

Counters

One signal?

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Control 3: bus I/F

• Objective: request the bus, drive the bus with data, generate interrupt when done

• Role: – Generate a sequence of Breq, Bgnt, Ben, Ack– Drive the C, A, and D buses– Drive the Int line and wait for Inta

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Bus

I/F

Bgnt

Breq

Int

BenAck

Inta C

Must drive C bus with memory write instruction

Bus interface

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Control input/outputs?

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HD DMA schematic

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Find expected behavior?

• All CPU’s request the bus at the same time

• Arbiter selects one CPU to own bus

• Arbiter issues bus grants in sequence {0, 1, 3, 2}

• First CPU to own bus depends on state of arbiter at that time

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Control input/outputs?

FSM

Clk, Reset

BreqBgnt

Zero Count

Ben

Inta Int

Port4

ClearAck

Documents

Advanced Computer Architecture Lecture 10