Spring 2006

Lillevik 437s06-l15 1University of Portland School of Engineering

EE 437

Advanced ComputerArchitecture

Lecture 15

Project 4 reviewCache design example

Spring 2006

Lillevik 437s06-l15 2University of Portland School of Engineering

EE 437

Project 4 team review

• Team Dog

Spring 2006

Lillevik 437s06-l15 3University of Portland School of Engineering

EE 437

Cache design example

• CPU: B2Logic model

• Memory– 256 x 8, RAM (no ROM)– 4X slower then cache, Rdy signal

• Cache: direct mapped, write-through– Data: 16 x 8, RAM (no delay)

– Tag: 16 x 4 RAM (no delay)

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Lillevik 437s06-l15 4University of Portland School of Engineering

EE 437

System schematic

Spring 2006

Lillevik 437s06-l15 5University of Portland School of Engineering

EE 437

Addressing

Tag Index0347

Memory address

from CPU

indexes

cache

written to

cache tag bits

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Lillevik 437s06-l15 6University of Portland School of Engineering

EE 437

Ram memory

Mrw#

Data

Address A

8

8

Dout

Din Rdy

R/W#

256 x 8

Rdy asserted when memory access complete

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Lillevik 437s06-l15 7University of Portland School of Engineering

EE 437

RAM schematic

G1 initiates a memory

operation

Rdy indicates access time complete

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Lillevik 437s06-l15 8University of Portland School of Engineering

EE 437

General memory design

Main

Cache

Control

Driver

Driver

enable

enable

R/W#

R/W#

hit

System

Bus

Spring 2006

Lillevik 437s06-l15 9University of Portland School of Engineering

EE 437

Find cache block diagram?Trw#

Crw#

Data

Address

Hit

8

8

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Lillevik 437s06-l15 10University of Portland School of Engineering

EE 437

Controller description

• Read hit: read cache data and drive it onto bus

• Write hit: write data/tag into cache and data into memory

• Read miss: read data from memory, drive it onto bus, write data/tag into cache

• Write miss: same as write hit (we will use this fact later in the design)

Spring 2006

Lillevik 437s06-l15 11University of Portland School of Engineering

EE 437

Find controller inputs?

• Hit (not miss)

• Ready

• Adr

• Data

• Read/wr#

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Lillevik 437s06-l15 12University of Portland School of Engineering

EE 437

Find controller outputs?

• Ack

• Cache r/w#

• Tag r/w#

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Lillevik 437s06-l15 13University of Portland School of Engineering

EE 437

State diagram 1

Reset

Memop

Ack

AckAck

Write

Read

Miss

Hit

Ready

Ready

ReadyReady

Difficult to assign adjacent states

Intuitive approach

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Lillevik 437s06-l15 14University of Portland School of Engineering

EE 437

State diagram 2

Reset

Memop

0000

0001 0101

1001

0100

0011

10000010

Write

ReadHit

ReadyReady

Ready

Ready

ReadMiss

AckAck

Ack

Correct, far from optimal

Spring 2006

Lillevik 437s06-l15 15University of Portland School of Engineering

EE 437

Collapsing states

• Objective: – High speed – Simple design

• Combine states: fewest to solve problem

– Write– Read hit– Read miss

Minimal or optimal

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Lillevik 437s06-l15 16University of Portland School of Engineering

EE 437

Find optimal state diagram?

000

c

bd

Reset Write

Read hit

Read miss

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Lillevik 437s06-l15 17University of Portland School of Engineering

EE 437

Spring 2006

Lillevik 437s06-l15 18University of Portland School of Engineering

EE 437

Find cache block diagram?Trw#

Crw#

Data

Address

Hit

A

DinDout

A

4

8

4

8

4

Dout

Din

4

R/W#

16 x 4 tag

16 x 8 cache

low

high

low

R/W#

Match4 high

Spring 2006

Lillevik 437s06-l15 19University of Portland School of Engineering

EE 437

Find controller inputs?

• Reset, clock: standard definitions

• Read: CPU executing a read

• Write: CPU executing a write

• Hit: upper address bits match with tag bits

• Rdy: main memory has completed access

Spring 2006

Lillevik 437s06-l15 20University of Portland School of Engineering

EE 437

Find controller outputs?

• Mrw#: memory read, write

• Mben: memory driving bus

• Crw#: cache read, write (same as Trw#)

• Cben: cache driving bus

• Ack: acknowledge that memory ready

Spring 2006

Lillevik 437s06-l15 21University of Portland School of Engineering

EE 437

Controller block diagram

Cache

controller

Read

Write

Hit

Rdy

Mrw#

Mben

Crw#

Cben

Ack

Mg1

Spring 2006

Lillevik 437s06-l15 22University of Portland School of Engineering

EE 437

Memory system schematic