Agenda

Last Year’s Mission

The Road Ahead

Summary

Last Year’s Mission AccomplishedF

eatu

re S

ize

(mic

ron

)

0

0.2

0.4

0.6

0.8

1

1.2

1990 1992 1994 1996 1998 2000 2002

5v

3.3v

2.5v

1.8v

1.3v

Process Leadership

Density Leadership

Performance Leadership

Price & Value Leadership

Software Leadership

Tra

nsi

sto

r C

ou

nt

(mil

lio

ns)

XC40125XV

XC40150XV

XC40250XV

0.25u Process

Virtex1 Million Gate

7.5

25

50

75

2Q984Q97 3Q98 4Q981Q98

Process Leadership

“samples today”

Density Leadership

XC4085XL

XC40125XV

1997 1998 1999 2000 2002

Virtex

Den

sit

y (s

yst

em g

ates

)

10M Gates

In 2002

Virtex II

10 Million System Gates in 2002!

XC40250XV

10M

2M

1M

250k

180k

500k

Distributed Dual Port RAM I/O Registers Internal Bussing 5V Tolerant I/O 3.3V and 5V PCI

Fea

ture

s 133 MHz Block Dual Port RAM System I/O (LVTTL, SSTL, GTL) Vector Based Interconnect Phase Locked Loops 66 MHz 64-Bit PCI

1998 1999 2000 2001 2002

Reconfigurable Logic On-Chip A/D-D/A Embedded Functions 1GHz Diff. Interface Built-in Logic Analyzer

Architecture Innovation Leadership

* 1/(Tsetup+Tclock-to-out)

Sys

tem

Clo

ck R

ate*

(M

Hz)

0

20

40

60

80

100

120

140

160

180

200

220

240

260

280

300

1995 1996 1997 1998 1999 2000 2001 2002

PC 100 SDRAM Compliant 100 MHz DSP for Wireless

Base Station 33 MHz PCI

Performance LeadershipEnabling high performance solutions first

2002 System Standards233 MHz uP300 MHz RAM I/F

133 MHz SDRAM I/F155 MHz SONET 66 MHz PCI

Quality & Reliability LeadershipWorldclass Today & Tomorrow

Description Industry Standard Xilinx Today Xilinx Future

AOQL* < 25 ppm < 3.4 ppm < 3.4 ppm

Reliability < 100 FITs < 10 FITs < 10 FITs

Moisture JEDEC Level 3 JEDEC Level 3 JEDEC Level 2Resistance

ISO Certification Some 9001 & 9002 9001 & 9002

QML Certification No Yes Yes

Delivery by OFD** No 95% > 95%

* Average Outgoing Quality Level

** Original Factory Commit Date

Chip ScaleFine Pitch BGA

Flip ChipTechnology

PLCC

PGAPQFP

HQFP

BGA

SBGA

1998 2000 2002

Packaging Leadership

1.0mm

<0.8mm

1.27mm

100

300

500

700

1000

Pins

Den

sit

y (S

yst

em G

ates

)

1997 1998 1999 2000 2001 2002

15K

40K

100K

100K unit volume price projections

60K

New Applications• Set Top Box• DVD• Digital Camera• PC Peripherals• Consumer Electronics

New Applications• Set Top Box• DVD• Digital Camera• PC Peripherals• Consumer Electronics

25K

60K

200K

100K

10K Gates/$ in 2002!10K Gates/$ in 2002!

Priced for High-Volume Leadership

1998 1999 2000 2001 2002

Spartan

$395

Spartan

$395

Pri

ce

SpartanXL

$295

SpartanXL

$295

0.35 5LMSpartan-II

< $200

Spartan-II

< $200

0.5 3LM

2.5 Volt

More Features

Without Compromises Pricing competitive with ASICs High Performance On-chip SelectRAMTM

PCI LogiCORE + AllianceCORE

3.3 Volt

5 Volt

*Prices are for 5K system gates, 100K units, -3 speed, Lowest Cost Package

0.25 5LM

SpartanNext Generation

< $150

SpartanNext Generation

< $150

1.8 Volt

0.18

FPGA Price Leadership

Pri

ce

XC9536/XL

$0.80

$7$1.80

$15

2001200019991998 2002

XC95216/XL

Without CompromisesFlexible ISP

tPD = 4ns

Best Pin-Locking

Industry Standard JTAG

* Prices are based on 100Ku+, slowest speed grade, lowest cost package

CPLD Price Leadership

1998 2000 2002

Team Based

Design

Modular Guide

Modular Compile

HDL- Centric Flows

Software Leadership

Largest Installed Base

Highest Circuit Performance with M1

Fastest Timing Driven Compile Times

Shrink-Wrapped FPGA Express Best flows & QOR with leading EDA

vendors

Push Button Design

Release 1.5 is Hot

5 New FPGA/CPLD Families

2x Runtime Improvements

Graphical Constraints Editor

Floorplanner

Automatic Pin Locking

6x Faster Timing Analysis (Kpaths algorithm)

Automatic Clock Skew Handling

New Reporting of Minimum Delays

Voltage and Temperature Speed Pro-rating

Compile Time Leadership

1999 Goal:1 Million Gates in 45 minutes!

Faster CPUs Faster Compile Times Modular Compile

0

20

40

50

60

70

80

90

100

1.4 1.5 2.1 2.2

Min

ute

s*

* 100k System gate designs (200MHz Pentium)

Release

Up to 6X faster than 1.3Up to 6X faster than 1.3

30

10

And with ...

The Road AheadDesign Methodology Evolution

Densi

ty

(sys

tem

gat

es)

25K 100K

500KPro

cess

Tech

nolo

gy

.5u

.35u

.25u

L

DesignDesignFrom Scratch

Reference Design,Generic Core D

Verify

V

Learn

V

Complete FPGACore Solution I

Implement

IL

D

Months

Pre-verified DesignsArea & Timing Optimized

Complete & Flexible DesignLittle Knowledge of Function Required

Complete Core SolutionsReduce Time To Market

Available Only From Xilinx

High Flexibility High Predictability

Intelligent SoftwareImplementation

Intelligent SoftwareImplementationArchitectures

tailored to cores

Architectures tailored to cores

Flexible Core Technology

Flexible Core Technology

High Performance

Xilinx Smart-IPTechnology

Xilinx Smart-IP Delivers

Advantages• Efficient Routing• Predictable Timing• Low Power

Xilinx Segmented Routing

Non-Segmented Routing

Core1

Core2

Architecture Tailored to Cores

RAM availablelocally to the Core

Advantages• Portable RAM based Cores• Improved Logic Efficiency by 16X• High Performance Cores

Segmented Routing

Distributed Memory

Enhances Performance & Predictability

Intelligent SoftwarePre-defined Placement & Routing

Relative Placement

Other Logic Has No Effect on the Core

Fixed Placement & Pre-defined Routing

GuaranteesPerformance

Guarantees I/O &Logic Predictability

Fixed Placement

I/Os

Data sheets

CoreLINX:

SystemLINX:

Web Mechanism to Download New Cores

Third Party System Tools Directly LinkedWith Core Generator

Parameterized Cores

Flexible Core TechnologyOptimal Core Creation & Flexible Core Delivery

Free Software & Free Cores Included (Cores offer over a 1,000,000 Permutations!)

Performance Independent of a Core’s Placement or the number of cores used in the Device

80 MHZ

80 MHZ

80 MHZ

Smart-IP Delivers Design Portability

Performance Independent

of Device Size Non-Segmented Architecture May Experience 30% Performance Degradation

80 MHZ

1998 1999

Sta

nd

ard

Bu

sIn

terf

ac

es

DS

P

Fu

nc

tio

ns

Co

mm

un

ica

tio

n&

Ne

two

rkin

gB

as

e L

ev

el

Fu

nc

tio

ns

•PCMCIA•USB

•CAN Bus•ISA PnP•I2C•PCI 32bit

•Add, Subtract, Integrate•Correlators•Filters: FIR, Comb•Multipliers•Transforms: FFT, DFT•Sin/Cos

•ATM Cell Assembly/Delineation•CRC-16/32•T1 Framer•HDLC•Reed-Solomon, Viterbi•UTOPIA, 25/33/50 MHz

•82xx, UARTs, DMA, •66 MHz DRAM/SDRAM I/F•Memory (RAM, ROM, FIFO)•Micro Sequencer (2901)•Proprietary RISC Processors

•CardBus•FireWire(100-400 Mbps)•PCI 64bit/66MHz•PC104•VME

• DCT• Cordic• DES• Divider• JPEG• NCO

•10/100 Ethernet•1Gb Ethernet•ADSL, HDSL, XDSL•ATM/IP Over SONET•SONET OC3/12

•Microprocessor I/Fs•8051/8031•IEEE 1284•MIPS•133+ MHz SDRAM I/F

• Emerging High- Speed Standard Interfaces

• DSP Processor I/Fs• DSP Functions >

200 MSPS• Programmable DSP

Engines• QAM

• Modems• SONET OC48 • Emerging Telecom and Networking Standards

• Satellite decoders

• Speech Recognition

• Advanced Processors

2000

By 2002: Virtually All Functions Available as Cores

Leader in Core SolutionsXilinx and Partners’ COREs

Xilinx Applications on The Rise

From Standard Products & Gate Arraysto Systems on a Programmable Chip

Simple & Fast Low Cost CPLD Solutions

Isolates User From Interface Issues• Critical Signal Timing• Electrical Interfacing• Control Signal Sequencing (State Machine Design)

Variances In InterfacesSDRAM (i.e. Bank vs. SIMM)Unique System Back-End

Flexible High Density FPGA SolutionsJPEG Compression (70k ASIC Gates + RAM)

FPGA Advantages over Chipsets• Can specify Non-Standard Data-Rate & Pixel Depth• Industrial Temp Range

High Performance2x NTSC Video Resolution1.5x NTSC Pixel Depth

Core FunctionXCS30XL

PricePercentage of Device Used

EffectiveFunction Cost

UART $6.95 17% $1.20

16-bit RISC Processor $6.95 36% $2.50

16-bit, 16-tap Symmetrical FIR Filter

$6.95 27% $1.90

Reed-Solomon Encoder $6.95 6% $0.40

PCI Interface(w/ faster speed grade)

$12.00 45% $5.40

High Value Applications with Spartan

External PLD15K Gates

Co

mp

on

ent

Co

st 1

00K

Un

its

Standard ChipPCI Master I/F

$5

$15

$20

$10

Costs less Than Standard ICs!

Standard Chip Solution >$20

PCI Master I/F

User Design15K Gates

Xilinx PCI Solution <$13.50

1.6

1.2

0.8

0.4

Gig

a-M

AC

s

* Prices based on 50k volume

$192* $9.95*

2 Extra uPs1 Extra uP 3 Extra uPs

Delivers High PerformanceAt a Fraction Of The Cost

• Integrated System Level Tools• Easy Parameterization Tools• Free Parameterization

The Road AheadDesign Methodology Evolution

500K

.25u

.18u

Density(system gates)

ProcessTechnology

1 Million

Designer1Module

DesignReuse

Designer2Module

Designer3Module

Reduces Compile Time & Increases Performance

Xilinx Enables Modular Design

Facilitates Group Design & Reuse

Seamless Integration Between ModulesExtension to leading cores solution

Modular Time SpecsWith industry’s best timing constraint language

Modular Incremental CompileExtensive R&D investment

Fast I/O PerformancePhase Lock Loops155MHz SONET133MHz SDRAM66MHz PCI

Flexible, Fast RAM133MHz External, Block, and Distributed RAMFully Dual Ported (2 independent read/write ports)Configurable Data Widths and DepthsSSTL3 Interface to External RAM

VirtexThe Ideal Platform for Modular Design

Predictably Fast PerformanceVector Based Interconnect10ns Global Signals100MHz+ from all devices

Flexible InterfacesLVTTL, LVCMOSSSTL, GTL, PCIFuture Standards

Virtex Enables System on a Programmable Chip

VHDL DesignEnvironment

Verilog DesignEnvironment CoreGen

Designer#2 DSPDesigner

#1New

ModulesFIFO

133MhzSDRAM

GbitEthernet

66MhzPCI

IP Modules

LogiCore

AllianceCore

CPU

DesignReuse

160 MHz I/O Performance133 MHz Memory Performance

1 Million System Gates

Functional FPGA Equivalence• Support for Complex FPGA Cores• Risk and Resource Reduction• No Re-engineering from FPGA• CLB Integrity Maintained• Planned for 2H 2000 Introduction

FPGAHardWire FpgASIC

HardWire FpgASIC’s The only ASIC solution designed for Virtex

Gbit Ethernet

133Mhz SDRAMLogic

Logic

SDRAM

$0

$50

$100

$150

$200

$250

$300

400K Gates

600K Gates

800K Gates

1 Million Gates

2001 2001 2001 20012002 2002 2002 2002

HardWire FpgASIC 100K unitsVirtex FPGA 50K units

Virtex + FpgASICCost Effective System on a Chip

The Road AheadDesign Methodology Evolution

1Million

10Million

.15u

.18u

System Gates

To

tal

De

velo

pm

ent

Tim

e

10k 100k 1M 10M 100M

Integration Time

Design Time

Increased Integration Time Requires Team Based Design

Xilinx To DeliverTeam Based Design Solutions

Team Oriented Design Mgmt Engineering Change Control

Team Oriented Design Mgmt Engineering Change Control

Module Timing Independence Fixed Timing On a Module

Module Timing Independence Fixed Timing On a Module

Timing Budget Calculator Module Based Timing Redistribution

Timing Budget Calculator Module Based Timing Redistribution

Global Timing Defn & OptimizationGlobal Timing Defn & Optimization

Auto Inter-Team FloorplanningAuto Inter-Team Floorplanning

Real Technology Partnerships

Xilinx Delivers

Committed to Product Leadership

Focused on Complete Solutions

Driving New Applications With Cores

Delivering the Vision