An expert tool for digital circuit design

F. N. Sibai Electrical Engineering Department, University of Akron, Akron, Ohio 44325-3904, U.S.A.

K. L. W a t s o n Electrical Engineering Department, Texas A&M University, College Station, Texas 77843, U.S.A. (Received June 1990)

ABSTRACT

A new CAD tool for digital combinatorial circuit design called DICES and based on artificial intelligence techniques has been developed. It includes a logic synthesizer and minimizer to synthesize and simplify Boolean expressions with an arbitrary number of variables. A rule-based forward-driven expert subsystem is also provided to select the technology and design approach that best satisfy the user's design criteria, including minimization of area/number of gates, propagation delay/speed, cost/number of inputs, power dissipa- tion, and flexibility/ease of modification. The system is implemented in Franz Lisp, running under Vax/Unix on a Vax 11/750. The results which are included in this paper show that DICES yields excellent simplified circuits at the expense of execution speed. Technology and design approach results are also satisfactory.

INTRODUCTION

As integrated circuits exceed the 1M transistors per chip mark, design engineers are faced with the problems of designing large and very complex circuits: mainly, long design time, high product cost, and low reliability. Hence the need to automate the circuit design process by the development of computer-aided design (CAD) tools for circuit design and analysis. DICES ~ is an expert CAD tool for digital combinational circuit design. It is composed of three major components. The first is an interface routine which allows user-friendly communication with the system. The second component is a logic synthesizer and minimizer that synthesizes simplified circuits out of given Boolean expressions. The third component is an expert system 2, a that infers the technology and "physical"

design approach under which the synthesized circuits are to be built. This tool is useful for designing combinatorial circuits because (unlike other tools) it directs the user, after synthesizing the Boolean expressions, to the VLSI placement and wiring tool under which the physical layout of the circuits is to be designed and tested. The block diagram of the DICES system is illustrated in Figure 1.

This tool is implemented to be used as a front-end to several VLSI layout tools such as the Full-Custom, PLA, ROM, RAM, Polycell, and Gate Arrays tools. In the Polycell semi-custom design approach, each gate of the logic-level description of the circuit is replaced by a corresponding physical layout cell from an available library of cells. The Polycell VLSI tool places the cells in a rectangle of acceptable area and then connects the cells together with wires of reasonable length. Similarly, the other VLSI tools yield the physical layout of the circuits under the form of PLAs, ROMs, etc.

Each of these VLSI tools requires a distinct design approach that is efficient only under specific design criteria. For example, adopting the Full-Custom design approach leads to the best possible VLSI layouts with minimal area; however, its costs in terms of time and man-power are too high, and therefore this approach is not efficient when the product volume is low. In this case, using a tool based on a semi-custom design approach and even on the off-the-shelf approach would be more economical. Similarly, the selection of circuit technologies is also very dependent on the design criteria. For example, Bipolar technologies are more convenient if the user is more interested in the circuit speed and in high-current applications such as I/O applications. On the other hand, MOS technologies are more convenient in low-area and low-power applications because their densities are higher and their power dissipations are lower than those of other technologies. Here emerges the role of DiCES's expert subsystem in choosing the best design approach and technology for particular design criteria. A rule base and technology and design approach tables are provided to assist the system in making the proper selection.

DICES accepts Boolean expressions representing the circuits to be synthesized and yields the gate- (or logic-) level description of these circuits. Using then the VLSI tools based on the technology and design approach suggested by DICES would produce the

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An expert tool for digital circuit design: F. N. Sibai and K. L. Watson

S User

Database Canonical Fttncgions

U.~er/Syslem Interface

Figure 7

(

Working Memory

Inference ET, gine

Stagistical Functions

Logic 1 Minimizer

t Logic r

A block diagram of DICES

physical circuit layout ready for manufacturing. The following section introduces the topics of expert systems and artificial intelligence techniques adopted in the building of CAD tools for circuit design.

EXPERT SYSTEMS AND DESIGN AUTOMATION

Automating the design of digital circuits has evolved from the not-so-recent work on finding suitable and efficient algorithms for synthesis and minimization. From the behavioural-level description to the physical-level description, tools have been developed for the purpose of mainly reducing design time, facilitating design changes and enhancing circuit reliability and life time. With advances in AI and the emergence of expert systems, tools started using

AI techniques to incorporate intelligent features. Equipped with a knowledge base and an inference engine, these new expert tools can actually reason and give satisfactory answers even under uncer- tainty. Moreover, they can communicate with the user and explain their thinking or inference process step-by-step. Expert systems are systems which are supposed to behave as human experts. They have a collection of knowledge which is called the rule base when the knowledge is expressed under the forms of IF-THEN rules (that is, IF (condition) THEN (ac t ionl ) (action2) . . . ) . They are also provided with a reasoning mechanism known as the "rule interpreter" or "inference engine" that drives the logical inferences on the rule base, and a memory space where the logical inferences are conducted called the working memory. In addition to the

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reasoning ability, the ability to expand their knowledge base easily, and the ability to offer the user explanations of made inferences, expert systems can deduce and induce knowledge provided that their inference engine is designed to handle two-way inferences. When deducing knowledge, expert systems are said to operate under the forward- chaining mode whereas when inducing knowledge, they are said to operate under the backward- chaining mode. Additions, deletions and any changes made to the rule base are facilitated considerably because of the separation of control and data.

Lisp4, 5 and Prolog are considered to be the two most popular high-level languages for AI applica- tions. The data types which are most commonly manipulated by Lisp are lists, while those most commonly manipulated by Prolog are terms (or strings of characters). Lisp is an interactive functional programming language which adopts the list as its main data structure, e.g. (function_name argument_l aryument 2 . . . ) . The car of a list l, where I is (a b c d), returns the first element a, while the cdr of the list I returns I less its first element, i.e. (b c d). Lisp has been used in the development of expert systems due to its support of symbolic manipulation, and the natural ease of representing and manipulating knowledge in it.

Several expert systems for digital-circuit design have been implemented. CRITTER 6, that "criticizes" digital circuits, and SOCRATES 7, which minimizes circuits, are examples of such systems. In the following sections, each of DICES' components is described.

LOGIC SYNTHESIS

The basic circuit representation in DICES consists of a list whose first element (car) is the name of the output node followed by a list whose car is a logic gate and whose cdr is a list of the inputs to the gate, which can be atoms corresponding to variable names representing circuit input nodes, or lists representing input subcircuits to that node. Note that the gate/input representation is in prefix form, i.e. the gate type identifier precedes all inputs. When entering the Boolean expressions to be synthesized into the system, these expressions are in infix form where the inputs surround the gates they are fed to. For instance, such a Boolean expression is (a AND b AND c). Notice that the gate AND is repeated more than once, in fact, n - 1 times for n

for digital circuit design: F. N. Sibai and K. L. Watson

inputs. This redundancy can be eliminated by putting the expression in prefix form: (AND a b c). Putting the expressions in prefix form also accelerates gate-type identification and circuit simplification. So the first step in the circuit synthesis procedure is to put the entered Boolean expressions expressed in infix form, into prefix form. Then logic simplification transformations can be made on the expressions one by one so as to simplify them. Next, the expressions can be put in Sum of Products (SOP) or Product of Sums (POS) forms depending on whether the AND-OR/NAND-NAND or OR-AND~NOR-NOR forms are requested respectively. However, at this stage, the expressions can be directly put in SOP/POS forms if the OR-AND or AND-OR forms are requested, because applying later a multi-function minimization on the expressions does not impede the OR-AND/AND- OR synthesis. In case the NOR-NOR or NAND- NAND forms are requested, the optional operation of multi-function minimization is conducted before putting the expressions in SOP/POS forms, for the following reason: If the expressions are first put in SOP/POS form and then minimized, they will often not remain in SOP/POS forms after minimization, and here the procedure of putting the expressions in SOP/POS forms must be repeated to express these expressions in NAND-NAND or NOR-NOR forms.

Following the latter step, the grouping and gate-assignment procedures are applied to the expressions. During the grouping phase, gates having more than four inputs are recursively "grouped" into a gate having three inputs on three of its input terminals, and having a similar gate grouping the other remaining inputs on its fourth input terminal. Thus, during that phase, all gates

(R OR Q OR (NOT S) AND E OR F OR G) (a) An example of an input Boolean expression

(OR R (OR e (OR (AND (NOT S) E) (OR F G)))) (b) The expression in prefix form

(OR R Q (AND (NOT S) E) F G) (c) The expression after being flattened

(AND (OR (NOT S) R Q F G) (OR E R e F G)) (d) The expression in POS form

(NOR (NOR (NOTS) R Q F G) (NOR E R Q F G)) (e) NOR-NOR synthesis

(AND (OR (NOT S) R O (OR F G)) (OR E R Q (OR F G))) (e) Grouping

(AND2 (OR2 (OR4 (NOTS) R O F) G) (OR2 (OR4ER O F) G)) (f) Gate assignment

Figure 2 A logic synthesis example

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are allowed to have a maximum of four inputs, and additional gates are added when needed to take care of the extra inputs. This step is necessary to make the process of synthesizing the expressions with discrete components (off-the-shelf approach) pos- sible, for most logic gates commercially available on chips have a maximum fan-in of four. During the gate-assignment step, each gate is replaced by an assigned gate denoting the gate type and the fan-in, e.g. (AND a b c) becomes (AND3 a b c). An example of an expression under synthesis is shown in Figure 2.

LOGIC MINIMIZATION

DICES allows Boolean expressions to go through two levels of minimization: single-function minimi- zation and multi-function minimization. The single-function minimization procedure attempts to simplify the function/expression by itself using the minimization rules such as Absorption, Idem- potency, etc. On the other hand, multi-function minimization involves the simplification of more than one Boolean function/expression. Multi- function minimization procedures attempt to simplify several expressions together at the same time, and tend in this process to discard redundant subexpressions present in those expressions.

Single-function minimization is conducted under the form of logic transformations where an expression or subexpression is replaced by a simpler and cheaper but logically-equivalent expression or subexpression. It is accomplished in two steps. In the first step, pattern-matching code recognizes an expression potentially ready for simplification. In the second step, the expression is replaced by a simplified version. First of all, the expression is scanned for Boolean constants. If any constant is detected, the constant is eliminated and the expression simplified accordingly. Next, Absorption, Complementation and Idempotency rules are applied to the expressions, followed by consensus terms elimination. An optional procedure is available to simplify some expressions into XOR or XNOR expressions.

As far as multi-function minimization in DICES is concerned, the expressions are first simplified each alone, and then common or redundant subexpres- sions are located and eliminated. To achieve this, multi-function minimization conducts the following operations. Here a ~ b denotes a production operation where b is returned as the result of the

L. Watson

operation if the input pattern a is matched in the given Boolean expression. It is assumed that the circuit C8:(C8 (AND a b c)), is already present in the list of circuits.

1. (OR (AND a b c) d) , (OR C8 d)

2. (OR (AND a b) (NOT c)) , (OR C8 (NOT e))

3. (OR (AND a b) (AND (NOT c) a)) , (OR C8 (AND (NOT c) a))

4. (OR (AND a b) (AND b (OR (NOT c) e))) , (OR C8 (AND b (OR (NOT c) e))

The dual form of each rule is also a valid operation. It is clear that this multifunction simplification does not always lead to minimum expressions but, in spite of its shortness and simplicity, it often reduces the number of redundant subexpressions in a very short time.

TECHNOLOGY AND DESIGN APPROACH INFERENCE

Inferring the technology and the design approach is accomplished by a rule interpreter, a rule base, and some technology and design approach tables providing all necessary knowledge. These tables contain ratings of general design criteria encom- passing minimization of delay time/speed, area/ number of gates, static power consumption, cost/ number of inputs, and flexibility/ease of modifica- tion, for each technology and design approach. The rule structure consists of a list with the rule name as the first element, followed by the rule goal, the antecedent or condition part, and ending with the consequent or action part of the rule. The rule goal describes the domain of application of the rule or the goal towards which the system will be heading after the action or consequent part of the rule is executed, i.e. after the rule is fired. For instance, " INFERTECH" and "INFERDES" are examples of goals, the former representing the goal of inferring the circuit technology and the latter representing the goal of inferring the design approach.

The third rule element is the antecedent or condition part, implemented as a Lisp function returning one of the values True/Nil. Once it returns True, the rule is said to be triggered and the fourth element of the rule (action) consisting of another Lisp function is executed. This action brings the system closer to the set goal(s). Now, how does the

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system know which rules to trigger and which goals to reach?

If the user asks the system to infer the technology and design approach that best satisfy the design criteria stressed by the user, then the system stores in its working memory a goal assertion list of the following form

(* GOAL1)

thus telling the system to trigger all rules whose goal is GOAL1 provided that their antecedent part evaluates to True.

The rule base is implemented as a list having as elements sublists, each representing a distinct rule or a goal assertion list. At the beginning of the inference process, the rule base is loaded onto the working memory following the already-loaded initialization rules, and preceding the loading of the meta-rules. The initialization rules are therefore the first rules in the working memory, so that initialization of the system can take place right at the beginning. The meta-rules are the last rules to be executed during the inference cycle. They contain control information useful for proper operation of the system. For example, they can detect idle cycles and terminate the execution when no more knowledge can be inferred from the available facts, and invoke the dead-end-resolver which asks the user for more facts and data when needed. The conflict-resolution facility is very simple, for the first rule satisfying the goal is fired directly after it triggers, thus reducing the complexity and length of the inference-engine facility.

Inferring the technology and design approach is based on two sets of information: the user ratings of the design criteria and the technology and design approach look-up tables. The user ratings of the design criteria are integers between 3 and - 3 indicating the amount of importance of each design criterion. The look-up tables contain technology and design approach ratings of all design criteria. A selecting function is provided to select the technology and design approach that best satisfy the user's requirements, i.e. it selects the technology and design approach whose ratings of the design criteria are the closest possible to the user's ratings.

A similar approach is followed in the selection of the best circuit version. In addition to allowing the user to enter a particular form in which the circuits are to be synthesized, DICES also provides the user with the option of letting the system select the best circuit form satisfying the user's ratings of the design

for digital circuit design: F. N. Sibai and K. L. Watson

criteria. DICES in the second option synthesizes four forms of each expression: the OR-AND, AND-OR, NOR-NOR and NAND-NAND forms. Then, functions that compute the longest propaga- tion time, power dissipation, number of gates (area) and number of inputs (cost) are called and a measure, called the "Rejection Factor" (RF), indicating how close the particular version of the circuit is to the user's requirements is associated with each of the four synthesized versions of the expression. A simple sorting routine sorts the versions in terms of their RFs (the lower the RF, the better the version) and returns the version with the lowest RF as the system's best guess.

USER/SYSTEM INTERFACE

Right after entering the system, the user is initially prompted to enter his/her name and then asked to enter the Boolean expressions to be synthesized into circuits. Next, DICES asks the user to enter the design criteria ratings and weights. The ratings rate the design criteria from low ( - 3 ) to high (+3) , while the weights provide information on how important one design criterion is with respect to the others. If the user enters "x" (for don't care), default ratings and weights are assigned to the r (rating) and w (weight) lists. The user can also choose not to make use of the rule-based system, and this is the case when the user already knows the technology, design approach and circuit form he/she wants, and uses DICES only to simplify the expressions and synthesize the circuits. Also, the user can allow DICES to choose for him/her the technology and design approach which best signify the design criteria rated by the user. Here, DICES forms the goal assertion list INFERTECH (or INFERDES or both) and stores it in the working memory, thus telling the rule-based system that one of the required goals to satisfy is to infer the technology (or design approach or both). Next, DICES asks the user whether he/she wants to choose the circuit form or not. If the user responds with a "no" or "x ", DICES chooses the default case which is the NAND-NAND form. As the result of the user asking the system to select the best circuit form, again, a goal assertion list ( INFERFORM in this case) is stored in the working memory, informing the rule interpreter to synthesize, during execution, the circuits under several forms and to select the most convenient form. Among the possible circuit

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( ( ( (NORA) AND (NOTB) AND CAND D) OR ((NORA) AND (NOr B) AND C AND (NOr O)) OR ((NOT A) AND B AND (NOT C) AND D) OR ((NOT A) AND B AND C AND D) OR ((NOT A) AND B AND C AND (NOT D)) OR (A AND B AND (NOT C) AND D) OR (A AND B AND C AND D) OR (A AND (NOT B) AND C AND D)

) )

(a) Expression fl

A_ oc l (b) Equivalent minimized expression f~

Figure 3 A sample of expressions minimized by DICES

forms the user can choose from are:

1. NAND-NAND 2. NAND-NAND with NOT 3. NOR-NOR 4. NOR-NOR with NOT 5. OR-AND 6. OR-AND with XOR and XNOR 7. AND-OR 8. AND-OR with XOR and XNOR.

After the form selection step, DICES simplifies the Boolean expressions if the user requests this, and then synthesizes the circuits if the user has selected a specific form. The rule-based system takes over and attempts to satisfy the goals set by the user. DICES offers the user the choice of a wide variety of commands in a Menu. The self- explanatory commands are:

1. Restart/reinitialize 2. Exit the system 3. Add a rule to the working memory 4. Add a rule to the rule base 5. Delete a rule from working memory 6. Delete a rule from rule base 7. Save current working memory

8. Enter additional Boolean expressions 9. Exit menu and continue

10. Display a rule from the working memory 11. Display current working memory 12. Display current list of circuits 13. Display current technology 14. Display current design approach.

RESULTS

To test the rule-based system, by rating the minimization of area higher than the other criteria, DICES suggested that the I3L/I2L technology and the Full-Custom design approach were the best technology and design approach. Similarly, by emphasizing the minimization of power dissipation criterion over the others, CMOS and the Gate Arrays approach, followed closely by the PLA approach, were the most convenient choices.

Figures 3-5 show expressions simplified and synthesized by DICES. Figure 3a shows the Boolean expression

ABCD + ABCD + ABCD + ABCD + ABCD

+ ABCD + ABCD + ABCD

to be simplified. Figure 3b shows the simplified circuit obtained by DICES (AC+CD+BD). In Figure 4a, the expression A B E + E B A + F is to be minimized. Figure 4b shows the equivalent expression obtained by DICES (A(BGE)+ F). Figure 5 shows a list of circuits given to DICES where f l is the AND of E and F, f2 is the AND of A, B and C, and f3 is AB+ CA+EF. This list of circuits was passed to the multi-function minimization proce- dure, which yielded the list of minimized circuits in Figure 5b. The graphical representation of that list of minimized circuits is given in Figure 5c. The replacement of AB in f3 by ABC is justified by the presence of the CA term in f3 since [ABC + CA = A(BC + C) = A(B + C) = AB + AC].

The only problem encountered is the execution- speed problem, for the execution time for minimizing the second expression (Figure 5) was 15.78 CPU seconds, not including 2.85 seconds spent on garbage collection. Mayaram s studied the execution of programs written in several high-level

(OR (AND A B (NOTE)) (AND E (NOT B) A) F) (a) Given expression

(OR (AND A (XOR B E)) F) (b) Output expression

Figure 4 XOR/XNOR simplification

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((fl (AND E F)) (f2 (AND A B C)) (f3 (OR (AND A B) (AND (NOT C) A)(AND E F))) (a) Given list of circuits

((fl f4) (f2 fs) (f3 (OR f, (AND (NOT C) A) fs) (f, (AND E F)) (f5 (AND A B C)))

(b) Circuits in (a) after multi-function minimization

A

f2 A

I

(c) Graphical representation of the minimized circuits

Figure 5 An example of multi-function minimization

/3

languages including Lisp on several machines including a Vax 11/780. He concluded that comparing programs written in Lisp and running on a Vax 11/780 to programs written in other languages but running on the same machine is unfair. For this reason, comparison of execution time with other tools is not given in this paper. In addition to speed performance degradation due to Lisp, pattern matching is very time-consuming, suggesting that the code dedicated to that operation needs to be improved in terms of run time.

Leaving aside the issue of run time, the system provided several advantages over other available tools:

1. DICES can satisfy more than one design criterion at a time, unlike other tools such as SOCRATES v that always gives the minimization of time criterion the highest priority and CADTOOLS 9 whose primary concern is to minimize the number of gates, etc.

2. DICES can synthesize circuits under several forms, unlike SWAMI 1° or PHIPLA 11, for example, that can obtain only the SOP form.

3. DICES is implemented in such a way as to facilitate expansion, for addition of rules or functions can be done very easily.

4. DICES produces simplified circuits for expres- sions of arbitrary length. For example, there is no restriction on the allowed number of variables/inputs in the Boolean expressions to be entered.

5. At any point of the minimization process, the

user can actually see expressions being simplified, because the minimization algorithm is simple and does not deal with prime implicants, essential prime implicants, or adjacencies concepts, but only with local transformations on the expres- sions. This is particularly desirable in a circuit synthesis/minimization learning environment in which the local transformations on the expression after each step of the simplification can be observed by the learner.

CONCLUSIONS

An expert tool for combinational circuit design has been presented. Results show that the tool yields excellent simplified circuits with convenient technol- ogy and design-approach selections. Minimization time of the expressions was not as low as expected and was increased by Lisp and the pattern-matching algorithms. A rule base, inference engine, working memory, and database canonical functions support- ing retrieval, addition, deletion of data/rules and statistical functions that compute the time delay, static power dissipation, area and cost of a circuit were implemented. What is currently missing is an explanation facility providing explanations of why one specific inference course has taken place, rather than another. To improve the execution speed, the program can be loaded onto a Lisp-based machine such as the Symbolics 3600, and pattern-matching heuristics may be considered. Also, future work may include: (1) the addition of rules for the minimization and synthesis of sequential networks; (2) graphics capabilities to enhance CAD features; (3) increasing the reasoning power of the system by addition of backward-chaining inference capabili- ties; (4) integrating the tool with VLSI layout packages and developing interface software to all VLSI placement and wiring tools; (5) investigating the loading of the system onto faster machines for speed improvement; and (6) recoding some key parts of the minimization and pattern-matching algorithms in order to reduce the execution time.

REFERENCES

1 Sibai, F. N. Dices: An expert system for digital combinational circuit design, M. S. Thesis, Texas A&M University, College Station, TX, USA (1986)

2 Barr, A. and Feigenbaum, E. A. The Handbook of Artificial Intelligence. Kaufman, Los Altos, CA (1982)

3 Hayes-Roth, F., Waterman, D. and Lenat, D. Building Expert Systems. Addison-Wesley, Reading, MA (1983)

4 Charniak, E., Riesbeck, C. and McDermott, D. Artificial Intelligence Programming. Erlbaum, Hillsdale, New Jersey (1980)

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5 Foderaro, J. K., Sklower, K. L. and Layer, K. The Franz Lisp Manual. EECS Department, University of California, Berkeley (1983)

6 Kelly, V. E. The Critter system: Automated critiquing of digital circuits designs. Proceedings of the 21st Design Automation Conference, Albuquerque, NM, pp. 419-425 (1984)

7 DeGeus, A. J. and Cohen, W. A. Rule-based system for optimizing logic. IEEE Design and Test of Computers, 2 (4), 22-32 (1985)

8 Mayaram, K. and Pederson, D. O. Circuit simulation in Lisp. IEEE ICCAD-84, pp. 24-26 (1984)

9 Shell, E. and Mercer, M. CADTOOLS: A CAD algorithm development system. Proc. 22nd Design Automation Conf., Las Vegas, Nevada, pp. 658-666 (1985)

10 Rowen, C. and Hennessy, J. L. SWAMI: A flexible logic implementation system. Proc. 22nd Design Automation Conf, Las Vegas, Nevada, pp. 169-175 (1985)

11 Van Laarhoven, P. J. M. et al. PHIPLA--A new algorithm for logic minimization. Proc. 22nd Design Automation Conf., Las Vegas, Nevada, pp. 739-743 (1985)

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