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540 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 17, NO. 7, JULY 2007 An Extension of the Classical Method to Design High Efficiency Microwave Class E PAs J. R. Loo-Yau, Associate Member, IEEE, Hugo Ascencio-Ramírez, and J. A. Reynoso-Hernández, Member, IEEE Abstract—This letter presents an extension of the analytical method proposed in [4] to determine the impedance of the load network of a class E power amplifier (PA). The extended method lies in a new analytical expression for calculating the output load network, which allows for the parasitic elements and the time that the input signal takes for saturating the field effect transistor (FET). To demonstrate the usefulness of the extended method, two class E PA at 6 GHz, 4 V were designed and compared. One of them was designed using the classical method, while the second was designed using the extended method. Both amplifiers were fabricated on a Duroid substrate and the transistor used was a GaAs FET FLK057WG. The amplifier, designed with the extended method, exhibits an improvement on the power added efficiency of 18.6% in comparison with the amplifier designed using the classical theory. Index Terms—Class E power amplifier (PA), high efficiency PA. I. INTRODUCTION S WITCHED mode amplifiers are in theory very high effi- ciency amplifiers, and one of the most popular switched mode amplifiers is the class E [1] developed by N. O. Sokal and A. D. Sokal in 1975. Analytical expressions to determine the output load network have been reported [1]–[3]. However, in all these works the transistor is assumed to be an ideal switch and, therefore, experimental adjustments are required to attain the best performance. At very low frequencies, this task be- comes very easy with the aid of an oscilloscope. However, at microwave frequencies this task is not as evident as in the low frequency case. In this sense it is desirable that in the design method the analytical expression for determining the output load network provides a value close to the optimum. So, in this work, a new expression for determining the load network of the class E power amplifier (PA) is presented. This new expression allows for the parasitic elements of the field effect transistor (FET) and the time that a non-square input signal takes to saturate the transistor. Two amplifiers at 6 GHz were fabricated using a Fu- jitsu GaAs FET FLK057WG; one with the classical approach proposed in [4] while the other was designed with the extended Manuscript received December 6, 2006; revised March 12, 2007. This work was supported by CICESE and CONACYT under Project 39835-Y, México. J. R. Loo-Yau is with the Centro de Investigación y Estudios Avanzados del I.P.N unidad, Guadalajara, México (e-mail: [email protected]). H. Ascencio-Ramírez and J. A. Reynoso-Hernandez are with the Departa- mento de Electrónica y Telecomunicaciones de la División de Física Aplicada del Centro de Investigación Científica y de Educación de Ensenada (CICESE), Ensenada, México (e-mail: [email protected]). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LMWC.2007.899322 Fig. 1. FET small signal equivalent circuit. method proposed in the present work. The amplifier designed with the extended method, without any post fabrication circuit tuning process, presents an improvement on the power gain and power added efficiency (PAE) of 4.75 dB and 18.57%, respectively. II. OUTPUT LOAD NETWORK The key to designing a high efficiency class E PA is the output load network. The output load network establishes the zero voltage switching (ZVS) condition in the transistor. This means that the voltage and the current in the transistor never overlap. In [4], the output load network is calculated using (1) where is the frequency of operation and is the output ca- pacitance of the transistor. Equation (1) is derived assuming that the transistor is an ideal switch where the principal parameter is . However, there are two problems that were not addressed in previous works [4], [5]. The first one is about the extraction of and the second is related to the effect of parasitic ele- ments on the performance of the class E PA at high frequency, which modify the performance of the transistor, and therefore, the assumption of an ideal switch to model the transistor is not entirely valid. Therefore, the following criteria are proposed in order to clarify the design method. A. FET Output Capacitance Most of the literature [4], [5] defines the drain source capac- itance as the output capacitance and ignores the parasitic (see Fig. 1). This definition seems to us incorrect because the output capacitance of the FET is strongly affected by the in- trinsic and parasitic capacitances. Assuming that the transistor equivalent circuit consists of intrinsic and parasitic elements, the output capacitance of the FET results from the contribution of the intrinsic output capacitances, and , and the parasitic 1531-1309/$25.00 © 2007 IEEE

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Page 1: An Extension of the Classical Method to Design High Efficiency Microwave Class E PAs

540 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 17, NO. 7, JULY 2007

An Extension of the Classical Method to DesignHigh Efficiency Microwave Class E PAs

J. R. Loo-Yau, Associate Member, IEEE, Hugo Ascencio-Ramírez, and J. A. Reynoso-Hernández, Member, IEEE

Abstract—This letter presents an extension of the analyticalmethod proposed in [4] to determine the impedance of the loadnetwork of a class E power amplifier (PA). The extended methodlies in a new analytical expression for calculating the output loadnetwork, which allows for the parasitic elements and the timethat the input signal takes for saturating the field effect transistor(FET). To demonstrate the usefulness of the extended method,two class E PA at 6 GHz, 4 V were designed and compared. Oneof them was designed using the classical method, while the secondwas designed using the extended method. Both amplifiers werefabricated on a Duroid substrate and the transistor used was aGaAs FET FLK057WG. The amplifier, designed with the extendedmethod, exhibits an improvement on the power added efficiencyof 18.6% in comparison with the amplifier designed using theclassical theory.

Index Terms—Class E power amplifier (PA), high efficiency PA.

I. INTRODUCTION

SWITCHED mode amplifiers are in theory very high effi-ciency amplifiers, and one of the most popular switched

mode amplifiers is the class E [1] developed by N. O. Sokaland A. D. Sokal in 1975. Analytical expressions to determinethe output load network have been reported [1]–[3]. However,in all these works the transistor is assumed to be an ideal switchand, therefore, experimental adjustments are required to attainthe best performance. At very low frequencies, this task be-comes very easy with the aid of an oscilloscope. However, atmicrowave frequencies this task is not as evident as in the lowfrequency case.

In this sense it is desirable that in the design method theanalytical expression for determining the output load networkprovides a value close to the optimum. So, in this work, a newexpression for determining the load network of the class Epower amplifier (PA) is presented. This new expression allowsfor the parasitic elements of the field effect transistor (FET)and the time that a non-square input signal takes to saturate thetransistor. Two amplifiers at 6 GHz were fabricated using a Fu-jitsu GaAs FET FLK057WG; one with the classical approachproposed in [4] while the other was designed with the extended

Manuscript received December 6, 2006; revised March 12, 2007. This workwas supported by CICESE and CONACYT under Project 39835-Y, México.

J. R. Loo-Yau is with the Centro de Investigación y Estudios Avanzados delI.P.N unidad, Guadalajara, México (e-mail: [email protected]).

H. Ascencio-Ramírez and J. A. Reynoso-Hernandez are with the Departa-mento de Electrónica y Telecomunicaciones de la División de Física Aplicadadel Centro de Investigación Científica y de Educación de Ensenada (CICESE),Ensenada, México (e-mail: [email protected]).

Color versions of one or more of the figures in this letter are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LMWC.2007.899322

Fig. 1. FET small signal equivalent circuit.

method proposed in the present work. The amplifier designedwith the extended method, without any post fabrication circuittuning process, presents an improvement on the power gainand power added efficiency (PAE) of 4.75 dB and 18.57%,respectively.

II. OUTPUT LOAD NETWORK

The key to designing a high efficiency class E PA is theoutput load network. The output load network establishes thezero voltage switching (ZVS) condition in the transistor. Thismeans that the voltage and the current in the transistor neveroverlap. In [4], the output load network is calculated using

(1)

where is the frequency of operation and is the output ca-pacitance of the transistor. Equation (1) is derived assuming thatthe transistor is an ideal switch where the principal parameter is

. However, there are two problems that were not addressedin previous works [4], [5]. The first one is about the extractionof and the second is related to the effect of parasitic ele-ments on the performance of the class E PA at high frequency,which modify the performance of the transistor, and therefore,the assumption of an ideal switch to model the transistor is notentirely valid. Therefore, the following criteria are proposed inorder to clarify the design method.

A. FET Output Capacitance

Most of the literature [4], [5] defines the drain source capac-itance as the output capacitance and ignores the parasitic

(see Fig. 1). This definition seems to us incorrect becausethe output capacitance of the FET is strongly affected by the in-trinsic and parasitic capacitances. Assuming that the transistorequivalent circuit consists of intrinsic and parasitic elements, theoutput capacitance of the FET results from the contribution ofthe intrinsic output capacitances, and , and the parasitic

1531-1309/$25.00 © 2007 IEEE

Page 2: An Extension of the Classical Method to Design High Efficiency Microwave Class E PAs

LOO-YAU et al.: CLASSICAL METHOD TO DESIGN HIGH EFFICIENCY MICROWAVE CLASS E PAS 541

Fig. 2. Simplified equivalent circuit of a transmission line class E PA includingthe parasitic elements of the FET.

output capacitance, . In summary the FET output capaci-tance can be calculated from

(2)

It is worth commenting that includes the parasitic capac-itance of the packaging, which is very difficult to extract fromcommercial FETs.

B. New Approach to Determine the Impedance of the OutputLoad Network of A Class E PA

At high frequency, the parasitic elements of the FET play animportant role in the performance of the transistor. Therefore,these elements should be considered in the determination of theimpedance of the output load network of the class E PA. Fig. 2shows the proposed equivalent circuit for determining the outputimpedance of the FET.

The parasitic inductance , associated with the drain of theFET is part of the output load network.

According to Fig. 2, the drain voltage of the FET during theoff-state is given by

(3)

while in the on-state, the drain voltage of the FET is written as

(4)

where is the frequency of operation in rad/sec, is thedc-to-ac voltage transfer ratio [2], is the phase of the outputcurrent, , , and are the parasitic elements of the FET,and is determined as in (2).

On the other hand, the switching action of the transistor is notinstantaneous and, consequently, one expects that the voltage inthe drain of the FET does not reach the ZVS condition. Thefollowing example demonstrates the effect on the waveformvoltage of the drain when the parasitic elements of the FET, aswell as the time that a sinusoidal signal takes to saturate the tran-sistor, are considered. Let us suppose that with a typical GaAsFET with pinch-off voltage of 1 V, a class E PA is designed at6 GHz with the output load network calculated with (1).

Fig. 3. Input voltage and drain voltage (classical approach).

Now, using the custom nonlinear model reported in [6] formodeling the GaAs FET and, with the aid of harmonic bal-ance, the amplifier is modeled and simulated. Fig. 3 shows thewaveform drain voltage of the FET when a sinusoidal voltageis applied to the gate of the transistor in order to saturate it. It isobvious that the ZVS condition is not achieved due to the para-sitic elements of the FET and because it takes time for the inputsignal to saturate the transistor. Therefore the transistor worksas a current source and a peak voltage is formed during the onstate.

This implies that the boundary conditions should be modifiedas follows:

(5)

and (6)

where is the period of the input signal and is defined asthe time that the input signal takes to saturate the transistor.

Now, using (5) and (6), and are determined, and the outputimpedance of the load network is derived and expressed as

(7)

where

(8)

(9)

Setting 41.66 ps ( 4), the impedance of the output loadnetwork is determined from (7)–(9), and the waveform of thedrain voltage in the FET is corrected. This fact will be verifiedin the next section with a class E PA designed at 0.75 GHz.

III. RESULTS

To validate the analytical expression, a 0.75 GHz class E PAwas designed using a NEC651R479A at 2.7 V and

1.0 V. The impedance of the output load network atthe fundamental frequency was determined from (7)–(9), whilehigh impedance is achieved with an open stub for the secondharmonic [5]. Fig. 4 shows the simulation of the voltage andcurrent waveform for this amplifier as well as the measured andsimulated output powers, gain and PAE. The input power wasexperimentally adjusted in the simulator so that the input signalreached 0 V. In addition, in the class E PA simulation, all in-trinsic capacitances of the FET were assumed linear. It is worthcommenting that these capacitances are nonlinear, but the dif-ference between the measurements of the PAE, gain and

Page 3: An Extension of the Classical Method to Design High Efficiency Microwave Class E PAs

542 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 17, NO. 7, JULY 2007

Fig. 4. Simulation results of the class E PA at 0.75 GHz.

Fig. 5. Layout of the 6-GHz class E PA.

TABLE IEXPERIMENTAL RESULTS OF THE 6 GHZ CLASS E PA

with the simulation of the class E PA assuming linear capac-itances are not significant. However, future work will addressthe nonlinear capacitance case.

Now, with the same procedure we scale the design to a 6 GHzclass E PA using a MESFET FLK057WG. Unfortunately, as inthe case of the 5.1-GHz class E PA (PAE 60%) reported in [5],we could not obtain the model of the FLK057WG because the

- characteristics of the FET present a non-hyperbolic tangentbehavior. Therefore, no simulations are presented. However, theextrinsic and intrinsic elements were determined by means ofthe methods proposed in [7] and [8], respectively.

Fig. 5 shows the layout of the 6–GHz class E PA. The outputload network was designed to present at the fundamentalfrequency and high impedance at the second and third harmonic.On the other hand, the input matching network was designed toachieve maximum power transfer ( ) and was experimentallyadjusted in order to obtain the best performance. The input andoutput matching networks were designed on a Duroid substratewith 2.2. Bias tees (model 5580) from Picosecond PulseLabs were used to test the amplifiers.

Furthermore, another 6-GHz class E PA was designed withthe classical approach, (1), and using the same topology as inthe first 6-GHz amplifier. Both amplifiers were tested at the biaspoint 2.5 V and 4.0 V, with an input powerof 15 dBm. Then a comparison of the performances of the twoamplifiers was carried out. Table I summarizes the experimentalresults for both amplifiers.

It is seen from Table I and Fig. 6 that a better performanceis achieved when the output load network is calculated with thenew expression, that is, when the parasitic elements and the timetaken for the input signal to saturate the transistor are consid-ered. It is important to mention that both amplifiers were mea-sured without any post fabrication circuit tuning.

Fig. 6. Measurements of the two amplifiers: (a) P and gain and (b) PAE.

IV. CONCLUSION

A new expression for determining the output load network ofthe FET for high efficiency class E PAs is presented in this work.The amplifier designed with the output load network determinedwith the new expression shows an improvement on the outputpower, gain, and PAE, when compared with a 6-GHz class EPA designed with the classical design method. The new analyt-ical expressions for determining the output impedance of a FETproposed in this work take into account the parasitic elements ofthe FET as well as the time taken for the input signal to saturatethe FET.

REFERENCES

[1] N. O. Sokal and A. D. Sokal, “Class E A new class of high efficiencytuned single ended switching power amplifiers,” IEEE J. Solid StateCircuits, vol. SC-10, no. 6, pp. 168–176, Jun. 1975.

[2] F. H. Raab, “Idealized operation of the class E tuned power amplifier,”IEEE Trans. Circuits Syst., vol. CAS-24, no. 12, pp. 725–735, Dec.1977.

[3] M. Kazimierczuk, “Effects of the collector current fall time on the classE tuned power amplifier,” IEEE J. Solid State Circuits, vol. SC-18, no.2, pp. 181–193, Apr. 1983.

[4] T. B. Mader and Z. B. Popovic, “The transmission line high efficiencyclass E amplifier,” IEEE Microw. Guided Wave Lett., vol. 5, no. 9, pp.290–292, Sep. 1995.

[5] T. B. Mader, E. W. Bryerton, M. Markovic, M. Forman, and Z.Popovic, “Swithced-Mode high efficiency microwave power ampli-fiers in a free-space power combiner array,” IEEE Trans. Microw.Theory Tech., vol. 46, no. 10, pp. 1391–1398, Oct. 1998.

[6] I. Angelov, H. Zirath, and N. Rorsman, “A new empirical model forHEMT and MESFET devices,” IEEE Trans. Microw. Theory Tech., vol.40, no. 12, pp. 2258–2266, Dec. 1992.

[7] J. A. Reynoso-Hernández, F. Rangel-Patiño, and J. Perdomo, “Full RFcharacterization for extraction the small signal equivalent circuit in mi-crowave FET’s,” IEEE Trans. Microw. Theory Tech., vol. 44, no. 12, pp.2265–2233, Dec. 1996.

[8] M. Berroth and M. Bosch, “Broadband determination of the FET smallsignal equivalent circuit,” IEEE Trans. Microw. Theory Tech., vol. 38,no. 7, pp. 891–895, Jul. 1990.