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Annual Report 2007 Solid-State Electronics Department Prof.Dr.rer.nat. F.J.Tegude Universität Duisburg-Essen Fakultät für Ingenieurwissenschaften Institut für Technologien der Informationstechnik Halbleitertechnik/Halbleitertechnologie Lotharstrasse 55 / ZHO D-47057 Duisburg Germany Tel.: ++49 (0)203 379 3392 (Secr.) Fax: ++49 (0)203 379 3400 www: http://www.hlt.uni-duisburg-essen.de Editors: Dr.-Ing. Werner Prost Dr.-Ing. Wolfgang Brockerhoff Halbleitertechnik/ Halbleitertechnologie

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Page 1: Annual Report 2007 Solid-State Electronics Department · Annual Report 2007 Solid-State Electronics Department ... Alice Eckhardt since 08/07 ... Annual Report 2007 - Solid-State

Annual Report 2007

Solid-State Electronics Department Prof.Dr.rer.nat. F.J.Tegude

Universität Duisburg-Essen Fakultät für Ingenieurwissenschaften

Institut für Technologien der Informationstechnik

Halbleitertechnik/Halbleitertechnologie

Lotharstrasse 55 / ZHO D-47057 Duisburg

Germany

Tel.: ++49 (0)203 379 3392 (Secr.) Fax: ++49 (0)203 379 3400 www: http://www.hlt.uni-duisburg-essen.de

Editors: Dr.-Ing. Werner Prost Dr.-Ing. Wolfgang Brockerhoff

Halbleitertechnik/Halbleitertechnologie

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Annual Report 2007 - Solid-State Electronics Department

Table of Contents 1 Preface ................................................................................................................................. 1

2 Members of the Department.................................................................................................... 3

3 Teaching Activities ................................................................................................................... 5

3.1 Lectures and Laboratory Exercises ................................................................................... 5

3.2 Student Reports ................................................................................................................ 8

3.3 Diploma Thesis ................................................................................................................. 8

3.4 Doctor Thesis .................................................................................................................... 9

3.5 Seminar on Semiconductor Electronics .......................................................................... 10

4 Research Activities ................................................................................................................. 13

4.1 Epitaxial Growth and Materials .................................................................................. 13

4.1.1 Doping of GaAs Nanowires C. Gutsche, I. Regolin ...................................................................................... 14

4.1.2 Fabrication of Artificially Shaped Nanowires by Combined VLS- and Conventional Layer Growth I. Regolin , C. Gutsche .................................................................................... 18

4.1.3 Growth of III/V Nanowires on a Silicon Substrate A. Lysov, C. Gutsche ........................................................................................ 21

4.2 Device and Circuit Processing ..................................................................................... 27

4.2.1 Reactive-Ion Etching for Accurate Vertical Electronic Devices on InP A. Krowas, A. Poloczek.................................................................................... 28

4.2.2 Development of a Modular Concept and Realization of Balanced PIN Photoreceiver for QPSK Transmission Systems Suitable for 10GHz Channel A. Poloczek, I. Nannen..................................................................................... 31

4.2.3 Development of a Transimpedance Amplifier with Optical Differential Input I. Nannen.......................................................................................................... 34

4.3 Device and Circuit Simulation, Measurement and Modelling.................................. 37

4.3.1 Development of a LabView Program for Semiconductor Hall Measurements R. Shabanah, I. Nannen, U. Doerk .................................................................. 38

4.3.2 Concept for an Ultra-Wideband Signal Generator with RTD-HBT Technology J. Driesen ......................................................................................................... 41

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Annual Report 2007 - Solid-State Electronics Department

4.3.3 Design and Simulation of an Electrical Input Circuit for an UWB-Pulse-Generator Based on Resonant Tunneling Diodes and Heterostructure Field-Effect Transistors Ö. Kharaman, A.Matiss ................................................................................... 44

4.3.4 2D Physical Simulation of conventional InP Based Heterostructure Field-Effect Transistors and Nanowire Field-Effect Transistors S. Makhlouka, W. Brockerhoff ......................................................................... 47

4.3.5 Characterization of a 1:2 Optoelectronic Demultiplexer based on Monostable-Bistable Logic Elements A. Matiss and A. Stoehr ................................................................................... 52

4.3.6 Development of RTD/HBT Oscillator for Ku- and Ka-Band Applications B. Münstermann, A. Matiss.............................................................................. 55

4.3.7 Modification of Hardware for the Communication between Rotary Encoder and PC-Interface B. Münstermann, I. Nannen ............................................................................ 59

4.4 Nanoelectronics ............................................................................................................ 63

4.4.1 Gate Length Scaling of InAs Nanowire Field-Effect-Transistors K. Blekker......................................................................................................... 64

4.3.2 S-Parameter Measurements of Nanowire Field Effect Transistors A. Matiss, T. Do ............................................................................................... 67

4.4.3 Low Capacitive Pad- and Gate-Configuration for Ultra High Frequency Single Nanowire Transistors K.Blekker.......................................................................................................... 70

4.5 Conference Contributions .............................................................................................. 73

4.6 Publications ................................................................................................. 75

4.7 Research Projects .......................................................................................................... 78

4.8 Other Activities ............................................................................................................. 80

5 Guide to the Solid-State Electronics Department ............................................................. 82

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Annual Report 2007 - Solid-State Electronics Department 1

1 Preface

This report presents the teaching and research activities of the Solid State Electronics Department (Fachgebiet Halbleitertechnik/Halbleitertechnolgie) during the year 2007.

Teaching activities have been reorganized to a strongly modular system, because now we have to serve four different curricula: the “old” diploma in Electrical Engineering, its substitute “Electrical and Electronic Engineering”, the “International Studies in Engineering (ISE)” and “Nano-Engineering”, all B.Sc./M.Sc. curricula. Still this new structure originated additional work load for all members of the department, especially for the experimental exercises and tutorials.

Our research work covers the areas of 1) Epitaxial Growth and Materials, 2) Device and Circuit Processing, 3) Device and Circuit Simulation, Measurement and Modelling, and since 2002, 4) Nanoelectronics, which is strongly correlated to the respective epitaxial work. This Nano-Technology field is growing strongly also in my department, but for real applications processing related as well as fundamental problems like material doping have to be solved; we work on both. Having demonstrated the InAs-nanowire-MISFET, still holding the transconductance world record, last year, we are now working on rf-optimization and tackling the rf-measurement difficulties due to their low current, high device impedance. For bipolar nanowire devices, an epitaxially grown pn-junction is still pending as one of the most important tasks.

Considerable improvements have been achieved also in the field of resonant tunnelling devices (RTD), combined with HFET and HBT stages. Both, oscillator and optoelectronic circuits using RTDs are developed and characterized, supported by simulation and modelling. Especially for digital and large signal RTD applications the RTD model has been improved significantly.

Let me finally thank all friends and partners for their support and fruitful cooperation, and all members and students of the Solid State Electronics Department for their excellent efforts and contributions, which is indispensable for future successful work.

Duisburg, April 2007

Prof. Dr. rer. nat. F.-J. Tegude

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2 Members and Guests of the Department

379- office email

head of the department

Prof. Dr.rer.nat. Franz-Josef Tegude - 3391 LT 207 [email protected]

secretary

Dagmar Birke - 3392 LT 206 [email protected]

scientific staff

Dipl.-Ing. Kai Blekker since 05/07 - 3879 LT 106 [email protected]

Dr.-Ing. Wolfgang Brockerhoff (AOR) - 2989 LT 205 [email protected]

Dipl.-Phys. Quoc Thai Do until 10/07 - 3393 LT 106 [email protected]

Dipl.-Ing. Christoph Gutsche since 08/07 - 3394 LT 203 [email protected]

Dipl.-Phys. Andrey Lysov since 01/07 - 3880 LT 203 [email protected]

Dipl.-Ing. Andreas Matiss - 4605 LT 203 [email protected]

Dipl.-Ing. Ingo Nannen - 3881 LT 204 [email protected]

Dipl.-Ing. Artur Poloczek - 3878 LT 104 [email protected]

Dr.-Ing. Werner Prost - 4607 LT 205 [email protected]

Dipl.-Ing. Ingo Regolin - 3877 LT 104 [email protected]

technical staff

Udo Doerk - 3395 LT 202 [email protected]

Dipl.-Ing. Ralf Geitmann - 4604 LT 202 [email protected]

Dipl.-Ing. Wolfgang Molls - 4603 LT 201 [email protected]

Andrea Osinski - 4600 LT 104 [email protected]

Ing. (grad.) Reimund Tilders - 3396 LT 201 [email protected]

apprentices

Sarah Dohle until 07/07 - 4095 LT 106 [email protected]

Florian Dippe until 07/07 - 4618 LT 106 [email protected]

Alice Eckhardt since 08/07 - 4601 LT 104 [email protected]

Svenja Köppen since 08/07 - 4095 LT 104 [email protected]

Maximilian Keiser since 08/07 - 4618 LT 105 [email protected]

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students

Betting, Björn 06/07-12/07 Kürten, Benedikt since 03/07

Blekker, Kai since 03/07 Lommel, Thomas since 04/07

Chen, Yun Makhlouka, Slim since 09/07

Faber, Dennis since 03/07 Münstermann, Benjamin

Keller, Gregor since 03/07 Nannen, Jörg since 06/07

Krowas, André until 06/07 Xue, Yan since 09/07

Guests of the department:

• Prof. Dr. Knut Deppert, Solid State Physics, Lund University, Sweden

• Dr. Michael Feiginov, Institut für Hochfrequenztechnik, TU Darmstadt, Germany

• Prof. Dr. Carsten Ronning, Institute for Solid State Physics, University of Jena, Germany

• Prof. Kanju Yoh, Hokkaido University, Research Center for Integrated Quantum Electronics, Sapporo Japan

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Annual Report 2007 - Solid-State Electronics Department 5

3 Teaching Activities 3.1 Lectures and Laboratory Exercises

Schedule International Studies in Engineering (ISE)

Electrical and Electronic Eng.

Nanoengi-neering. Lectures and exercises diploma

course B.Sc. M.Sc B.Sc. M.Sc B.Sc.

Solid-State Electronics 1 Festkörperelektronik 1 3rd sem.

Solid-State Electronics 2 Festkörperelektronik 2 4th sem.

Introduction to Solid-State ElectronicsEinführung in die Festkörperelektronik 4th sem. 2nd sem. 4th sem.

Technical Electronics 1 Technische Elektronik 1 / Elektronische Bauelemente

5th sem.

Basic Electronic Devices Grundlagen Elektronischer Bauelemente 5th sem. 3rd sem. 5th sem.

Technical Electronics 2 Technische Elektronik 2 / Elektronische Schaltungen

6th sem.

Basic Electronic Circuits Grundlagen Elektronischer Schaltungen 2nd sem.

Basic FET- and Bipolar Transistor Circuits Grundlagen Elektronischer FET und Bipolartransistorschaltungen

2nd sem.

Semiconductor Microelectronics Technology 1/ III-V Technologies and Components 1/ Halbleitertechnologie 1

optional

Laboratory exercises

Communication Electronics Praktikum Technische Elektronik 7th sem.

Introduction to Operational AmplifiersPraktikum Operationsverstärker optional

Semiconductor Technology Praktikum Halbleitertechnologie/ Halbleitertechnologie

optional

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Schedule International Studies in Engineering (ISE)

Electrical and Electronic Eng.

Nanoengi-neering.

Laboratory exercises diploma course

B.Sc. M.Sc B.Sc. M.Sc B.Sc.

Basic Electronic Devices Praktikum Grundlagen Elektronischer Bauelemente

5th sem.

Basic Electronic Circuits Praktikum Grundlagen Elektronischer Schaltungen

2nd sem.

Electronics and RF Praktikum Grundlagen Elektronischer und Hochfrequenzschaltungen

5th sem.

Basic FET- and Bipolar Transistor Circuits Grundschaltungen der FET- und Bipolarelektronik

2nd sem.

Seminars and Colloquia

Seminar on Semiconductor ElectronicsProbleme der modernen Halbleiterphysik

Seminar on Epitaxial Problems

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Annual Report 2007 - Solid-State Electronics Department 7

Lectures and Exercises:

Introduction to Solid-State Electronics / Solid-State Electronics 1,2 (Einführung in die Festkörperelektronik) / (Festkörperelektronik 1,2)

These courses start with an introduction to the basics of Quantum physics. Based on Schroedinger's equation and Heisenberg's uncertainty relations a comprehensive understanding of semiconductor band structure is achieved. The first part (Introduction to Solid-State Electronics) also includes carrier statistics and ends up with a discussion of current continuity and Poisson's equation. In the second part of this lecture the basic building blocks of electronic devices, i.e. semiconductor-metal contact, MIS system, pn junction and heterostructures, are treated for subsequent courses on field effect and bipolar electronics.

Basic Electronic Devices (Technische Elektronik 1)

MOS-Capacitors, charge coupled devices and Field-Effect Transistors both, on Silicon and III/V material, are treated during the first part of the course. The fundamentals as well as the DC characteristics of MOSFET, MESFET, JFET, and Heterostructure FET (HFET) are derived and analysed in detail.

Additionally, bipolar devices - pn-diodes, npn- and pnp-transistors as well as tunnel- and zener-diodes - are considered. Based on the dc characterisitics simple small-signal equivalent circuits are derived.

Basic Electronic Circuits / Basic FET- and Bipolar Transistor Circuits (Technische Elektronik 2 / Grundschaltungen der FET- und Bipolarelektronik)

This course covers the basic methods to calculate complex electronic circuits using the devices treated within the "Basic Electronic Devices". Various device models with respect to circuit design and circuit simulation using commercial circuit simulation tools are discussed. Numerous analog (e.g. operational amplifiers) and digital applications are included.

Semiconductor Microelectronics Technology 1,2 (Halbleitertechnologie 1,2)

The semiconductor microelectronics technology lectures are devoted to III/V-semiconductor heterostructures for high speed electronic devices. The process steps from crystal growth to circuit fabrication are discussed. The first semester is focused on heterostructure material issues. Modern growth techniques like molecular beam epitaxy (MBE) and metal-organic vapour-phase epitaxy (MOVPE) are discussed in terms atomic layer control of thickness, composition, and doping. High Resolution X-ray diffraction, photoluminescence, and ellipsometry are explained for non-destructive material assessment in the mono-layer scale. The second semester is devoted to microelectronic fabrication techniques for high speed (f ≥100 GHz) devices and circuits. The lateral and vertical processing of epitaxial films, insulating layers, and metallizations are presented for high performance monolithic high speed analog and digital integrated circuits.

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Laboratory exercises

Communication Electronics, Basic Electronic Devices, Basic Electronic Circuits (Praktikum Technische Elektronik)

Within the laboratory exercises students apply their theoretical knowledge based on the lectures "Basic Electronic Devices" and "Basic Electronic Circuits". The capacitance-voltage characteristics of schottky diodes are measured and evaluated. The dc and small signal parameters of bipolar transistors as well as the switching behaviour is experimentally investigated. The course also covers the analysis of the dynamical performance of digital circuits. Additionally, numerical simulations and synthesis of basic electronic circuits are carried out on a UNIX system.

Introduction to Operational Amplifiers (Praktikum Operationsverstärker)

The aim of this course is the understanding of the basic principles and the characteristics of operational amplifiers (OpAmps). The laboratory exercises demonstrate their applicability in electronic circuits enabling the students to an independent design and understanding of complex circuits. Starting with the measurement and interpretation of the most important characteristic parameters of OpAmps, circuits like adders and multipliers, amplifiers and active filters are intensively calculated and investigated. Oscillators and generators are designed and measured.

Seminars and Colloquia

Seminar on Semiconductor Electronics (Probleme der modernen Halbleiterphysik)

Within this seminar actual topics of the semiconductor electronics are discussed. Students, but also members of the department, report about their own work.

Seminar on Epitaxial Problems

Problems of the epitaxial growth of semiconductor structures are analysed, results are interpreted and future trends are discussed.

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Annual Report 2007- Solid-State Electronics Department 9

3.2 Student Reports (Studienarbeiten)

1. Anpassung einer Schnittstellen-Hardware (Drehgeber auf USB) zur Optimierung der Kommunikation zwischen Drehgeber und Schnittstellen-Hardware und Aufbau eines Testmodells

BENJAMIN MÜNSTERMANN

submitted: 02.02.2007

2. Entwurf und Simulation einer elektrischen Eingangsschaltung für einen UWB-Pulsgenerator auf Basis von Heterostruktur-Feldeffekttransistoren

ÖZGÜR KAHRAMAN

submitted: 04.10.2007

3.3 Diploma Thesis (Diplomarbeiten)

1. Entwicklung eines LabVIEW Programms zur Charakterisierung von Halbleiterschichten mittels Hallmessungen

RAED SHABANAH

submitted: 30.03.2007

2. Reaktives Ionenätzen für strukturtreue vertikale Bauelemente auf InP ANDRÉ KROWAS

submitted: 08.05.2007

3. Herstellung von Nanodraht pn-Dioden CHRISTOPH GUTSCHE

submitted: 10.07.2007

4. 2dimensionale physikalische Simulation von InP basierten Heterostruktur-Feldeffekttransistoren (HFET)

SLIM MAKHLOUKA

submitted: 08.11.2007

5. Entwicklung eines RTD/HBT Oszillators für Ku- und Ka-Band Anwendungen BENJAMIN MÜNSTERMANN

submitted: 27.12.2007

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10 Annual Report 2007- Solid-State Electronics Department

3.4 Doctor Thesis (Dissertation)

1. MOCVD-Präparation von III-V-Materialien auf der Gitterkonstanten von InP für Solarzellen

HERMANN-JOSEF SCHIMPER,

examination: 06.07.2007

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Annual Report 2007 - Solid-State Electronics Department 11

3.5 Seminar on Semiconductor Electronics

11.01.2007 DENNIS FABER, REPORT ON THE STUDENT THESIS: 'Ohmsche Kontakte an InAs und GaAs Nanodrähten'

KAI BLEKKER, REPORT ON THE DIPLOMA THESIS: 'Kontaktierung und elektrische Charakterisierung von InAs Nanodrähten'

25.01.2007 THAI DO, REPORT ON 'Modellierung von Nanodraht-FET's'

01.02.2007 HERMANN JOSEF SCHIMPER, HMI, BERLIN, REPORT ON 'MOCVD Präparation von III/V Materialien auf der Gitterkonstanten von InP für

Solarzellen'

08.02.2007 BENJAMIN MÜNSTERMANN, REPORT ON THE STUDENT THESIS: 'Anpassung einer Schnittstellen-Hardware (Drehgeber auf USB) zur Optimierung

der Kommunikation

zwischen Drehgeber und Schnittstellen-Hardware und Aufbau eines Testmodells'

05.04.2007 INGO NANNEN, REPORT ON THE PROJECT "Key components for synchronous optical quadrature phase shift keying

transmission (SynQPSK)"

12.04.2007 RAED SHABANAH, REPORT ON THE DIPLOMA THESIS: 'Entwicklung eines LAbVIEW Programms zur Charakterisierung von

Halbleiterschichten mittels

Hallmessungen'

10.05.2007 WERNER PROST, REPORT ON THE CONFERENCE 'Material Research Society Spring Meeting' (MRS), San Francisco, CA, USA,

09.04.2007 - 13.04.2007

24.05.2007 ANDRÉ KROWAS, REPORT ON THE DIPLOMA THESIS: 'Reaktives Ionenätzen für strukturtreue vertikale Bauelemente auf InP'

14.06.2007 FRANZ-JOSEF TEGUDE, REPORT ON THE CONFERENCE 'IEEE Int. Conf. on InP and Related Materials (IPRM)', Matsue, Japan, 14.05.2007 -

18.05.2007

ANDREAS MATISS, BENJAMIN MÜNSTERMANN, REPORT ON THE PROJECT: "RTD/HBT-Kombinationsbauelemente für Oszillatoranwendungen für die

Satellitenkommunikation", Ziele und Konzepte

21.06.2007 STEFAN HÄCKEL, "Patente im Hochschulbereich"

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12 Annual Report 2007 - Solid-State Electronics Department

12.07.2007 CHRISTOPH GUTSCHE, REPORT ON THE DIPLOMA THESIS: 'Herstellung von Nanodraht pn-Dioden'

25.10.2007 ÖZGÜR KAHRAMAN, REPORT ON THE STUDENT THESIS: 'Entwurf und Simulation einer elektrischen Eingangsschaltung für einen UWB-

Pulsgenerator auf Basis von Heterostruktur-FET'

SLIM MAKHLOUKA, REPORT ON THE DIPLOMA THESIS: '2dimensionale physikalische Simulation von InP basierten Heterostruktur-

Feldeffekttransistoren (HFET)'

08.11.2007 A.MATISS, REPORT ON THE CONFERENCE 2007 IEEE Int. Conf. on Ultra-WideBand (ICUWB), Singapore, Singapore,

24.09.2007 - 26.09.2007

15.11.2007 F.-J.TEGUDE, REPORT ON THE CONFERENCE The second Int. Conf. on One-Dimensional Nanomaterials 2007 (ICON), Malmö,

Sweden, 26.09.2007 - 29.09.2007

W.PROST, REPORT ON THE CONFERENCE Topical Workshop on Heterostructure Microelectronics for Inf. System Applications

(TWHM), Chiba, Japan, 21.08.2007 - 24.08.2007

13.12.2007 A.POLOCZEK, REPORT ON THE CONFERENCE 20th Annual Meeting of the IEEE Lasers and Electro-Optics Society (LEOS), Lake

Buena Fista, Fl, USA, 21.10.2007 - 25.10.2007

I.NANNEN, REPORT ON THE CONFERENCE Europ. Conf. on Optical Communication 2007 (ECOC), Berlin, Germany, 16.09.2007

- 20.09.2007

A.MATISS, REPORT ON THE CONFERENCE Europ. Microwave Week / Workshops and Short Courses (EuMW), München,

Germany, 08.10.2007 - 12.10.2007

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Annual Report 2007 - Solid-State Electronics Department 13

4 Research Activities

4.1 Materials, Growth and Characterization

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4.1.1 Doping of GaAs Nanowires

Student: C. Gutsche Scientist: I. Regolin in collaboration with Prof. Carsten Ronning, University of Göttingen

Introduction III/V semiconductor nanowires (NWs) grown by the vapour-liquid-solid (VLS) mechanism are attractive building blocks for nanoscaled devices [1]. The electrical conductivity of the NWs may be provided by charged carriers induced by an electric field (accumulation, inversion) or by carriers stemming from dopant atoms. It is important to note that a high surface potential φs of the nanoscaled wires may cause a full depletion of the wire. In case of GaAs (φs ≈ 0.5 V), a remaining conductivity in the center of a wire of 100 nm diameter requires a high doping level >1017 cm-3. Doping is routinely done during epitaxial growth by offering a specific dopant precursor. After growth, doping may be provided by thermal diffusion or kinetic ion implantation. However, so far a controllable doping method is lacking especially for III/V semiconductor nanowires. In this study we report on both in-situ and ex-situ doping techniques for GaAs nanowires grown by MOVPE in the VLS mode. Ion implantation is used as post growth doping technique.

Experimental GaAs NWs were grown on top of <111> GaAs substrates using gold nanoparticles as seed elements during metal-organic vapour phase epitaxy (MOVPE). Tertiarbutylarsine (TBAs) and trimethylgallium (TMGa) were used as precursors at a growth temperature of 450°C. For electrical characterisation, the nanowires were cut-off the growth substrates, transferred onto an insulating carrier substrate, and patterned using e-beam lithography. Pt/Ti/Pt/Au contacts were evaporated and annealed at 360°C for 30 sec. The morphology, structure and electrical properties of implanted nanowires were investigated by scanning electron microscopy (SEM) and I/V-measurements.

In-situ p-type doping during growth using of 100 nm diameter Au seed particles was performed using carbon tetrabromide (CBr4) for sample M3664a, and diethyl-zinc (DEZn) for samples M3681. For n-type doping experiments ditertiarbutylsilane (DitBuSi) was used.

For ex-situ doping ion implantation is adopted. The wires were implanted with Zn acceptors at the II. Institute of Physics at the University of Göttingen. Different ion energies were used in order to create a box-like implantation profile with a peak concentration of 3.1019 cm-3 matching the diameter of the GaAs nanowires. After ion implantation, the samples were sent back to Duisburg and annealed in the MOVPE at 800°C under TBAs stabilisation.

In-situ doping during VLS growth Various GaAs nanowires were grown by MOVPE under VLS conditions. The SEM micrographs (Fig. 1) of the selected batch of samples are given in Fig.1. The NWs exhibit a length of about 15 µm, and a smooth surface. The VLS growth is accompanied by an additional lateral component

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grown in conventional layer growth. This radial overgrowth depends on different growth parameters and causes the tapered profile. The measured I/V-characteristics of both samples (Fig.1) exhibit a non-ohmic behaviour, with room-temperature resistance of about 25 MOhm. Assuming a contact distance of 1.5 µm the doping concentration could be estimated to exceed 1019cm-3 indicating a successful in-situ doping process despite the non-ohmic behaviour at zero volt bias. The high conductivity may be provided by the bulk nanowire or by the shell which is grown in the normal layer growth mode. However, we observed no influences of the used precursor flow on the measured concentration. A further experiment using ditertiarbutylsilane (DitBuSi) for n-type doping during growth showed no increased conductivity of NWs. We conclude that at the selected growth temperature of 450°C DitBuSi has no visible doping effect. For an effective decomposition of DitBuSi higher temperatures may be necessary, which would though lead to an intensified radial overgrowth and tapering effect.

-50

-25

0

25

50

-2 -1 0 1 2voltage / V

curre

nt /

µA

a) CBr4

GaAs NWM3681

b) DEZn

-50

-25

0

25

50

curre

nt /

µA

-2 -1 0 1 2voltage / V

GaAs NWM3664

Fig. 1 GaAs nanowire with p-dopant CBr4 (a) and DEZn (b): SEM micrograph (left) and I-V

characteristics (right) with a number of samples fabricated from the same bath of wires [2].

Ion implantation of Zn into GaAs nanowires GaAs nanowires were grown on top of <100> GaAs substrates using gold nanoparticles of 150 nm as seed elements. The nanowires are bevel upstanding due to the <111> orientation of the substrate (cf. Fig. 2). This orientation is well suited for ion implantation of as grown wires.

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16 Annual Report 2007 - Solid-State Electronics Department

Fig. 2 Used process scheme for implantation experiments and SEM micrograph of a prepared sample

The measured I/V-characteristic (Fig. 3) shows a current increase by more than four orders of magnitude for Zn implanted and annealed nanowires. Further experiments with different nanowire diameters (100 and 200 nm) confirmed this result. We estimated the doping concentrations of an “as grown” and Zn implanted nanowire as well. This estimation based on mobility vs. carrier concentration model and takes a surface depletion into account. The result of the Zn implanted nanowire shows a good agreement between the experimental (3,5.1018 cm-3) and calculated (3.1019 cm-3) data, taking into account that only a fraction of acceptors is ionized in heavily doped semiconductors at RT [3]. However, the measured data exhibit a broad variation but remain in the same order of magnitude.

Fig. 3 I/V-characteristics of “as grown” and Zn implanted GaAs nanowires [3].

-80

-40

0

40

80

-2 -1 0 1 2voltage / V

curr

ent /

µA

Zn implantationNA = 3,5.1018 cm-3

-80

-40

0

80

40

curr

ent /

nA

as grownNA = 4.1017 cm-3

GaAs-NWdAu = 150 nmPt/Ti/Pt/Au-contacts

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Annual Report 2007 - Solid-State Electronics Department 17

In addition, the continuation of growth after the doping treatment has been successfully demonstrated (Fig. 4). The surface of the whiskers after ion-implantation and annealing is studied by SEM micrographs. The transition between implanted and additionally grown nanowire area can be identified due to different surface roughness and some small defects at the intersection. The implanted area shows an enhanced surface roughness even after annealing.

Fig. 4 Bevel upstanding GaAs nanowires on GaAs (100) before (a) and after (b) Zn implantation, annealing and continued growth process. (c) high resolution SEM of the transition from implanted to re-grown section.

Summary GaAs nanowires exhibit a high surface potential. Therefore a very high doping level is required in order to avoid a full wire depletion. A high p-type conductivity has been obtained with in-.situ doping using both CBr4 and DEZn precursors. The low VLS growth temperature limits the usability of dopant precursors and is a possible reason for lacking success with n-type doping using DiTBuSi. Ion implantation was adopted to GaAs nanowires. After Zn implantation and annealing under TBAs atmosphere in the MOVPE, a high conductivity with full ohmic I-V characteristics was obtained. In addition, the ability of continued growth after the ion implantation process is shown. The main focus of our upcoming work will be on the realisation of n-type doping in GaAs nanowires via ion implantation of S. These way longitudinal nanowire pn junctions should be realized, leading to a high efficient nanoscale LED device.

References: [1] X. Duan, Y. Huang, Y. Cui, J. Wang and C.M. Lieber; "Indium phosphide nanowires as building

blocks for nanoscale electronic and optoelectronic devices", Nature 409, 66-69, 2001. [2] C. Gutsche, "Herstellung von Nanodraht pn-Dioden", Diploma Thesis, University Duisburg-

Essen, July 2007. [3] D. Stichtenoth, K. Wegener, C. Gutsche, I. Regolin, F.J. Tegude, W. Prost, M. Seibt, C. Ronning;

Controlled p-type doping of GaAs nanowires, submitted to Appl. Phys. Lett., 2008.

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a

VLS

p

n

2

VLS

1

substrate

Au

3

b Fig. 1. Epitaxial core-shell nanowire structure (a) design, (b) SEM micrograph

4.1.2 Fabrication of Artificially Shaped Nanowires by Combined VLS- and Conventional Layer Growth

Scientist: I. Regolin, C. Gutsche

Introduction Core-shell types of nanowires have recently found wide interest for photonic and electronic applications. Both, selective area epitaxy and vapor-liquid-solid (VLS) mechanism [1, 2] have been used for the synthesis of the core while the shell is routinely provided by conventional epitaxial layer growth. We report here on the growth of artificially shaped GaAs core-shell nanowires structures realized by multiple switching between the VLS growth mode using Au seed elements and the conventional layer growth. The switching between the different growth modes is basically done by ramping the growth temperature from low temperatures (Tg < 500 °C) for VLS to high temperature (Tg > 550 °C) for conventional layer growth. In this study we put emphasis on the behavior of the Au seed element at high temperatures and the possible application of the conventional layer growth for selective doping of the core-shell structures.

Experimental Setup Monodisperse Au nanoparticles, in the range of 150 nm were deposited on (111)B GaAs substrates by dropping a small amount of colloidal solution onto the surface and evaporating the solvent. Next, the samples were annealed under N2 atmosphere at 300 °C for 300 seconds in order to remove organic residuals. Prior to growth the sample is loaded into a metal-organic vapor-phase epitaxy (MOVPE) and annealed at 600 °C for 10 minutes in a Tertiarybutylarsine (TBAs) atmosphere. TBAs and Trimethylgallium (TMGa) are used as group-III and group-V precursor, respectively. The process for the growth of an artificially shaped core-shell nanowire is depicted in Fig. 1a. The inner core (1) was grown first at low temperatures in the VLS mode. After ramping the growth temperature, the shell is grown via conventional layer growth mode (2). During layer growth controlled doping using i. e. Ditertiarybutylsilane (DitBuSi) for n-type and Carbontetrabromid (CBr4) for p-type doping shall be possible. Due to the low solubility of Au in GaAs, the Au seed element might remain unchanged on the top of the lower core-shell structure. Therefore, we tried to continue the growth after the fabrication of the lower core-shell structure. The thinner upper part, the GaAs nanowire was continued again under VLS

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Annual Report 2007- Solid-State Electronics Department 19

conditions (3).

The structural characterization was done by scanning electron microscopy (SEM). For electrical measurements, the structures were transferred to a carrier substrate. Ohmic contacts were patterned by electron beam lithography. For n-type contacts Au/Ge/Ni and for p-type contact Au/Pt/Ti was evaporated. The ohmic contacts were annealed for 30 s at 360 ° C.

Results Various GaAs core-shell type nanowire structures were grown proving the above described concept. The inner core of the structure shown in Fig. 1b was grown at 420 °C for 20 minutes in the VLS mode, resulting in nanowires with negligible tapering and a length up to several micrometers. Following, the growth temperature was raised up to 600 °C. A growth time of 4 minutes led to the shell of approximately 200 nm. SEM micrographs proved that the Au nanoparticle remains stable at the top of the wire. This provides the basic requirement for the third step under VLS conditions, which was added to produce the top nanowire. This part was grown at 450 °C for 15 minutes. The successful production of the intended nanowire design is depicted in Fig. 1b. By variation of the growth temperature and time, various artificially shaped core-shell type nanowires may be produced.

In contrast to the VLS mode, well known doping schemes are available at the high temperatures of layer growth. Therefore, the designed core-shell structures may also enable a specific doping scheme as indicated in Fig. 1a. For n-type doping of the GaAs shell at 600 °C DitBuSi was supplied during growth. To create a p-type doping, CBr4 was introduced while the upper part was grown at 450 °C in the VLS mode.

For electrical characterization, the structures were transferred to a highly insulating host substrate and multiple ohmic contacts are patterned with electron beam lithography (Fig. 2b, Fig. 3). The top part shows nearly ohmic behavior. The measured resistance of Rp-p = 87 kΩ corresponds to a doping density of NA = 1.1018 cm-3. For this estimation the contact resistance was neglected. We further assumed a surface depletion energy of 0.5 eV and a mobility of 225 cm²/Vs. The growth temperature of 450 °C for the upper p-part of the whisker results into a tapering effect (c.f. Fig. 2b). Etching experiments have shown that the tapered surface exhibits a higher conductivity compared to the core.

The I-V characteristic of the pn-junction shows a strongly non-linear but symmetrical behavior. The origin of the barrier of about 1 eV is unknown. The lower conductivity indicates that the n-part and/or the n-contact is limiting the current through the junction. This estimation is further confirmed with experiments on n-n junctions which exhibit an even much lower conductivity. The differential resistance rn-p at higher bias corresponds to rn-p = 125 kΩ and is attributed to a low doping density ND< = 1.1017 cm-3. The growth temperature of 600 °C may be to low for efficient cracking of the DitBuSi precursor. The shell layer growth takes place into the <110> orientation of the side facets which may alter the Si incorporation in comparison to the growth in (100) orientation. In addition, the tapered growth of the upper part may also result in a p-type skin of the lower part.

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20 Annual Report 2007 - Solid-State Electronics Department

npp n

p-p n-p

a

b

500 nm

Fig. 2 Contact pattern after substrate transfer, electron beam lithography, and metallization

of core-shell nanowire structures: (a) design and (b) SEM micrographs

-20

-10

0

10

20

Au 400 nmPt 25 nmTi 10 nmPt 10 nm30 s @ 360 °C

curr

ent I

n-n /

µA p-p

-2 -1 0 1 2voltage Vn-p / V

a)

-4

-2

0

2

4

-2 -1 0 1 2voltage Vn-p / V

Au 400 nmGe 10 nmNi 10 nmGe 5 nm30 s @ 360 °C

n-pcu

rren

t In-

p / µ

Ab)

Fig. 3 I-V characteristics of junctions on the core-shell nanowire (a) “n-p” and (b) “p-p”

Conclusion The successful combination of VLS mode and conventional layer growth core-shell nanowire structures. The Au seed particle remains stable during high temperature growth processes on the top of the nanowire and may be reused for subsequent VLS growth experiments. This technology enables artificially shaped core-shell nanowire structures. A high p-type conductivity is obtained in a VLS grown GaAs nanowire. Further works will focus on the improvement of the non-linear I-V characteristic of the p-n junction which is attributed to a low doping density in its n-part.

Acknowledgement This work was supported by Center of Excellence SFB 445 “Nanoparticles from the gas-phase”

References [1] J. Noborisaka, J. Motohisa, S. Hara, T. Fukui; “Fabrication and characterization of freestanding

GaAs/AlGaAs core-shell, nanowires and AlGaAs nanotubes by using selective-area, metalorganic vapor phase epitaxy”, Appl. Phys. Lett. 87, 093109, 2005.

[2] N. Sköld, L.S. Karlsson, M.W. Larsson, M.-E. Pistol, W. Seifert, J. Trägårdh, L. Samuelson; ”Growth and optical properties of strained GaAs-GaxIn1-xP core-shell nanowires” Nano Letters, vol. 5, no. 10, pp. 1943-1947, 2005.

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Annual Report 2007 - Solid-State Electronics Department 21

4.1.3 Growth of III/V Nanowires on a Si Substrate

Scientist/Student A. Lysov, C. Gutsche

Introduction The integration of compound semiconductors with the mainstream Silicon (Si) technology is a sought-after goal. Si is the prevalent platform for microelectronics, while III-V compound semiconductors are the basis for light emitting diodes, photo-detectors and other optoelectronic applications. However, epitaxial growth of III-V semiconductors on Si is prevented by several fundamental issues such as lattice mismatch, appearance of structural defects known as antiphase boundaries, and wide disparity of thermal expansion coefficients [1]. Semiconductor nanowires offer a way to combine strongly mismatched materials. The small wire cross-section accounts for a strain relaxation along the growth direction within a few layers.

The monolithic integration with CMOS requires (100) Si substrates. A severe obstacle for the integration of III-V nanowires on (100) Si substrate is, that the nanowires grow in <111> directions with an angle of 35.3° towards the surface (see Fig. 1a). The appearance of the four different <111> directions inhibits the fabrication of locally defined top contact, even if the seed position prior to the growth is known. However, even in the case of (111) Si, there are 4 <111> directions but with an angle of 19° towards the surface where nanowire growht may occur (Fig. 1b).

In this study we investigate the growth of III/V nanowire on differently oriented Si substates. We discuss the integration of III/V nanowires on Si with a defined top contact technology.

a

b

Figure 1: Preferred growth in <111> directions of nanowires on differently oriented Si substrates (a)(100) and (b) (111).

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22 Annual Report 2007 - Solid-State Electronics Department

Experiments and results The growth experiments of GaAs nanowires on (111) Si substrates via MOVPE have shown, that the largest part of the nanowires still don’t grow vertically, but appear inclined (see Fig. 2). The appearance of the inclined nanowires arises from the existence of four equivalent <111> growth directions on (111) Si substrates, one of them being perpendicular to the surface and three other orientations having an 19° angle with the surface and in-plane components at an angle of 120° from each other (cf. Fig. 1b).

a b

Figure 2: Secondary electron microscope image of GaAs nanowires grown on (111) Si substrate. a) Sideview. b) Topview.

Recently, Dr. P. Werner at the MPI Halle presented vertically Si nanowires grown on (111) Si substrates (cf Fig. 3) via a vapour-liquid-solid mechanism in a molecular beam epitaxy (MBE). We have used these Si nanowires as a template for continued VLS growth of GaAs nanowires by MOVPE. Since the templates were exposed to air for some days before the growth in MOVPE, tens of nanometers of SiO2 may have been formed at the interface between Au and Si stump at room temperature, because Au is known to catalyse the oxidation of Si [2]. To remove the oxide the annealing step prior to GaAs nanowires growth on top of the Si-stumps was investigated.

Figure 3: Secondary electron microscope image of a pre-grown template with Si stumps on (111) Si substrate (produced in the workgroup of Dr. P. Werner, MPI Halle).

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Annual Report 2007 - Solid-State Electronics Department 23

A series of annealing experiments were made to find out the optimal conditions with respect to the growth direction of GaAs nanowires.The annealing temperature was varied between 600°C and 950°C and the annealing time between 5 and 30 minutes. For the nanowire growth the standard temperature of 450°C was chosen. Below an annealing temperature of 800°C, no growth of GaAs on Si-stumps was observed. The best yield was observed with the annealing step of 10 min at 900°C. However, all four <111> directions still appeared under these conditions (see Fig. 4). The Si stump was transformed to the thickened base going over into GaAs nanowires. Whether the vertical [111] direction or some other <111> direction appears, depends on the flatness of the interface between Au-seed and the underlying Si-stump at the beginning of the growth process [3,4]. If the Au-particle merges into the Si stump forming an eutectic alloy 111 facets with different orientation than the initial (111) surface plane can appear. When we offer the group III and V materials from the gas phase, these atoms will dissolve in the Au/Si particle. The growth nucleation can now start on one of the side facets, yielding an orientation of the nanowires, which is not perpendicular to the surface (see Fig. 6).

Figure 4: Secondary electron microscope (SEM) images of GaAs nanowires grown on a template with Si stumps on (111) Si substrate. Annealing at 900°C for 10 min was made prior to the growth of GaAs.

Figure 5: Schematics of the interface between the Au globule and Si stump a) for the case of the flat interface, when the surface under the Au droplet remains intact and b) for the case when facets different from (111) appear.

When nanowire growth is initiated the Si will be excreted, forming the thickened interface. Since the growth of the nanowires with an orientation, which is not perpendicular to the surface seems to

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24 Annual Report 2007 - Solid-State Electronics Department

be favoured by merging of Au in Si an annealing at lower temperatures should yield better outcome of perpendicular nanowires. The best results concerning growth in [111] direction were achieved with an annealing step of 10 min and 20 min at the temperatures of 850°C (see Fig. 6). Obviously, the annealing at high temperatures favours the growth of the inclined nanowires. In the future works a transfer technology which avoids oxidation of the Si at the Au interface has to be developed.

Figure 6: SEM images of GaAs nanowires grown on a template with Si stumps on (111) Si substrate. Annealing at 850°C for A)10 min and B) 20 min was made prior to the growth of GaAs nanowires.

To combine the growth on the (111) surfaces with the (100) substrates prevalent for MOS technology, we proposed to etche V grooves constituted of (111) planes in the (100) Si-substrates. This could enable the fabrication of top contacts (see Fig. 7). We elaborated [5] a wet chemical V-groove etching technology using potassium hydroxide (KOH, 30% at 80°C) as etchant and LPCVD Si nitride as etch mask. Hot phosphoric acid (H3PO4 at 120°C) and optical lithography were used to structure the hard mask. Figure 10b shows the realized (111) growth on (100) oriented Si substrates by wet chemical etching. Colloidal Au particles (30 nm and 50 nm) were dispersed on the processed substrates and hence also on the (111) facets. The samples were transferred into a MOVPE system and heated up to 950°C in order to remove the native oxide. Afterwards GaP NWs were grown at 480°C.

Figure 7: Proposed scheme for the fabrication and contacting of a III/V nanowire grown on the (111) edge of a V groove in the (100) Si substrate

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Annual Report 2007 - Solid-State Electronics Department 25

a 3 µm

b Figure 8: SEM micrograph of V-groove in (100) Si substrate: (a) (111) facets and (b) after GaP

nanowires growth on (111) facet [5]

We have produced V groves in (100) Si substrates and demonstrated the possibility to fabricate vertical wires on etched (111) planes in principal. To become high yield of GaAs nanowires growing vertically on (111) planes series of growth experiments on Si stumps were carried out. Growth parameters yielding best resuts concerning growth in [111] direction were found out.

References: [1] S. F. Fang, K. Adomi, S. Lyer, H. Morkoc and H. Zabel,. “Gallium arsenide and other compound

semiconductors on silicon”, J. Appl. Phys., 68, R31 (1990) [2] Hiraki A, Lugujjo E and Mayer J W, “Formation of silicon oxide over gold layers on silicon substrates”,

J. Appl. Phys., 43, 3643 (1972) [3] Mårtensson, T. et al. , “Epitaxial III-V nanowires on silicon. ” Nano Lett. 4, 1987–1990 (2004). [4] U. Krishnamachari, M. Borgstrom, B. J. Ohlsson, N. Panev, L. Samuelson, W. Seifert, M. W. Larsson,

and L. R. Wallenberg, “Defect-free InP nanowires grown in [001] direction on InP (001),” Appl. Phys. Lett., 85, 2077-2079 (2004).

[5] C. Gutsche, “Herstellung von Nanodraht pn-Dioden”, Diploma Thesis, University Duisburg-Essen, July 2007

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4.2 Device and Circuit Processing

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28 Annual Report 2007 - Solid-State Electronics Department

4.2.1 Reactive-Ion Etching for Precise Pattern Definition of InP-Based Vertical Electronic Devices

Student: A. Krowas Scientist: A. Poloczek

Introduction The lack of counter accuracy is often a cause of malfunction in (opto-) electronic devices. Vertical and lateral dimensions of these devices deviate from the data specified by the layout because of processing tolerances. Thereby the functionality of circuits can be endangered. Reactive-ion etching enables etching of structures with high aspect ratio. However dry etching can cause surface damage of the semiconductor. These damages have to be minimized by variation of the process parameters. Within this work the dry etching process for the vertical electronic devices resonant tunnelling diode (RTD) and pin-diode was investigated.

Reative Ion Etching An Oxford Instruments plasma system “PlasmaLab System 100 ICP65” with inductively coupled plasma is used for reactive ion etching using chlorine [1]. The remote plasma is generated by the power source PICP at 13.56 MHz. The kinetic energy of incident ions can be additionally controlled by a second power generator PRF which is applied to the sample electrode. This electrode is heated to a temperature of 170°C in order to support the desorption of especially Indium-containing reaction products. During all process runs the pressure was kept constant at 5 mTorr. Reactive ion etching is performed with a metallic etch mask. The metallisation corresponds to the top contact of the semiconductor device of interest. The etch profiles of different etching processes was investigated (cf. Fig. 1). The high isotropy of wet chemical etching results in a strong undercut of the metallic mask (Fig. 1a). In addition, the etch profile is further affected by both, a crystal orientation and heterostructure related anisotropy, respectively. This uncertainty inhibits the control of the effective area Aeff of the semiconductor below the metal mask at submicron dimensions.

Fig. 1 Vertical device mesa profile defined by wet (a), hybrid etching (b), and dry (c)etching.

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Annual Report 2006 - Solid-State Electronics Department 29

On the contrary, a pure reactive etching process (Fig. 1c) results in an abrupt profile where the semiconductor mesa directly corresponds to the metal mask or hence to the top contact area. In order to remove the plasma damage from the etch ground and from the sidewall a combined wet/dry etching process may be desirable. The resulting etch profile is depicted in Fig. 1b.

Small-Area Resonant Tunnelling Diodes The investigated Resonant Tunnelling Diode (RTD) consist of a InGaAs well sandwiched between InAlAs double barriers and InGaAs contact layers all grown lattice matched on InP substrate by MOVPE. While the current density J is determined by the intrinsic double barrier layer structure, the absolute current I = J.Aeff is proportional to the effective area of the device. The RTD processing starts with the definition of the top contact area Anom which is used as the etch mask during reactive ion etching. The best results were achieved using a power PICP = 150 W, PRF = 50 W and a gas mixture Cl2(/Cl2+N2) = 0.1. The remaining RTD process is completed with standard technology wet chemical etching for device isolation and a spin on glass (durimid) for the access to the top contact. A complete RTD device is depicted in Fig. 2a. For comparison RTDs have been realized with wet chemical etching, too (see fig. 1a).

Fig. 2 Nominal contact area of RTD top contact: (a) SEM micrograph of the fabricated RTD with 1 µm² top contact area and (b) peak current density of differently etched RTDs

The vertical sidewall profile of the dry etched RTD results in a good scalability of the RTDs peak current density. Figure 2b shows the peak current density normalized on the nominal area of the upper contact which defines the area of the device. The under etching of the wet chemically and hybrid etched devices results in a decreasing peak current density because of the decreased effective area (Aeff < Anom) of the RTD. Figure 2b shows that a scalability on submicron RTD require a dry etching process.

Using a metal mask with a thickness of 300 nm it can be excluded, that the semiconductor is damaged by the plasma. Only a small area of the semiconductor around the protected active RTD material has a higher roughness. A small part of this area is used for contacting the device. Measuring the contact resistance shows no degradation.

a b

10

20

30

40

50

0 2 4 6

nominell contact area Anom [µm²]

peak

cur

rent

den

sity

I/A

nom

[kA

/cm

²]

hybridwetdry

.

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30 Annual Report 2007 - Solid-State Electronics Department

PIN Photodiode A PIN photodiode on InP substrate consists of a thick InGaAs absorption layer sandwiched between a thin highly p-doped top contact and a highly doped n-bottom contact. The InGaAs absorption layer may be as thick as 2 µm for high responsivity diodes. In the previous process the absorption layer was patterned using wet chemical etching. However, at this etching thickness the photo resist becomes severely degraded such that the resist patterning has to be repeated three times for one mesa. The resulting etch profile is depicted in Fig. 3a. The different slopes of the etch profile are attributed to alignment variations of the three resist patterns used.

A dry etching process with a high etch rate shall be developed in order to avoid this uncertainty without degrading the optoelectronic function of the device. The manufacture of the diode begins with the upper ring contact. This contact has to be covered with a removable etching mask in order to etch the first mesa with a dry etching process. In this work an etch mask consisting of SiNx and Ni has been used, which can be removed using hydrofluoric acid. In comparison to the RTD etching process just the plasma power has been doubled to PICP = 300 W (retch = 200 nm/min). The dry etched p-mesa is shown in fig. 3b. The better counter accuracy allows a more reliable manufacturing process for pin-diodes. The measured responsivity of the dry etched pin-diodes were as high as the wet chemical etched one (S = 0.58 A/W). That means that the plasma does no damage to the semiconductor through the etching mask.

Fig. 3 Vertical sidewall profile of the wet chemical etched p-mesa (a) in comparison to a dry etched one (b)

Conclusion During this work dry etching processes for the RTD and the PIN-diode were developed. Thereby an improved reliability and a better counter accuracy of the etched structures could be obtained. The RIE process just enables the manufacture of sub-µm RTDs with a good scalability. The new RIE process applied to PIN provides a good pattern control for a mesa height up to 2µm.

References [1] Serkan Topaloglu, „Process Technology for High Speed InP based Heterojunction Bipolar

Transistors“, Doctoral Thesis, Universität Duisburg-Essen, 2006.

a b

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4.2.2 Modular Concept and Realisation of Balanced PIN Photo-Receiver for QPSK Transmission Systems Suitable for 10 GHz / Channel

Scientists A. Poloczek, I. Nannen

Introduction Quadrature phase-shift keying (QPSK) has attracted much interest for long haul ultra-high bit rate communication systems within the last decade. In order to handle the differential optical signal at the downlink, the o/e- conversion is performed by an balaced photoreciever consisting of two photodiodes per channel. Based on our expertise on PIN-photodetectors, we have developed a modular system which allows further increase of channels per device easily.

Concept

Fig. 1 Design schematic of the receiver modular system consisting of four “basic elements”

The basic design concept is depicted in figure 1. The most simple device with two channels consists of four “basic elements”. Element 1 includes bias feeds and a monitor PIN-diode which is used for fiber alignment during the system assembly. Element 2 (channel) provides two PIN-diodes for QPSK signal detection and integrated MIM smoothing capacitances CS for each detector. Elements 3 and 4 are the appropriate mirrored counterparts. Thus, the channel number can be easily defined

CS CS CS CS

V+ V+V-V- G G GS S

metal (GND)

isolator(spin-on-glas)

metal

PIN-diode

1 2 3 4

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during the design phase by merging the designated amount of basic elements to one device. Finaly, this approach leads to an element with an GSG output with specified pitch distance and symetric bias feeds on the left and right.

Realisation The devices were fabricated using an InGaAs/InP layer stack grown on InP substrate by metal-organic vapour phase epitaxy (MOVPE). The 1700 nm thick PIN-absorption layer consists of lattice matched InGaAs. The processing technology contains wet chemical etching and optical lithography using the design described above. Figure 2 shows optical micrographs of fabricated two- and four channel devices using the modular concept.

Fig. 2 Optical micrograph of realised two-channel (left) and four-channel (right) devices

Measurement Results The DC- and RF-performance of a four channel receiver device has been tested. The PIN-diodes exibit dark currents in the range of 100 nA @ Ubias=-2 V, which are low enough for the desired application.

The RF-measurement was performed using laser source at λ=1.55 µm which was modulated by port 1 of an network analyser (NWA). The bias voltage was supplied via a submount on a ceramic carrier. The electrical response was detected by a GSG RF-probe connected with port 2 of the NWA. As it can be seen in Fig. 3, all diodes exhibit identical frequency responses with a 3 dB corner frequency of 10 GHz.

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frequency response (M3721_H2A1)

-12

-10

-8

-6

-4

-2

0

1,0E+07 1,0E+08 1,0E+09 1,0E+10 1,0E+11

frequency [Hz]

mag

[dB

]

h

Fig. 3 Frequency response of 8 photodetectors belonging to a four channel device

Conclusion We have developed a modular design for QPSK differrential receiver device with which allows an easy extention of the channel number during the design phase. This concept has been prooved by an four channel demonstrator providing high performance with uniform parameters.

Aknowledgement The support by the company CeLight in Washington D.C., USA is greatly aknowledged.

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T1

T2

D1

D2

D3

D4

T3

R1

R2

R3

T5

R4

T6

T7

R5

R6

VS

uout,p uout,n

T4

Rf

C5

second circuit:same as drawn above but seperate power supplies

Vd1 Vd2 Vd3

C6 C7C8

C9

V1-

V1+

V2+

V2-

C1

C2

C3

C4

Cascode to reduce effective input capacitance Differential output stage Buffer Stage

Balanced photo diode pair

4.2.3 Development of a Transimpedance Amplifier with Optical Differential Input

Scientist I. Nannen

Introduction The increased use of optical communication systems results in a higher bit rate, which has to be transported over existing optical fibers. Therefore the complexity and bandwidth of transmitted data hat to be improved. Synchroneous Quadrature Phase Shift Keying (synQPSK) is an extremely attractive modulation format for long haul fiber communication. Thereby the tolerance to polarization mode dispersion and the tolerance against fiber nonlinearities are better compared to standard intensity modulation.

Transimpedance Amplifier Within the synQPSK project, financed by the EU, a three stage transimpedance amplifier was developed. The first stage is a cascode employing two HFET which provides the gain. The transimpedance converter is used as second stage and feedback point for the feedback resistor Rf forming the typical TIA configuration. The third and last stage is a differential amplifier. This stage matches the output impedance to 50 Ω and provides different outputs shifted 180° in phase.

Fig. 1 Opto-electronic Transimpedance Amplifier

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Annual Report 2007 - Solid-State Electronics Department 35

Technology The layer stack of the developed pin-TIAs was grown in a metal-organic vapor phase system with an absorption layer of 1900 nm to get a high dc-responsivity of 0.9 A/W at λ=1550 nm. The employed HFET has a gate length of 250 nm. Because of an annealing step the threshold voltage shifted +0.2 V. Another problem was an unexpected high sheet resistance resulting in resistor values scaled by factor 1.5. Both causes a bias voltage shift in the complete circuit. Nevertheless functionality of the pin-TIA circuit were shown up to 7.5 GHz (expected: 10 GHz) with an unsymmetrical differential output.

Fig.2 Measured differential output voltage (1 GHz) with unchanged layer stack

The topping of the layer stack is mainly responsible for the sheet resistance. It was increased to fit the differences between expected and measured resistor values. Furthermore the transistors were designed with a threshold voltage which is 0.2 V lower than required for circuit functionality. As expected, the annealing step causes a shift of +0.2 V, such that the threshold voltage reaches the value needed for circuit functionality. The thickness of absorption layer was decreased to 1700 nm for a better yield and shorter growth time, which is enough for a bandwidth over 10 GHz and a responsivity higher 0.85 A/W fulfilling the synQPSK project specifications.

s.i. InP:Fe substrate

A

C

GS D

BufferInGaAs Channel

InP

n-InGaAs:Si

InGaAs

p-InGaAs:C

HEMT

pin-diode

InGaAs Increased for correctresistor values

Increased to compensatethreshold voltage shift

1900 nm 1700 nmfor better yield

Fig.3 Changes in layer stack for better yield and correct threshold voltage and sheet

resistance

22.00 22.40 22.80 23.20 23.60 24.00 time / nsec

Am

plitu

de /

mV

33.0

26.4

19.8

13.2

6.6

0

-6.6

13.2

19.8

26.4

33.0

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36 Annual Report 2007 - Solid-State Electronics Department

Measurement For the characterization of the pure electrical bahavior of the TIA, s-parameter measurements were performed. Therefore a circuit with electrical input was used.

The results of these measurements are shown in the next picture. The transimpedance of the circuit is 60 dBΩ with a bandwidth of 10 GHz.

Fig.4 Measured transimpedance of pure electrical circuit

Summary The unexpected high sheet resistance and shifted threshold voltage has been corrected by changes in the layer stack. Measurements on pure electrical circuits with changed layer stack achieved a transimpedance of 60 dBΩ (1000 Ω) with a bandwidth of 10 GHz. References: [1] T.Pfau et al. "First Real-Time Data Recovery for Synchronous QPSK Transmission With Standard DFB Lasers" IEEE Photon. Technol.Lett, vol.18,no.18,September 15,2006

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Annual Report 2007 - Solid-State Electronics Department 37

4.3 Device and Circuit Simulation, Measurement

and Modeling

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38 Annual Report 2007 - Solid-State Electronics Department

4.3.1 Development of a LabView Program for Semiconductor Hall Measurements

Student R. Shabanah Supervisor I. Nannen Technical Assistant: U. Doerk

Introduction Semiconductor transport measurements are routinely done by van-der-Pauw/Hall measurements. In this work a new software platform based on LabView programme has been developed providing a user friendly interface and extended data storage utilities. It replaces the existing platform based on a HP Basic programme. Special emphasis was given in the optimization of the measurement data aquisition. This way the range of measurement conditions offering precise transport data has been successfully extended.

The Program The transport of charged carriers in a semiconductor crystal is affected as by an magnetic field described by the of Lorenz force: ( )LF q v B= ⋅ ×

r rr. If the magnetic field is perpendicular to

direction of current flow, the Lorenz force results into a accumulation of charge in a semiconductor sample which gives rise to the Hall voltage given here for electron transport:

1HV B I

q n d= ⋅ ⋅

⋅ ⋅ . (1) The challenge of Hall measurement is a precise set up of the magnetic field B, the measurement current I, and the precise measurement of the Hall voltage VH in the presence of parasitic conditions like a remaining magnetic field, and a non-symmetric sample. For the control and read-out of the measurement data the LabView (Laboratory Virtual Instrumentation Engineering Workbench) has been adopted. LabView is a graphic programming language. The programming is carried out according to the data flow model. LabView programs are called virtual instruments or simply VIs. VIs consists of two components:

- the front panel, that contains the Graphical User Interface

- the block diagram of the graphic program code.

Fig. 1 shows as an example the programming of the read out of the Hall voltage from a digital multimeter (Keithley 199). Every 0.5 ms measurement data are recorded. In a sub-VI the standard deviation and the mean value of four subsequent data are determined. The data are accepted if the standard deviation is less than 10% of the average value. An error message window will appear if the data are not valid. In the same manner the programming is done for the magnetic field adjustment and the various current source adjustments according to the van der Pauw technique. This program makes it possible to store results of measurement on the computer as HTML file which facilitates the exchange of the results over E-Mail and network. In order to proof the ohmic

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Annual Report 2007 - Solid-State Electronics Department 39

conductivity of all contacts and the degree of symmetry of the sample, an integrated I-V test using the HP parameter analyser HP 4145B has been implemented.

Fig. 1 Block diagram of the read-out of measurement data using Lab View

Results of measurement We report here on the precision of the Hall measurement in a wide range of measurement conditions. For this purpose, two InP-based samples with very different transport data have been selected: a highly p-type doped InGaAs layer as part of a pin diode and a high mobility two-dimensional electron gas of a heterostructure field-effect transistor structure (InAlAs/InGaAs/InP).

Tab.1 shows the results of the initial 4-point measurement without a magnetic field of the van-der-Pauw technique for the determination of the sheet resistance. The measurement current IAB is applied to the contacts AB of the sample and the voltage drop VCD is measured at terminals CD.

IAB [µA] HP-basic VCD [mV] LabView VCD[mV] ∆VCD [%]

5 -0.26 -0.263 -1.2 10 -0.516 -0.518 -0.4 20 -1.02 -1.03 -1.0 40 -2.05 -2.05 0.0 100 -4.10 -4.10 0.0 200 -5.12 -5.13 -0.2 400 -20.5 -20.5 0.0

1,000 -52.0 -52.2 -0.4 2,000 -104 -105 -1.0 4,000 -116 -117 -0.9

Tab.1 Comparision of digital multimeter read-out data of the LabView and the HP basic programme for the sheet resistance determination of p-doped sample without magnetic field.

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40 Annual Report 2007 - Solid-State Electronics Department

Tab. 1 shows that the agreement of voltage measurement of both platforms is very high (< 1%). In addition, the linearity of the measurement results over three orders of magnitude indicates that a very wide range of input currents give a precise measurement result.

Next, the precision and range of measurement with applied magnetic field is investigated. For this purpose the high mobility sample has been chosen. Fig. 2 shows the transport data of two-dimensional electron gas. As the thickness d is unknown, the sheet carrier concentration sn n d= ⋅ (cf. eq. 1) is determined. Both software platforms were investigated in a wide range of applied magnetic fields B. The high precision of the measurement set-up enables a very reliable measurement at a magnetic field strength as low as B = 50 mTesla. There should be no physical dependence of measurement data up to approximately 1Bµ ⋅ ≤ which holds here because the mobility doe not exceed 10,000 cm²/Vs (cf. Fig. 2). Therefore, the higher variation of the evaluated data in comparison to table 1 is attributed to the precision of the set-up of the magnetic field. The relative deviation of the mobility with the basic program is 5.88 % while with the new LabView program a strongly reduced deviation of 1.38 % is achieved.

Fig. 2 Transport data of a two-dimensional electron gas determined at various magnetic field strength. (I = 20 µA, T=300K).

Summary A new LabView program is developed, enabling user friendly van-the-Pauw/Hall measurements with extended data storage utilities. The program has been tested with exemplary samples like a high mobility two-dimensional electron gas and a low mobility p-type doped layer. The measurements shows a good agreement to the previous basic program. In addition, a wide measurement parameter regime for precise HALL measurements and an improved data acquisition could be demonstrated.

2.5

3.0

3.5

shee

t car

rier

conc

entra

tion

ns [

cm²]

8600

8900

9200

9500

0 200 400 600 800

magnetic field B /mT

mob

ility

µ [

cm²/V

s]

HP-BASICLabView

ns

µ

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Annual Report 2007 - Solid-State Electronics Department 41

4.3.2 Concept for an Ultra-Wideband Signal Generator With RTD-HBT Technology

Scientist J. Driesen

Introduction Recently, the Ultra-WideBand (UWB) technology got into the focus of world-wide research and development activities, since it promises a new near-field high data-rate communication and location technology without the necessity of a small bandwith channel. These radio frequency channels become more and more rare due to the rising number of radio standards like GSM, UMTS, ZigBee, WiFi, WLAN, Bluetooth and so on. In UWB technology, a signal with a bandwidth of at least 500 MHz and a center frequency of mostly 5 GHz but with a very low power is used. So it disappears in the background noise for all small bandwidth channels of traditional communication signals. To achieve this, a small peak in time domain is needed as signal to get a broad bandwidth signal in frequency domain.

In literature, mostly CMOS circuits that make use of run-time effects, or alternatively, circuits with step recovery diodes (SRD) are proposed to provide this kind of signals [1, 2]. Both circuit types lack of small peak width (around several hundred picoseconds) and a high repetition rate. An alternative concept is presented here, by using a combined technology with heterojunction bipolar transistors (HBT) and resonant tunneling diodes (RTD).

RTD-HBT Technology As basis for the circuit design, a combined technology for RTD and HBT devices has been developed. Both devices have been integrated by growing the RTD stack on top of the standard HBT layers. A stop layer has been grown inbetween both device stacks to be able to ease the processing and to be able to use them separately from each other. The emitter cap layer of the HBT is used as bottom contact layer of the RTD. Fig. 1 depicts typical layouts for RTD and HBT.

Fig. 1 Photographs of the RTD (left) and HBT (right).

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42 Annual Report 2007 - Solid-State Electronics Department

Both devices have been fabricated and measured. In fig. 2 and 3, typical dc and rf curves are presented for RTD and HBT devices in comparison to the device models that have been fitted to the data.

0

10

20

30

0 0.2 0.4 0.6 0.8 1Ud [V]

Id [m

A]

measuredmodeled

0.68

0.72

0.76

0.8

0.01 0.1 1 10 100f [GHz]

|S21

|

Fig. 2 RTD I-V curve (left) and RF performance (right). Measured data as points, simulated data as curve.

Fig. 3 Gummel-Plot (left) and sample s-parameters (right) of the HBT. Simulated data as black curve, measured data as points.

Concept of the Peak Former In fig. 4, the circuit concept of the peak former is presented. It acts comparable to a differential pair, but with the input signals in phase instead of differential input signals. Therefore, both transistors are operated in the same manner and the currents in both RTD increase equally, so the differential signal of the outputs between the emitters and RTDs stays approximately zero. This is due to the almost equal voltage drop over both RTD operated at these low currents. Since both RTDs have different areas, the peak current of the RTD with the smaller area is reached earlier than that of the other. At the peak current under current mode of the RTD, the voltage drop over the RTD increases in a step from PDR1 into PDR2 region of the diode. Now, there is a certain differential voltage at the output. As soon as the second peak current also has been reached, the differential voltage drops to zero again.

0.4 0.5 0.6 0.7

Ube [V]

Ib, I

c [A

]

IC

IB

10-8

10-6

10-4

10-2

1

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Annual Report 2007 - Solid-State Electronics Department 43

In fig. 4, the differential voltage is presented that appears with a sinusoidal signal of 1 GHz at the input of both transistors. It is a sharp peak with a high possible repetition rate.

Fig. 4 Circuit of the peak former (left) and simulated curves, the differential output signal (Vd = Vout – nVout) and the input signal (left).

Conclusion A concept for an UWB signal generator is presented. The concept study is based on an newly developed technology with RTD and HBT devices. There are several possibilities to extend this basic circuit, e.g. the circuit for the differentiation, the input signal generation, maybe a combination for a multiplier circuit to be able to modulate the output signal train. But also this simple basic concept demonstrates a circuit for generating peak impulses for UWB applications that overcome the lacks of alternative concepts in literature.

References: [1] J.W. Han and C. Nguyen, “A New Ultra-Wideband, Ultra-Short Monocycle Pulse Generator with

Reduced Ringing,” IEEE Microwave and Wireless Comp. Lett., Vol. 12, No. 6, pp. 206-208, 2002,. [2] R. Xu, Y. Jin, C. Nguyen; "Power-Efficient Switching-Based CMOS UWB Transmitters for UWB

Communications and Radar Systems", IEEE Transactions on Microwave Theory and Techniques, 54(8), pp. 3271–3277, August 2006.

[3] J. Driesen; "Design von schnellen Heterostruktur-Bipolar-Transistoren für den Einsatz in Schaltungen mit Resonanz-Tunnel-Dioden", Dissertation, University of Duisburg-Essen, February 2008

R3

UCC

T1

T2

T3 T4

Ud

Ue

D1

A = 10 µm²D2A = 12.5 µm²

200 Ω

HBT emitter area

1x15 µm²

-10

0

10

20

30

t [ns]

Ud

[mV]

0

0.5

1

1.5

2

2.5

Ue

[V]

0 0.4 0.8 1.2 1.6 2.0

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44 Annual Report 2007 - Solid-State Electronics Department

4.3.3 Design and Simulation of an Electrical Input Circuit for an UWB-Pulse-Generator Based on Resonant Tunneling Diodes and Heterostructure Field-Effect Transistors

Student: Ö. Kharaman Supervisor: A. Matiss

Introduction and technology In this student report, an electrical input circuit on the basis of III/V-Heterostructure-Field- Effect-Transistors to an existing UWB-Pulse-Generator has been designed, implented and studied. The focus was hereby on the development of the input circuit and the necessary simulations. The goal was the preservation of the function of the pulse generator for the use in UWB range up to 10 GHz.

Given circuit setup Two in series connected Resonant Tunnelling Diodes were building a mobile which can be controlled through a current source input in its switching behaviour. Out of two mobiles, a pulse generator was realized. How the pulse generation was done, can be illustrated in the following graphic:

Fig. 1 Graphical illustration of pulse generation

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Annual Report 2007 - Solid-State Electronics Department 45

Device layouts and Results The replacement of the current source by a High Electron Mobility Transistor (HEMT) as a voltage controlled current source resulted in the aimed switching behaviour of the mobiles, but also in an unstable attitude around the voltage input values for the switching. Therefore the input circuitry had to be adjusted by an impedance converter to stabilize the output signals for the resulting input voltage values. In addition to that, an adaptation to the 50Ω environment was possible. Furthermore the inquiries of the mobile outputs showed that the load currents were dependent on the load impedances. Through simulations the impedance values of 5kΩ have been acquired. On this account the mobile outputs had to be decoupled to keep the function in an 50Ω environment and to be able to have an independent switching characteristic of the mobiles. With one more impedance converter the desired characteristics resulted in the following circuit layout. To show the resulting UWB-signal to an incoming digital signal, the input signal is generated by a bit-sequence-voltage-source.

Fig. 2 Resulting circuit

The resulting UWB-signal is shown in the figure underneath. Here it is good to follow that a “High” input leads to a switching and a “Low” input to a non switching characteristic of the mobiles. By controlling the switching mechanism of the mobiles the generation of any gauss pulse is over this circuitry possible.

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46 Annual Report 2007 - Solid-State Electronics Department

Fig. 3 Pulse generation through a bit sequence

Results An input circuit was designed and tested for the application of a pulse generator at an operating frequency of 10GHz. Due to stabilizing and functionality factors, it was necessary to device a single level input and output circuit. The complexity of the whole circuit is with the usage of four HEMT’s low. The switching mechanism was realized through a voltage drop from 0V to -1,2V. Furthermore it was a reduction from four to two supply voltages feasible. Simulations with 10% deviation of the used resistance values, which can occur during manufacturing processes, resulted in the same and aimed switching characteristics of the mobiles as before.

In total, a better control of the pulse generator through little device additions and a lesser power consumption was implemented and tested.

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Annual Report 2007 - Solid-State Electronics Department 47

4.3.4 2D Physical Simulation of Conventional InP Based Hetero-structure Field-Effect Transistors and Nanowire Field-Effect Transistors

Student: S. Makhlouka Supervisor: W. Brockerhoff

Introduction In recent years all types of computer simulations have become more and more important, especially in the field of semiconductor devices. Since the complete device processing is very cost- and time-intensive, an easier approach is use to numerical simulations when examining modifications within a structure or even for complete redevelopments. The most important part is that the simulation software in use is able to accurately simulate the physical properties of real devices. An applicable software is provided by the company Silvaco in terms of their Technology Computer Aided Design (TCAD) programs. In this work, InP based heterostructure field effect transistors (HFET) and within the reduction of device structures, InAs nanowire field effect transistors (NWFET) will be investigated using the physical simulator Atlas. III-V semiconductors like InAs, InP or InGaAs have become more important in recent years for applications at highest frequencies. The mobility of charge carriers in III-V semiconductors is considerably higher as for example in silicon. Because of their band structure they are further appropriate for the layout of optoelectronic circuits.

Simulation of InP based HFET At the beginning of this work the necessary material parameters have been calibrated on the basis of measuring data of real devices. To demonstrate the potential of the physical simulator, the electrical properties inside the devices were investigated. In fig. 1 the electron concentration is shown for two different operating points.

Fig. 1 Electron concentration in the HFET a) VGS=0,0V and VDS=3,0V and b) VGS=-0,4V and VDS=3,0V

a) b)

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48 Annual Report 2007 - Solid-State Electronics Department

In fig. 1 the electron concentration is shown. At VGS= 0V and VDS= 3V (fig. 1a) the density in the channel layer is high whereas biased near pinch-off (VGS= -0.4V and VDS= 3V ) the concentration in the channel layer is strongly reduced (fig. 1b), as expected

Furthermore, investigations of the DC output- and transfer-characteristics as well as the RF characteristics have been performed.

The theoretical HFET investigations have been compared to real data from HFET fabricated at the department. Simulations based on the real device geometry exhibited very good agreements in terms of the DC characteristics and the small signal parameters like transconductance, gate-source-capacitance and transit frequency. Solely the output characteristics in the saturation region showed some discrepancies because of the Kink-Effect, partly due to impact ionization, that was not implemented in the model.

The investigations of the dependence of technological parameters on the device characteristics demonstrated the strong influence of the doping concentration and the gate-length. Increasing the doping concentration led to a considerable shift of the threshold voltage to negative gate-source-voltages (s. fig. 3) and to an increasing drain current. The reduction of the gate-length resulted in an improvement of the high frequency performance due to higher transconductance values and transit frequencies. Other layout parameters like ohmic contact spacings or InP cap-layer thickness have shown that they are of little importance regarding to high frequency applications.

a)

0

2

4

6

8

10

12

14

16

0,0 1,0 2,0 3,0Drain-Source Spannung VDS [V]

Dra

in-S

trom

I D [m

A]

- Messung - - Simulation

VGS=0,4V

VGS=0,3V

VGS=0,2V

VGS=0,1V

VGS=0,0V

VGS=-0,1V

VGS=-0,2V

b)

0

2

4

6

8

10

12

14

16

-0,7 -0,5 -0,3 -0,1 0,1 0,3 0,5 0,7Gate-Source Spannung VGS [V]

Dra

in-S

trom

I D [m

A]

SimulationMessung

c) -200

-100

0

100

200

300

400

500

600

-0,7 -0,5 -0,3 -0,1 0,1 0,3 0,5 0,7

Gate-Source Spannung VGS [V]

Stei

lhei

t gm

[mSm

m-1

]

SimulationMessung

Fig. 2 Comparison of measured and

simulated data a) output characteristics b) transfer characteristics c) transconductance

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Annual Report 2007 - Solid-State Electronics Department 49

Fig. 3 Variation of the doping concentration

Simulation of InAs Nanowire FET The simulations of the Nanowire FET (NWFET) showed very promising results. On the basis of detailed investigations inside the device an accumulation of charge carriers was shown at the hetero junction. Increasing the drain-source-voltage resulted in a separation of an accumulated region at the drain-contact and a depleted region near the source contact (s. fig. 4).

Fig. 4 Electron concentration in the NWFET

0

10

20

30

40

50

60

70

-1,0 -0,8 -0,6 -0,4 -0,2 0,0 0,2 0,4 0,6

Gate-Source Spannung VGS [V]

Dra

in-S

trom

I D [m

A]

Nd=1,0e18Nd=2,5e18Nd=5,0e18

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50 Annual Report 2007 - Solid-State Electronics Department

Fig. 5a shows the 2D potential distribution in the NWFET. The parasitic resistances of the NWFET could be extracted from of the electrical potential distribution along the channel as demonstrated in fig. 5b.

Fig. 5 a) 2D potential distribution in the NWFET b) 1D potential distribution in the NWFET along the channel

The data from numerical results where compared with experimental data as well as with theoretical data calculted on base of the well known conventional and analytical MOSFET model.

The comparison of the simulated output- and transfer characteristics (fig. 6) demonstrates good agreement, especially in the saturation region for small gate-source voltages. Solely the results from the conventional analytical MOSFET model diverge in the ohmic region due to fact that parasitic resistances are not taken into account within the simple model.

a)

a)

b)

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Annual Report 2007 - Solid-State Electronics Department 51

Fig. 6 Comparison of simulated, measured and modeled data

Conclusion The functionality as well as the flexibility of the TCAD software was demonstrated. The software is able to simulate all significant DC characteristics as well as the significant small signal parameters of InP-HFETs and InAs nanowire FETs.

0,00

0,05

0,10

0,15

0,20

0,0 1,0 2,0 3,0

Drain-Source Spannung VDS [V]

Dra

in-S

trom

I D [m

A]

- MOSFET Modell - Simulation - Messung

VGS=1,4V

VGS=1,0V

VGS=0,6V

VGS=0,2V

VGS=1,2V

VGS=0,8V

VGS=0,4V

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52 Annual Report 2007 - Solid-State Electronics Department

4.3.5 Characterization of a 1:2 Optoelektronical Demultiplexer Based on Monostable-Bistable Logic Elements

Scientist A.Matiss and A.Stoehr, Optoelectronics Department

Introduction The measurement of a realized optoelectronic demultiplexer based on resonant tunneling diodes is presented here. Full 1:2 demultiplexing with a complementary MOBILE configuration is demonstrated up to 2 x 6.6 Gbit/s.

Description of Demultiplexer circuit The invesitgated circuit is shown in figure 1. Four resonant tunneling diodes form two MOBILE gates that are connected to both nodes of a common current source [1]. The MOBILE are clocked alternatingly in order to output every second bit to the respective output of one MOBILE.

RTD

2,lo

ad

Icon=f(Uin)

RTD

1,dr

iver

Ineg

RTD

2,dr

iver

RTD

1,lo

ad

Ipos

U1,out,neg U2,out,pos

U1,ref,neg U2,clk,pos

U1,clk,neg U2,ref,pos

MOBILE 1 MOBILE 2

AT<AL

I1

I2

Fig. 1 Demultiplexer circuit setup consisting of four resonant tunneling diodes.

For the measurements, the current source has been realized using a pin-photodiode.

Measurement Setup A measurement setup consisting of a 13.2 Gbit/s bit pattern generator is used to test the demultiplexing circuit. The data signal is modulated on an optical fibre using an electro absorption

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Annual Report 2006 - Solid-State Electronics Department 53

modulator with a bandwidth of 13 GBit/s. The clock signal to synchronize the circuit is also supplied from the bit pattern generator. Figure 2 shows the complete measurement setup.

DemultiplexerfClk

Bit Pattern Gen.

LO

CLK

DATA(NRZ)

CLK

DATAOUTP

OUTN

fData

Sampling Oscilloscope(fClk=fData)

(optical)

Fig.2 Measurement setup including a bit pattern generator and the optical 1:2 demultiplexer

Due to the common clock and data signal from the bit pattern generator, both signals share the same frequency. In order to drive the demultiplexer in the full 1:2 mode, only half the data frequency has to be applied to the clock input. Despite this, by using the same data and clock frequency, every incoming bit will be sampled twice, still demonstrating the capabilities of the demultiplexer. The output of the circuits have opposite polarities and the signal will have Return-to-Zero (RZ) format due to the specific characteristics of the MOBILE circuits used here. The incident optical signal has Non-Return-to-Zero format (NRZ).

28 29 30 31 32 33 34-75

-50

-25

0

25

50

75

outp

ut v

olta

ge /

mV

time / ns

pos neg

optical bit-pattern: 00001111

fclk=6.6GHzfdata=6.6GBit/s

Fig. 3 Output bit pattern 11110000 of the demultiplexer

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54 Annual Report 2007 - Solid-State Electronics Department

The functionality could have been verified up to 6.6 GBit/s for every output channel, as demonstrated in figure 2.

Fig. 3 Eye diagram of the negtive output of the demultiplexer

The input signal consists of a '00001111' string which is accurately sampled by the demultiplexer. Both outputs, the negative and positive, both sample the same bit with a phase delay of 90°. Since the function of the demultiplexer MOBILE stages inverts the incoming signal, every '0' at the output corresponds to a '1' at the fibre input. All measurements have been taken with a sampling oscilloscope with a bandwidth of 50 GHz. In order to verify the quality of the signal and to estimate the bit error probability, an eye diagram measurement has been done for the negative output at 6.6 GBit/s. The resulting eye is presented in figure 3 and shows clear eye openening for a RZ-coded signal as well as very low timing jitter and low noise influence. Therefore a low bit error rate can be estimated for this demultiplexer.

Summary A new optical 1:2 full demultiplexer in RTD-MOBILE technology has been successfully measured using an optoelectronical measurement setup up to 2x6.6 Gbit/s by oversampling the input bit stream. In a system setup, the full achievable data rate at the input would be 13.2 Gbit/s while both outputs operate at 6.6 Gbit/s. Furthermore very low jitter and low noise yield a low bit error rate.

References [1] A. Matiss, W. Prost, F.-j. Tegude, "Optoelectronic 1:2 demultiplexing based on resonant tunnelling

diodes and pin-photodetectors", IEE Electronics Letters, vol. 42, no. 10, pp. 599-600, 11 May 2006

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4.3.6 Development of RTD/HBT Oscillator for Ku- and Ka-Band Applications

Student: B. Münstermann Supervisor: A. Matiss

Introduction Because of their application in satellite communication low power consumpition of K-Band voltage controlled oscillators (VCO) is crucial. Resonant tunneling diodes exhibit non-linear current-voltage characteristics with a negative differential resistance regime at low voltages and are therefore applicable as low-power active devices in oscillators. Combined with InP-HBT technology VCO’s with oscillation-frequencies up to 23 GHz have been reported [1,2]. In this work, simulations based on a scaleable large-signal RTD model are presented and different approaches to increase the RF-power and phase noise performance are proposed. The optimized circuit topology have been realized in layouts for single-ended and balanced VCO-circuits.

Scaleable large-signal model Basically, the large-signal behaviour of RTD’s can be described by a voltage-controlled current source in parallel to a capacitor CRTD, depending on the voltage Vc across the barrier structure (Fig. 1). The resistor Rs is added with respect to the resisive losses of the contact layers. The parameters to fit the DC- and AC-curves have been determined as described in [3], using the semi-physical current equations of Tsu and Esaki.

Fig. 1 Large-signal equivalent model

Time-domain behaviour of RTDs in VCOs To describe the behaviour of RTD-oscillators the simplified model shown in Fig. 2a can be used. The ohmic losses of the resonator are represented by the conductance gL. To enable oscillation these losses have to be compensated by the negative conductance ga of the active device. If condition (1) is met the RF-power at the oscillation frequency originated from noise will be amplified until the quasi-stable state (2) of the oscillator is reached.

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0)()( <+ oscLosca gg ωω (1)

0)()( =+ oscLosca gg ωω (2)

When using RTD’s as active devices, the limitation of amplitude depends on the width of the NDR-region. As seen in Fig 2b, the differential conductance gRTD fulfils condition (1) for voltages in a small voltage range around the optimal bias point VRTD,opt.

Fig. 2 Simplified model of NDR-oscillators (a) and time domain behaviour of the RTD oscillating at 20 GHz (b)

For K-Band frequencies a resonator, consisting of a lumped inductor and a varactor-diode in parallel, has been designed by using electro-magnetic-field simulations. The resonator can be tuned between 18,5 GHz and 21 GHz by applying voltages between 0 V and 4 V and exhibits a quality factor of 22 at the center frequency 20 GHz. The dynamic I/V characteristic of the RTD, plotted in Fig. 2b, has been simulated at a bias-voltage VRTD,opt = 0.41 V and showed a peak-to-peak voltage Vpp = 240 mV.

Optimization of available RF-power The signal power available from RTD-oscillators depends on the available gRTD at the bias point and on the width of the NDR-region. One way to improve these properties is to use an RTD-pair. Here two identical RTD’s of identical areas, connected in series and biased with opposite voltages, are used to create a negative conductance at the center node P (Fig. 3). The I/V-characteristics of the RTD-Pair can be influenced by varying the voltage |VRTD| to improve the differential conductance as needed for optimizing output power. Transient simulations of the RTD-pair oscillator provide an improvement of 3.4 dB signal power.

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Fig. 3 RTD-pair and its I/V-characteristics

For the use in K-Band applications the RTD-pair is integrated in the balanced VCO-circuit shown in Fig. 4. Two identical RTD-VCO circuits are combined to form a virtual ground at the node between the varactor-diodes leading to a fixed phase relation between the output voltages. To isolate the VCO-core from the measurement environment an output buffer stage, consisting of an HBT in collector configuration, was added. In this configuration the differential RF-power was improved by additional 6 dB in comparison with the single RTD-pair without increasing the noisepower. To investigate further optimization possibilities the RTD-model was modified by increasing the peak to valley current ratio (PVCR) and the peak voltage of the RTD to create wider NDR-regions. This optimization yields additional enhancement of signal power up to 6.3dBm.

Layout The circuit design was implemented in a 1mm x 1mm layout for on-wafer characterization. To overcome the bias-instability, caused by spurious oscillation in the bias lines, large shunt capacitors have been added. The DC-power supply is realized from both sides to ensure the symmetry of the balanced VCO.

Fig. 4 Schematic and layout of the balanced VCO-circuit

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Summary In this work the time-domain behaviour of RTDs in K-Band oscillators has been investigated, to reveal possible improvement in performance. Furthermore a new balanced-VCO with a wide tuning range of 2.5 GHz and an optimized outputpower up to 6.3dBm has been developed and realized in a circuitlayout.

References [1] S. Choi, Y. Jeong, and K. Yang, “Low DC-Power Ku-Band Differential VCO Based on an RTD/HBT

MMIC Technology”,IEEE Microw. And Wirel. Comp., vol. 15, no. 11, pp.742-744, 2005 [2] S. Choi, K. Yang, “Low-voltage low-power K-band balanced RTD-based MMIC VCO”,Microw.

Symp. Digest, p.743-746, 2006 [3] A.Matiss, A. Poloczek, W. Brockerhoff, W. Prost and F.- J. Tegude “Large-Signal Analysis and AC

Moedlling of Sub Micron Resonant Tunneling Diodes”, Europ. Microw Conf., pp.207-210, 2007

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4.3.7 Modification of Hardware for the Communication Between Rotary Encoder and PC-Interface

Student B. Münstermann Supervisor I. Nannen Technical Advisor J. Kötting (Lenord+Bauer & Co. GmbH)

Introduction This student report was made in collaboration with the Company Lenord, Bauer & Co. GmbH, which develops innovative automation systems for industrial motion sequences. One of its main expertises are heavy-duty rotary sensors based on magnetic resistance measurements. In this work, an interface-hardware has been modified and manufactured to enable bidirectional communication between a personal computer and the magnetic absolute rotary encoder GEL 235 via the USB-Port. In addition to the conventional USB-Interface chips an A/D converter was integrated on the interface hardware to access the analog signals of the sensor. A new Software has been developed to read out and visualise the converted data.

Magnetic rotary encoder GEL 235 The absolute rotary encoder, given in this work, returns for each angular position a unique data value via the digital interface with a resolution up to 28 bit. The measurement principle is based on the magnetic scanning of a ferromagnetic code disc by using GMR-sensors (Fig. 1a). Hereby the phase relation between the sinusoidal signal of each track of the disc (Fig. 1b) is used to encode the angle by using the so called “nonius-principle”. With an additional mechanical gear the absolute number of turns is also measured and processed by the integrated interpretation hardware. To enable real time control, the outer track of the disc is scanned by additional GMR-sensors, wich generate sine- /cosine-signals with 64 periods per turn. The analog output is implemented by differential output buffers.

Fig. 1 Cross section of the magnetic absolute rotary encoder (a) and the metallic code disc (b)

a) b)

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The USB-interface card The designed interface card manages the two types of data, available from the GEL235, as shown in the block diagram Fig. 2. To interprete the digital data the company iC-Haus provides the iC-MB3-Chip. This programmable IC can process the BiSS- and SSI-data, delivered by the GEL235, and provide them on the SPI-Bus. The link to the USB-interface has been realized by using the FT2232D which allows the interpretation of SPI-commands and offers an additional parallel port to scan data from the additional 8-Bit analog to digital converter.

Fig. 2 Block diagram of the designed interface-card

To sample the analog signals the chipset has been extended by the ADC0804 from National Semiconductor. The converter can operate in self-clocking mode, so no additional oscillators are necessary. This mode ensures a continuous sampling of the sine wave with 9700 samples per second with a resolution of 8 bit. The sampling range is adjustable by two reference voltages, adjustable by potentiometers.

Fig. 3 Designed and manufactured interface card

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The schematic and layout of the new interface-hardware, including the A/D-conversion and the digital communication chipset on one interface card, has been developed with the EAGLE Software from CadSoft. The manufactured board, shown in Fig. 4, uses two copper layers to realize the electrical interconnections and has a size of 10 x 6cm.

Software Apart from the used conventional software for testing the digital chip set a new labView software has been developed, which enables the read out of the second port of the USB-interface chip FT2232D and plots the recieved data in realtime. In Fig. 4 an example of the visualized waveform is illustrated.

Fig. 4 Converted signal displayed by the labView software

Summary In this work a modified interface card has been developed to enable digital communication with magnetic absolut rotary encoder devices of the GEL235 series. In addition to the convential interface cards the hardware is extended by an integrated analog to digital converter to sample the highly interpolateable sine-/cosine-signals. The sampled data can be read via the USB interface by using the developed interface-software implented in labView. The designed hardware has been manufactured to demonstrate the advanced features of the new interface card.

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4.4 Nanoelectronics

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4.4.1 Gate Length Scaling of InAs Nanowire Field-Effect-Transistors

Scientist K. Blekker

Introduction Nanowire (NW) transistors have gained an enormous interest over the last years. While outstanding device performance has already been demonstrated [1], modeling of InAs NW transistors is still in a very early stage. In order to investigate the dependence of transistor performance on gate length LG a complete set of InAs NW transistors was fabricated. Scalability of experimental transconductance versus gate length has been compared to modeled data using long-channel MOSFET equations.

Fabrication InAs nanowires with a diameter of 30 to 50 nm were synthesized via vapor-liquid-solid (VLS) growth mode [2] in a low-pressure MOVPE. Details on growth can be found elsewhere [1]. To use the most common top-gate configuration, the nanowires were transferred onto insulating carrier substrates. Drain and source contacts were patterned by e-beam lithography and lift-off technique, also used for patterning of room temperature deposited silicon nitride (SiNx) gate dielectric and gate metallization. A self-aligned gate as depicted in Fig. 1 was chosen to reduce serial resistance to a minimum and allow a very short gate length. In this investigation the gate length was varied from 2 µm to less than 150 nm.

Fig. 1 Top view (a) and cross-section (b) of a nanowire FET with a self-aligned gate

Results All devices exhibit n-channel characteristics with high output current and transconductance. Fig. 2a shows an output characteristics ID-VDS of a single InAs nanowire FET with a gate length of LG = 870 nm and 30 nm SiNx gate dielectric. The maximum transconductance of this FET divided by the nanowire diameter representing channel width is g*

m = 615 mS/mm at VDS = 1.5 V. Transistors with smaller gate length tend to higher output conductance, while pinch-off behaviour degenerates. Fig. 2b shows an output characteristics of a NW-FET with a gate length of LG = 430 nm. The maximum normalized transconductance of this FET is g*

m = 1.05 S/mm and the normalized channel current is up to >2 A/mm.

a b

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0,0 0,5 1,0 1,5 2,0

0

10

20

30

40

50

60

drai

n cu

rrent

I D [µ

A]

drain-source voltage VDS [V]

M3712bB3 F7T2

VGS = -0.5V - 2.5 V: steps 0,5 VLG = 870 nmd = 43 nm

0,0 0,5 1,0 1,5 2,00

20

40

60

80

100 VGS = -0.5V - 2.5 V: steps 0,5 VLG = 430 nmd = 43 nm

drai

n cu

rren

t ID [µ

A]

drain-source voltage VDS [V]

M3712aB2 F4 T1

Fig. 2 Output characteristics of single InAs nanowire FET with a gate length of LG = 870 nm

(a) and LG = 430 nm (b)

The transconductance was studied in linear region at VDS = 0.02 V in order to reduce the impact of parasitic series resistances. Following the long channel MOSFET model [3], the transconductance is inversely proportional to LG as given in g*

m = µ·C’G·VDS/(LG·dnw), where µ is the electron

mobility, C’G is the gate capacitance per length unit, and dnw is the nanowire diameter. C’

G was calculated from electrostatic field simulation in previous works [4]. Fig. 3 shows that modeled data using this equation is in good agreement with the experimental values down to a gate length of about 400 nm. Below, ballistic transport is expected to set in and therefore causing a weaker dependence on the gate length.

0,0 0,5 1,0 1,5 2,00

20

40

60

80

100

120

trans

cond

ucta

nce

g*m

[mS

/mm

]

gate length LG [µm]

g*m M3712bB2

M3712bB3 M3712bB4

VDS=0,02V

Fig. 3 Normalized transconductance g*

m in linear region versus gate length LG: experimental values (rectangles, triangles and dots) and modeled data using long channel MOSFET equations (solid)

a b

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Conclusion As a further step towards modeling of InAs NW-FET, gate length scaling was studied in this investigation. The experimental values figured out in linear region show that transconductance is inversely proportional to the gate length in a wide range. Below a gate length of 400 nm, transconductance shows a weaker dependence.

Acknowledgement This work was supported by SFB 445 and SPP 1165.

References: [1] Q.-T. Do, K. Blekker, I. Regolin, W. Prost, and F.-J. Tegude "High Transconductance MISFET With a Single InAs Nanowire Channel" IEEE Electron Device Letters, vol.28, no.8, pp. 682-684, August 2007 [2] R. S. Wagner and W. C. Ellis "Vapor-Liquid-Solid Mechanism of Single Crystal Growth" Appl. Phys. Lett, (4) pp. 89-90, 1964. [3] S.M. Sze "Semiconductor Devices" John Wiley & Sons, 2001 [4] K.Blekker, Q.-T-Do, I. Regolin, W. Prost, and F.-J. Tegude "Scalable Transconductance of Single n-doped Nanowire Transistors by Variation of Gate Dielectric

Thickness" Nanoelectronics Days Aachen, September 2006

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4.4.2 S-Parameter Measurements of Nanowire Field Effect Transistors

Scientist A.Matiss and T. Do

Introduction Nanowire transistors have been found to exhibit very high transconductance within the DC characteristics. For the high frequency analysis of these devices, certain requirements concerning the measurement setup and the de-embedding procedure of parasitics have to be discussed and investigated.

The fabrication details on InAs nanowire-transistors are discussed in section 4.2.

DC-Characteristics The measured IV-charateristics of a two finger gate nanowire transistor in figure 1 confirms very good current saturation and pinch off behaviour of the nanowire structure. The transconductancs that can be determined from the measurements exhibit a gain of 40 µS for a nanowire with 35 nm diameter.

0,0 0,5 1,0 1,5 2,0

0,0

20,0µ

40,0µ

60,0µ

80,0µ

100,0µ

I d / A

Vds / V

Vgs: 2.5 V 2.0 V 1.5 V 1.0 V 0.5 V 0.0 V -0.5 V

Fig. 1 DC characteristic of a two finger gate nanowire field effect transistor (Vgs from –0.5V

to 2.5V, step 0.5V)

We recently reported, that InAs nanowire transistors exhibit a very high DC-transconductance [1].

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Parasitics Contact structures are required that allow on-wafer measurements of the nanowire devices. Due to the very low device capacitance and gain, the contact structure parasitics have to be keep very low for accurate rf-measurements.

Fig. 2 Parasitics of contact structure for nanowire transitor rf-measurements

Special attention has to be paid for the extraction of CIO due to the very low gate-drain capacitance Cgd of the nanowire transisotor, which can be in the same order as the input to output capacitance. Therefore special deembedding test structures have been developed that allow a precise calculation of all parasitic elements. In order to reduce parasitics influence even further, probe tips with the lowest pitch commercially available (pitch = 50 µm) have been employed for the on-wafer measurements.

Scattering parameters and de-embedding The vector signal analyser has been calibrated using an OSLT-calibration technique. With the contact structure calculated from open and short measurements of test structures all measured s-parameter files have been corrected for the pads influence. An example for the correction of the transmission parameters is shown in fig. 3. The left polar diagramm shows the raw measured s-parameters still including the contact structures parasitics, while the right polar diagram has been corrected for the parasitics and show the s-parameters of the nanowire itself. Investigating the influence, the isolation of the pad-structure on InP resulting from the input-output capacitance CIO of the pad strongly limits the rf-performance in the high frequency range.

NanowireTransistor

CPD

LD

LS

LG

CPG

Gate

Source Source

Drain

CIO

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Fig. 3 Measured transmission s-parameters and corrected for the pad-parasitics for Vgs=0.5V and Vds=1V.

Furthermore, the output power to 50 Ohm of the nanowire-FET is very small and thus difficult to detect accurately with the s-parameter test set. Noise becomes a critical parameter when measuring nanoscale DUTs with low output powers. In order to improve the signal quality, a high averaging of frequency point data has been using to reduce noise influence.

Summary S-parameter measurement of nanowire transistors are strongly limited by the parasitics of the pad structure. By downscaling of the pad-size to 50 µm probe tip pitch the parasitics can be strongly reduced. Another problem the occurs is the detection of very low output powers of the nanowire FET. By increasing averaging at the test set this could be improved a little.

References [1] Q.T. Do, K. Blekker, I. Regolin, W. Prost, F.-J. Tegude, " High Transconductance MISFET With a

Single InAs Nanowire Channel", IEEE Electron Device Letters, Vol. 28, No. 8, pp.682-684, 2007

-0.008

-0.006

-0.004

-0.002

0.000

0.002

0.004

0.006

0.008

-0.010

0.010

freq (45.00MHz to 21.88GHz)

S_d

e(1,

2)S

_de(

2,1)

-0.04

-0.03

-0.02

-0.01

0.00

0.01

0.02

0.03

0.04

-0.05

0.05

freq (45.00MHz to 21.88GHz)

S(1

,2)

S(2

,1)

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4.4.3 Low Capacitive Pad- and Gate- Configuration for Ultra High Frequency Single Nanowire Transistors

Scientist K. Blekker, A. Matiss

Introduction InAs nanowire transistors are promising canditates for future high speed electronic devices. Despite of theoretically derived cut-off frequencies up to THz regime [1], high frequency characterization of single nanowire field-effect-transistors (NW-FET) still remains a challenge. The main diffulties to overcome are low device capacitance [2] in comparison to the environment and small absolute value of signal power. Therefore, a coplanar waveguide pad configuration has been optimized towards low capacitance. The pads were used in two different processes for self-aligned gates, minimizing series resistance and hence giving raise to signal power. To avoid high parasitic capacitance due to the gate overlapping drain and source, a totally new approach applying negative tone resist has been studied.

Pad Configuration Fig. 1 shows the coplanar waveguide pad configuration developed for single nanowire transistors. Along with pad width and distance between designed to fit 50 Ω environment, a smaller pitch reduces pad size and therefore capacitance significantly. Thus, a small pitch of p = 50 µm instead of common 150 µm was chosen. A two finger gate as shown in the inset of Fig. 1 was used allowing a symmetric pad design.

Fig. 1 Layout of the coplanar waveguide pad configuration with a two finger gate (inset)

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Optimal coplanar pad length l was determined experimentally as follows: The layout presented above was fabricated with varying l on a GaAs substrate coated with 150 nm SiNx. Small signal scattering parameter measurements and extraction of parasitic capacitance were carried out for open structures. The equivalent circuit model is shown in Fig. 2 along with the extracted values for gate-source capacitance Cpg, drain-source capacitance Cpd, and gate-drain capacitance Cio at 10 GHz. The gate length is LG = 1.5 µm.

Fig. 2 Equivalent circuit model of the open structure (left) and extracted values (right)

Cpg and Cpd decrease with l, while Cio increases slowly. Therefore, l should be adjusted to the smallest value allowing reliable positioning of probes. For these purposes a lenght of l = 80 µm seems to be most practical for further investigations. Low influence of l indicates that the inner part around the self-aligned gates is the crucial factor. The parasitic capacitance is still high compared to the intrinsic capacitance of a single InAs NWFET of up to about 1 fF.

Gate Configuration The open structures characterized above were fabricated using positive tone e-beam resist exclusively. First, drain and source pads were patterned, then SiNx gate dielectric as well as gate metallization in a second step. The gates were exposed overlapping drain and source, so that the NW is covered over the whole length. In this way, no additional serial resistance emerges and hence signal power rises. A cross section perpendicular to the gates is shown in Fig. 3.

Fig. 3 Cross section of self-aligned gates along NW (shown in the inset of Fig. 1)

Due to the self-aligned method a high parasitic capacitance arises. To maintain the advantages of self-aligned gates but not pay for it, a new process applying negative tone e-beam resist to define drain and source was developed. Exposure parameters as well as developer dilution had to be optimized carefully to allow a lift-off process. This technique results in drain and source contacts with undercut edges as shown in Fig. 4.

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Fig. 4 Cross section showing the undercut edges of drain and source due to the use of negative

tone resist

Patterning of gate dielectric and metallization was carried out using positive tone resist. The undercut edges of drain and source cause the evaporated gate metallization to be discontinuous and therefore no additional capacitance emerges as a result of self-aligned technique. With this process, open structures with a coplanar pad length of l = 80 µm were fabricated. Tab. 1 shows the parasitic capacitance values for two different LG.

Tab. 1 Parasitic capacitance values for open structures fabricated with advanced process

In comparison to the values above, Cpg is reduced to about the half and Cio to a fourth. Cpd shows a small increase, thought to be due to higher contact width needed for a reliable lift-off. The parasitic capacitance decreases with LG as expected. Besides, smaller LG also promises a higher cut-off frequency and hence points out the next step towards ultra high frequency NW-FET.

References: [1] Q.-T. Do, K. Blekker, I. Regolin, W. Prost, F.-J. Tegude "Experimental and modelled transconductance of InAs Nanowire-FET" Symposium on Semiconductor Nanowires, Eindhoven, September 19th, 2006 [2] Q.-T. Do, K. Blekker, I. Regolin, W. Prost, and F.-J. Tegude "High Transconductance MISFET With a Single InAs Nanowire Channel" IEEE Electron Device Letters, vol.28, no.8, pp. 682-684, August 2007

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4.5 Conference Contributions

1. Integrated InGaAs pin-diode on exactly oriented silicon (001) substrate suitable for 10 Gbit/s digital applications

A. POLOCZEK, M. WEISS (1), S. FEDDERWITZ (1), A. STÖHR (1), W. PROST, I. JÄGER (1), F.-J. TEGUDE (1) Dept. of Optoelectronics, University Duisburg 20th Annual Meeting of the IEEE Lasers and Electro-Optics Society (LEOS), Lake Buena Fista, Fl, USA, 21.10.2007 - 25.10.2007

2. A Four-Resonant-Tunneling-Diode (4RTD) NAND/NOR Logic Gate T. WAHO (1), A. YAMADA (1), T. OKUYAMA (1), V. KHORENKO, Q.T. DO, W. PROST (1) Dept. of Electrical and Electronics Eng., Sophia University, 7-1 Kioicho, Chiyoda-ku, Tokyo, Japan Int. Symp. on Circuits and Systems 2007 (ISCAS), New Orleans, USA, 27.05.2007 - 30.05.2007

3. Herstellung von pn-Übergängen in Nanodrähten I. REGOLIN, C. GUTSCHE, Q.T. DO, W. PROST, F.-J. TEGUDE

Workshop des SFB 445, Nordwalde, Germany, 14.03.2007 - 15.03.2007

4. Kombination von Nanodrahtwachstum mit konventionellem Schichtwachstum F.-J. TEGUDE, I. REGOLIN, C. GUTSCHE, A. LYSOV, W. PROST

DGKK Workshop, Marburg, Germany, 06.12.2007 - 07.12.2007

5. Dotierungsproblematik der GaAs-Nanodrähte A. LYSOV, I. REGOLIN, C. GUTSCHE, K. BLEKKER, W. PROST, F.-J. TEGUDE

DGKK Workshop, Marburg, Germany, 06.12.2007 - 07.12.2007

6. Fabrication and electrical characterization of III-V semiconductor nanodiode A. LYSOV, I. REGOLIN, C. GUTSCHE, K. BLEKKER, W. PROST, F.-J. TEGUDE

Schwerpunktprogrammtreffen (SPP), Norderney, Germany, 20.08.2007 - 24.08.2007

7. III-V Semiconductor Nanowires: Preparation and Perfomance Issues F.-J. TEGUDE (1) (1) INVITED The second Int. Conf. on One-Dimensional Nanomaterials 2007 (ICON), Malmö, Sweden, 26.09.2007 - 29.09.2007

8. Large-Signal Analysis and AC Modelling of Sub Micron Resonant Tunneling Diodes A. MATISS, A. POLOCZEK, W. BROCKERHOFF, W. PROST, F.-J. TEGUDE

Europ. Microwave Week / Workshops and Short Courses (EuMW), München, Germany, 08.10.2007 - 12.10.2007

9. Ion Implanted GaAs Nanowire Pn-junctions C. GUTSCHE, W. PROST, F.-J. TEGUDE, D. STICHTENOTH (1), C. RONNING (1) (1) II. Institute of Physics, University of Goettingen, Goettingen, Germany MRS Fall Meeting - Novel Assembly Concepts and Device Integration, Boston, MA, USA, 26.11.2007 - 30.11.2007

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10. High-Speed Monostable-Bistable Transition Logic Element Gates with Optical Inputs at 1.3µm/1.55µm

W. PROST, A. POLOCZEK, A. MATISS, J. DRIESEN, F.-J. TEGUDE

XXII Conf. on Design of Circuits and Integrated Systems 2007 (DCIS), Sevilla, Spain, 21.11.2007 - 23.11.2007

11. Sub-Nanosecond Pulse Generation using Resonant Tunneling Diodes for Imulse Radio A. MATISS, A. POLOCZEK, A. STÖHR (1), W. BROCKERHOFF, W. PROST, F.-J. TEGUDE (1) Department of Optoelectronics, University of Duisburg-Essen 2007 IEEE Int. Conf. on Ultra-WideBand (ICUWB), Singapore, Singapore, 24.09.2007 - 26.09.2007

12. Investigation of the Conductance of Silicon Nanowire Biosensors Using the 2D Drift-diffusion Model

S. DAMODARAN (1), S. VADIVELMURUGAN (1), Q.T. DO, C. HEITZINGER (1), G. KLIMECK (1) (1) School of Electrical and Computer Engineering, Purdue University Nanotechnology Conference and Trade Show (Nanotech), Santa Clara, USA, 20.05.2007 - 24.05.2007

13. High-speed picosecond pulse response GaNAsSb p-i-n photodetectors grown by rf plasma-assisted nitrogen molecular beam epitaxy

K.H. TAN (1), S.F. YOON (1), W.K. LOKE (1), S. WICAKSONO (1), K.L. LEW (1), A. STÖHR (2), O. ECIN (2), A. POLOCZEK, D. JÄGER (2) (1) School of Electrical and Electronic Engineering, Nanyang Technological University (2) Dept. of Optoelectronics, University Duisburg-Essen Workshop on Optical Technologies and Broadband Access 2007 (ISIS), Budapest, Hungary, 16.05.2007

14. InP-HEMT-TIA with Differential Optical Input Using Vertical High Topology Pin-Diodes I. NANNEN, A. POLOCZEK, A. MATISS, W. BROCKERHOFF, I. REGOLIN, F.-J. TEGUDE

IEEE Int. Conf. on InP and Related Materials (IPRM), Matsue, Japan, 14.05.2007 - 18.05.2007

15. Single n-InAs Nanowire MIS-Field-Effect Transistor: Experimental and Simulation Results

Q.T. DO, K. BLEKKER, I. REGOLIN, W. PROST, F.-J. TEGUDE

IEEE Int. Conf. on InP and Related Materials (IPRM), Matsue, Japan, 14.05.2007 - 18.05.2007

16. Modeling the Carrier Mobility in Nanowire Channel FET W. PROST, K. BLEKKER, Q.T. DO, I. REGOLIN, S. MÜLLER (1), D. STICHTENOTH (1), K. WEGENER (1), C. RONNING (1), F.-J. TEGUDE (1) University of Göttingen Material Research Society Spring Meeting (MRS), San Francisco, CA, USA, 09.04.2007 - 13.04.2007

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4.6 Publications

1. A Four-Resonant-Tunneling-Diode (4RTD) NAND/NOR Logic Gate T. WAHO (1), A. YAMADA (1), T. OKUYAMA (1), V. KHORENKO, Q.T. DO, W. PROST (1) Dept. of Electrical and Electronics Eng., Sophia University, 7-1 Kioicho, Chiyoda-ku, Tokyo, Japan

Proc. 'Int. Symp. on Circuits and Systems 2007 (ISCAS), New Orleans, USA, 27.05.2007 - 30.05.2007'

2. Growth and characterisation of GaAs/InGaAs/GaAs nanowhiskers on (111)GaAs I. REGOLIN, D. SUDFELD (1), S. LÜTTJOHANN (2), V. KHORENKO, W. PROST, J. KÄSTNER (1), G. DUMPICH (1), C. MEIER (2), A. LORKE (2), F.-J. (1) Dept. of Experimental Physics, University Duisburg-Essen (2) Dept. of Solid State Physics, University Duisburg-Essen

Journal of Crystal Growth, Vol. 298, 2007, pp.607-611

3. GaAs Whiskers Grown by Metal-Organic Vapor-Phase Epitaxy Using Fe Nanoparticles I. REGOLIN, V. KHORENKO, W. PROST, F.-J. TEGUDE, D. SUDFELD (1), J. KÄSTNER (1), G. DUMPICH (1), K. HITZBLECK (2), H. WIGGERS (2) (1) Dept. of Physics, University Duisburg-Essen (2) Inst. of Combusion and Gasdynamics, University Duisburg-Essen

Journal of Applied Physics, Vol. 101, 054318, 2007

4. Large-Signal Analysis and AC Modelling of Sub Micron Resonant Tunneling Diodes A. MATISS, A. POLOCZEK, W. BROCKERHOFF, W. PROST, F.-J. TEGUDE

Proc. 'Europ. Microwave Week / Workshops and Short Courses (EuMW), München, Germany, 08.10.2007 - 12.10.2007'

5. Integrated InGaAs pin-diode on exactly oriented silicon (001) substrate suitable for 10 Gbit/s digital applications

A. POLOCZEK, M. WEISS (1), S. FEDDERWITZ (1), A. STÖHR (1), W. PROST, I. JÄGER (1), F.-J. TEGUDE

(1) Dept. of Optoelectronics, University Duisburg Proc. '20th Annual Meeting of the IEEE Lasers and Electro-Optics Society (LEOS), Lake Buena Fista, Fl, USA, 21.10.2007 - 25.10.2007'

6. High-Speed Monostable-Bistable Transition Logic Element Gates with Optical Inputs at 1.3µm/1.55µm

W. PROST, A. POLOCZEK, A. MATISS, J. DRIESEN, F.-J. TEGUDE

Proc. 'XXII Conf. on Design of Circuits and Integrated Systems 2007 (DCIS), Sevilla, Spain, 21.11.2007 - 23.11.2007'

7. Sub-Nanosecond Pulse Generation using Resonant Tunneling Diodes for Imulse Radio A. MATISS, A. POLOCZEK, A. STÖHR (1), W. BROCKERHOFF, W. PROST, F.-J. TEGUDE (1) Department of Optoelectronics, University of Duisburg-Essen

Proc. '2007 IEEE Int. Conf. on Ultra-WideBand (ICUWB), Singapore, Singapore, 24.09.2007 - 26.09.2007'

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76 Annual Report 2007 - Solid-State Electronics Department

8. High Transconductance MISFET With a Single InAs Nanowire Channel Q.T. DO, K. BLEKKER, I. REGOLIN, W. PROST, F.-J. TEGUDE

IEEE Electron Device Letters, Vol. 28, No. 8, pp.682-684

9. High performance III/V RTD and PIN diode on a silicon (001) substrate W. PROST, V. KHORENKO (1), A.C. MOFOR (2), S. NEUMANN, A. POLOCZEK, A. MATISS, A. BAKIN (2), A. SCHLACHETZKI (2), F.-J. TEGUDE (1) AZUR SPACE Solar Power GmbH, Heilbronn (2) Institute for Semiconductor Technology, Technical University Braunschweig

Applied Physics A, Vol. 87, No. 3, pp.539-544

10. Investigation of the Conductance of Silicon Nanowire Biosensors Using the 2D Drift-diffusion Model

S. DAMODARAN (1), S. VADIVELMURUGAN (1), Q.T. DO, C. HEITZINGER (1), G. KLIMECK (1) (1) School of Electrical and Computer Engineering, Purdue University

Proc. 'Nanotechnology Conference and Trade Show (Nanotech), Santa Clara, USA, 20.05.2007 - 24.05.2007', pp.542-544, Volume 2

11. High-speed picosecond pulse response GaNAsSb p-i-n photodetectors grown by rf plasma-assisted nitrogen molecular beam epitaxy

K.H. TAN (1), S.F. YOON (1), W.K. LOKE (1), S. WICAKSONO (1), K.L. LEW (1), A. STÖHR (2), O. ECIN (2), A. POLOCZEK, D. JÄGER (2) (1) School of Electrical and Electronic Engineering, Nanyang Technological University (2) Dept. of Optoelectronics, University Duisburg-Essen

Proc. 'Workshop on Optical Technologies and Broadband Access 2007 (ISIS), Budapest, Hungary, 16.05.2007'

12. InP-HEMT-TIA with Differential Optical Input Using Vertical High Topology Pin-Diodes I. NANNEN, A. POLOCZEK, A. MATISS, W. BROCKERHOFF, I. REGOLIN, F.-J. TEGUDE

Proc. 'IEEE Int. Conf. on InP and Related Materials (IPRM), Matsue, Japan, 14.05.2007 - 18.05.2007', pp.107 - 109

13. Single n-InAs Nanowire MIS-Field-Effect Transistor: Experimental and Simulation Results

Q.T. DO, K. BLEKKER, I. REGOLIN, W. PROST, F.-J. TEGUDE

Proc. 'IEEE Int. Conf. on InP and Related Materials (IPRM), Matsue, Japan, 14.05.2007 - 18.05.2007', pp.392-395

14. High-speed picosecond pulse response GaNAsSb p-i-n photodetectors grown by rf plasma-assisted nitrogen molecular beam epitaxy

K.H. TAN (1), S.F. YOON (1), W.K. LOKE (1), S. WICAKSONO (1), K.L. LEW (1), A. STÖHR (2), O. ECIN (2), A. POLOCZEK (2), A. MALCOCI (2), D. JÄGER (2) (1) School of Electrical and Electronic Engineering, Nanyang Technological University (2) Dept. of Optoelectronics, University Duisburg-Essen

Appl. Physics Letters, Vol. 90, pp.183515

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Annual Report 2007 - Solid-State Electronics Department 77

15. Modeling the Carrier Mobility in Nanowire Channel FET W. PROST, K. BLEKKER, Q.T. DO, I. REGOLIN, S. MÜLLER (1), D. STICHTENOTH (1), K. WEGENER (1), C. RONNING (1), F.-J. TEGUDE (1) University of Göttingen

Proc. 'Material Research Society Spring Meeting (MRS), San Francisco, CA, USA, 09.04.2007 - 13.04.2007', Mat. Res. Soc. Symp. Proc. Vol. 1017E, 2007

16. Sequential Mechanism of Electron Transport in the Resonant Tunneling Diode with Thick Barriers

N.V. ALKEEV (1), S.V. AVERIN (1), A A. DOROFEEV (2), P. VELLING, E. KHORENKO, W. PROST, F.-J. TEGUDE (1) Institute of Radio Engineering and Electronics, Russian Academy of Sciences (Fryazino Branch) Moccow (2) Pulsar Research Institute, Moscow

Semiconductors, Vol. 41, No. 2, pp.227-231

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78 Annual Report 2007 - Solid-State Electronics Department

4.7 Research Projects

• Nano Particles from the Gas Phase Sonderforschungsbereich 445 (SFB 445), supported by Deutsche Forschungsgemeinschaft (DFG)

together with other departments at the University Duisburg-Essen

• Key components for synchronous optical qudrature phase shift keying transmission (synQPSK)

supported by European Union (EU)) together with

- University of Paderborn, Germany - CeLight Israel Ltd, Israel - PHOTLINE Technologies SA, France

• Nano Wires and Nano Tubes supported by Deutsche Forschungsgemeinschaft (DFG)

• RTD/HBT-Kombinationsbauelemente für Oszillatoranwendungen für die Satellitenkommu-nikation im Ku- und Ka-Band supported by German Aerospace Center (DLR)

• Optoelektronische Digitalschaltungen auf der Basis von Resonanztunneldioden und Photo-dioden den-Arrays supported by Deutsche Forschungsgemeinschaft (DFG)

• Development of RTD and HFET Circuit Model cooperation with Instituo de Microelectronica de Sevilla, Spain

• Development of PIN-Photo Detector Arrays

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Annual Report 2007 - Solid-State Electronics Department 79

4.8 Other Activities: Schueler-Ingenieur-Akademie

I. Nannen, W. Brockerhoff

Introduction The very small number of pupils who actually decide to start an engineering study becomes an increasing problem for the national economics. To increase the number of pupils interested in technical subjects the Schueler-Ingenieur-Akademie (SIA) was founded supported by the German Telekom Foundation. 15 pupils from the Max-Planck Gymnasium, the Franz-Haniel Gymnasium and the Steinbart Gymnasium at Duisburg could get an overview about engineering activities. They had the chance to join and work at university and companies as well once a week for two years.

The Task During the first part of the project the participants joined the solid-state electronics department. The pupils were confronted with the task to realize a clock comparable to that at the rhine tower in Duesseldorf. The clock at the rhine tower, built 1979-1981, is the largest decimal clock in the world and includes 39 LEDs showing the hours, minutes and seconds separately encoded corresponding to the decimal system. Each section is separated by LEDs of another color.

Fig. 1 Schematic of rhine tower clock showing 15:37:19

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80 Annual Report 2007 - Solid-State Electronics Department

The DCF77-signal The displayed time is derived from a DCF77-signal transmitted from Mainflingen in Germany. The encoded information, transmitted within one minute is shown in fig. 2.

Fig. 2 Code table of the DCF77-signal

The first steps To train the skills the project started with the fabrication of simple electronic circuits like a astable multivibrator. Paralell to the practical exercises they visited various laboratories within the department to become acquainted with research activities like the atomic force microscopy, the e-beam technology and various measurement techniques.

Fig. 3 Simple flow chart for the clock

During the next part the participants fabricated the circuits including layout, etching and assembly of the boards. The received DCF77-signal is decoded by an µ-processor (PIC16F628a). Because there are not enough ports to supply all LEDs and to save power a 8x8 display driver is used. A simple parallel communication standard is used for sending the data from the µ-processor to the display driver.

At the end of this phase each group could demonstrate the functionality of their decimal clock.

receive DCF-

signal

decode DCF-signal with µ-

processor Communicate

with multiplexer

Display time with LEDs

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Annual Report 2007 - Solid-State Electronics Department 81

Fig.4 Clock showing the 28th of december 2007 (5th day of the week) at 15:57:59

Fig. 5 Participants of the first "Schueler-Ingenieur-Akademie" from the Steinbart Gymnasium, Franz-Haniel Gymnasium and Max-Planck Gmynasium at Duisburg

hours minutes seconds

day month year working day

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82 Annual Report 2007 - Solid-State Electronics Department

Guide to the Solid-State Electronics Department (HLT)

B M

Hbf

Mülheimerstr.Mülheimerstr.

Landfermannstr.

Königstr.

Neu

dorf e

r Str.

Komm

anda

nten

str.

Koloniestr.

Bism

arck

str.

Ster

nbus

chwe

g (B8

)

Ster

nbus

chweg

(B8)

Sch

wei

zer S

tr. (B

8)

Mozart

str.

Loth

arst

r.

Loth

arst

r,Finkenstr.

Bürgerstr.

Kammerstr.

Zoo

Abfahrt (exit)Duisburg-Kaiserberg

Abfahrt (exit)Duisburg-Wedau

Autobahnkreuz Duisburg-Mitte

A59 Wesel A2/A3Hannover/Emmerich

A40

A3

Köln

A59Düsseldorf

A40Krefeld/ Moers

Rathaus

Düs

seld

orfe

r Str.

Düs

seld

orfe

r Str.

Düs

seld

orfe

r Str.

(B8)

Sportpark Wedau

N

*) ZHO: Zentrum für Halbleitertechnik und Optoelektronik(Center for solid-state electronics and optoelectronics)

LLo

thar

str.

(Haupteingang)main entrance

HighwayLT

ZHO*)

Travel by car: The Solid-State Electronics Department (HLT) at the ZHO (Zentrum fuer Halbleitertechnik und Optoelektronik) can be reached by car via various highways: A3 from the South, A40 from the Netherlands and the East, A2/A3 from the North. Exit: Duisburg-Kaiserberg or Duisburg-Wedau (see map).

Travel by train: The main station (Hauptbahnhof (Hbf)) is 25 min (walk) away from the Solid-State Electronics Department (HLT) and the ZHO (see map). Take the bus 933, 936 or 924 to "Universität/Städtische Kliniken" and leave it at "Universität (Uni-Nord)" or take the tram 901 to "Mülheim" and leave it at "Universität".

Travel by plane: After landing at Duesseldorf Airport (the next airport to Duisburg) take the city-train (S-Bahn) S1 from Duesseldorf to Duisburg main station (Hauptbahnhof (Hbf)). For further informations see: "Travel by train":