architecture of 8085 processor

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    8085

    M icroprocessor

    Architecture

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    The 8085 and I ts Busses

    The 8085 is an8-bit general purposemicroprocessor that can

    address64K Byte of memory.

    I t has40 pinsand uses +5V for power. I t can run at amaximum

    frequency of 3 MHz. The pins on the chip can be grouped into 6 groups:

    AddressBus.

    DataBus.

    Control and StatusSignals.

    Power supplyandfrequency.

    Externally Ini tiated Signals.

    Ser ial I /O ports.

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    The Address and Data Busses

    The address bus has 8 signal l inesA8A15which are

    unidirectional.

    The other 8 address bits aremultiplexed(time shared)with the 8

    data bits. So, the bitsAD0AD7arebi-directionaland serve asA0

    A7andD0D7at the same time.

    Dur ing the executi on of the instruction, these l ines carry

    the address bits dur ing the early part, then dur ing the

    late parts of the executi on, they carry the 8 data bits.

    I n order to separate the address from the data, we can use a

    latch to save the value before the function of the bits

    changes.

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    The Control and Status Signals

    There are4maincontrolandstatussignals. These are:

    ALE:Address Latch Enable. This signal is a pulse that

    become1when theAD0AD7lines have anaddresson

    them. I t becomes 0 after that. Thi s signal can be used toenable a latch to save the address bits from the AD lines.

    RD:Read. Active low.

    WR:Write. Active low.

    IO/M: This signal specif ies whether the operation is a

    memory operation(IO/M=0) or anI /O operation

    (IO/M=1).

    S1 and S0: Status signals to specify thekind of

    operationbeing performed .Usual ly un-used in smal l

    systems.

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    Frequency Control Signals

    There are3important pins in the frequency control group.

    X0andX1are theinputsfrom thecrystalor clock

    generating circuit.

    The frequency is internall y divided by 2.

    So, to run the microprocessor at 3 MHz, a clock

    running at 6 MHz should be connected to the X0

    and X1 pins.

    CLK(OUT): An output clock pin to dr ive the clock of the

    rest of the system.

    We will discuss the rest of the control signals as we get to them.

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    M icroprocessor Communication and Bus Timing

    To understand how the microprocessor operates and uses these

    different signals, we should study the process of communication

    between the microprocessor and memory dur ing a memory read

    or wr ite operation. Lets look at timing and the data flow of aninstruction fetch

    operation. (Example 3.1)

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    Demultiplexing AD7-AD0

    From the above description, it becomes obvious that

    theAD7AD0lines are serving adual purposeand

    that they need to be demultiplexed to get al l the

    information.

    Thehigh order bitsof the address remain on the busforthree clock per iods. However, thelow order bits

    remain foronly one clock per iodand they would be

    lost if they are not saved externally. Also, notice that

    thelow order bitsof the addressdisappearwhen they

    are needed most.

    To make sure we have the enti re address for the ful l

    three clock cycles, we wil l use anexternal latchto save

    the value of AD7AD0 when i t is carrying the address

    bits. We use theALEsignal to enable this latch.

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    Demultiplexing AD7-AD0

    Given that ALE operates as a pulse dur ing T1,

    we wil l be able to latch the address. Thenwhen ALE goes low, the address is saved and

    the AD7AD0 lines can be used for their

    purpose as the bi-directional data lines.

    A15-A8

    LatchAD7-AD0

    D7

    - D0

    A7

    - A0

    8085

    ALE

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    Cycles and States

    From the above discussion, we can define terms that wil l becomehandy later on:

    T- State: One subdivision of an operation. A T-state lasts for

    one clock per iod.

    An instructions execution length is usually measured in

    a number of T-states. (clock cycles). Machine Cycle: The time requi red to complete one operation

    of accessing memory, I /O, or acknowledging an external

    request.

    This cycle may consist of 3 to 6 T-states.

    I nstruction Cycle: The time requi red to complete theexecution of an instruction.

    I n the 8085, an instruction cycle may consist of 1 to 6

    machine cycles.

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    Generating Control Signals

    The 8085 generates a single RD signal . However, the signal

    needs to be used with both memory and I /O. So, it must be

    combined with the IO/M signal to generate different control

    signals for the memory and I /O. Keeping in mind the operation of the IO/M signal we can

    use the foll owing circui try to generate the right set of

    signals:

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    The ALU

    I n addition to the ar ithmetic & logic circui ts, the ALU

    includes the accumulator, which is part of every

    ar ithmetic & logic operation.

    Also, the ALU includes a temporary register used for

    holding data temporari ly dur ing the execution of the

    operation. This temporary register is not accessible by

    the programmer.

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    The F lags register

    There is also the fl ags register whose bits are aff ected by the ari thmetic &

    logic operations. S-sign f lag

    The sign f lag is set i f bit D7 of the accumulator is set after an

    ari thmetic or logic operation.

    Z-zero fl ag

    Set if the resul t of the ALU operation is 0. Otherwise is reset. This

    flag is affected by operations on the accumulator as wel l as otherregisters. (DCR B).

    AC-Auxiliary Carry

    This flag is set when a car ry is generated from bi t D3 and passed

    to D4 . This fl ag is used only internal ly for BCD operations.

    (Section 10.5 describes BCD addit ion i ncluding the DAA

    instruction). P-Pari ty fl ag

    After an ALU operation if the result has an even # of 1s the p-

    f lag is set. Otherwise i t is cleared. So, the fl ag can be used to

    indicate even par ity.

    CY-carry flag

    Discussed earl ier

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