Architecture & Organization

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    ARCHITECTURE

    & ORGANIZATION

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    COMPUT

    ER

    INTER-CONNECTI

    ON

    I/O

    MEMORY

    CPU

    TOP LEVEL STRUCTURE

    SUBSYSTEM

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    FATHER OF THE CLASSICAL COMPUTER

    VON NEUMANN

    ARCHITECTURE

    BOTH DATA INSTRUCTION ARE STOREDIN READ/WRITE MEMORY

    THE CONTENTS OF READ/WRITE

    MEMORY ARE ACCESSED BY LOCATION.

    THE INSTRUCTIONS ARE ACCESS &EXECUTED SEQUENTIALLY.

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    CP

    U

    R/W

    MEMORY

    I/O

    SYSTEM BUS

    CPU, MEMORY & I/O ARE INTERCONNECTEDWITH THE HELP OF THE SYSTE BUS THROUGH WHICH

    R/W MEMORY & I/O ARE INTERFACE. CPU is responsible for sequentially gettinginstructions & data from memory. Then storedtemporarily inside the cpu, then execute one of the

    other, or the DATA will return back to memory. THIS IS VON NEUMANN ARCHITECTURE.

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    MICROPROCESSOR ARCHITECTURE

    REGISTERS

    A . L . U

    .TIMING

    &CONTROL

    UNIT

    INTE

    RFACE

    MEMORY

    I / O

    CPU-ON-A-CHIP

    P, MEMORY & I / O are

    Interface through

    System Bus

    C P U

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    REGISTERS - THE INSTRUCTIONS & DATA ARESTORED TEMPORARY ON CPU.

    A . L . U . - RESPONSIBLE FOR PROCESSING THEDATA, the arithmetic & logical operations.

    TIMING AND CONTROL UNIT

    - RESPONSIBLE FOR COORDINATION & CONTROTHE ACTIVITY WITH IN THE CPU & ALSO CONTROL THEAREAS OF THE MEMORY & I / 0 DEVICES.

    INTERFACE - THIS SECTION HAS A SET OF PINSTHROUGH WHICH CONNECTED ON

    MEMORY & I / O DEVICE ON SYSTEMBUS.

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    Bus Structure

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    Address Bus

    The address bus is a group of 16 lines

    generally identified as A0 to A15.

    The address bus is unidirectional: bits flowin one direction-from the MPU to peripheral

    devices.

    The MPU uses the address bus to perform

    the first function: identifying a peripheral or a

    memory location.

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    DATA Bus

    The data bus is a group of eight lines used for data

    flow. These lines are bi-directional - data flow in both

    directions between the MPU and memory and peripheraldevices. The MPU uses the data bus to perform the second

    function: transferring binary information.

    The eight data lines enable the MPU to manipulate8-bit data ranging from 00 to FF (288 = 256 numbers).

    The largest number that can appear on the data bus is

    11111111.

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    Control Bus

    The control bus carries synchronization

    signals and providing timing signals.

    The MPU generates specific control signals

    for every operation it performs. These signals areused to identify a device type with which the MPU

    wants to communicate.

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    REGISTER SECTION

    Have a six general-purpose registers to store 8-bit data

    during program execution. These registers are identified as B, C, D, E, H, and L. They can be combined as register pairs-BC, DE, and HL-to

    perform some 16-bit operations.

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    GENERAL PURPOSE - USE TO HOLDDATA & ADDRESSES.

    NUMBER OF BITS

    SIZE EXECUTION TIME EASE OF PROGRAMMING

    2 TYPES

    GENERAL PURPOSE SPECIAL PURPOSE

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    SPECIAL PURPOSE - DESIGN FOR

    SPECIFIC PURPOSES.

    ACCUMULATOR PROGRAM COUNTER (PC) FLAGS (FLIP-FLOPS) STACK POINTER

    USER ACCESSIBLE OR NOTACCESSIBLE

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    FLAGS

    The ALU includes five flip-flops that are set

    or reset according to the result of an operation.

    The microprocessor uses the flags fortesting the data conditions.

    They are Zero (Z), Carry (CY), Sign (S),

    Parity (P), and Auxiliary Carry (AC) flags. The

    most commonly used flags are Sign, Zero, and

    Carry.

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    The bit position for the flags in flag register

    Program StatusWord(PSW)

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    SIGN FLAG (S)

    After execution of any arithmetic and logicaloperation, if D7 of the result is 1, the sign flag is

    set. Otherwise it is reset.

    D7 is reserved for indicating the sign; the

    remaining is the magnitude of number.

    If D7 is 1, the number will be viewed as

    negative number. If D7 is 0, the number will be

    viewed as positive number.

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    ZERO FLAG (Z)

    If the result of arithmetic and logical

    operation is zero, then zero flag is set otherwise itis reset.

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    AUXILIARY CARRY FLAG (AC)

    If D3 generates any carry when doing any

    arithmetic and logical operation, this flag is set.Otherwise it is reset.

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    PARITY FLAG (P)

    If the result of arithmetic and logical

    operation contains even number of 1's then thisflag will be set and if it is odd number of 1's it will

    be reset.

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    CARRY FLAG (CY)

    If any arithmetic and logical operation result

    any carry then carry flag is set otherwise it isreset.

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    Program Counter(PC)

    This 16-bit register sequencing the execution of

    instructions.

    It is a memory pointer. Memory locations have 16-bit

    addresses, and that is why this is a 16-bit register.

    The function of the program counter is to point to the

    memory address of the next instruction to be executed.

    When an opcode is being fetched, the program counter is

    incremented by one to point to the next memory location.

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    STACK Pointer (Sp)

    The stack pointer is also a 16-bit register used

    as a memory pointer.

    It points to a memory location in R/W memory,

    called the stack.

    The beginning of the stack is defined by

    loading a 16-bit address in the stack pointer

    (register).

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    USER ACCESSIBLE

    all general and special purposes.

    USER NOT ACCESSIBLE

    all are temporary hold the (addresses, data, information

    and temporary registers) before it is decoded & executed by

    microprocessor.

    Memory Address Register (MAR) Memory Data Register (MDR) Instruction Register (IR)

    Temporary Register (TR)

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    Arithmetic Operations

    Addition Subtraction Increment Decrement

    A . L . U. Section

    execute immediately for 8-bit data. need to write a program & cannot be executing

    immediately the instructions for 16-bit & 32-bit data.

    Multiplication Division Decimal Adjust

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    Logical Operations

    AND OR

    EX-OR NOT CLEAR COMPARE

    SHIFT / ROTATE

    ON MODERN MPU, the logical operation are even

    more operated.

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    INTERFACE SECTION

    set of PINS.

    Memory & I / O Control Lines

    READ / WRITE INPUT, OUTPUT / MEMORY READY / WAIT

    Address Latch Enable ( ALE ) STATUS LINES ADDRESS LINES DATA LINES

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    CPU and BUS control lines

    RESET INTERRUPTS BUS REQUEST / BUS GRANT LINES

    UTILITY LINES

    Power Supply

    Clock I / O Lines Vcc Ground

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    TIMING & CONTROL UNIT SECTION

    COORDINATE & CONTROL THE SUBSYSTEMSWITHIN THE CPU AND ALSO OUTSIDE THE CPU.

    also called HEART OF THE CPU

    Control Unit

    HARDWIRED

    MICROPROGRAMMED

    ANY DESIGN OF THIS CONTROL UNIT, THE

    FUNCTION ARE THE SAME.

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    CONTROL

    UNIT

    INPUT OUTPUT

    SIGNAL

    CLOCK

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    Clock

    SINGLE-PHASE CLOCKHIGH

    LOW

    HIGH-TO-LOW

    CONDITION

    LOW-TO-HIGH

    CONDITION

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    1

    2

    HI

    LOW

    HI

    LOW

    TWO-PHASE CLOCK

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    THREE CONTROL SIGNALS

    ADDRESS LATCH ENABLE(ALE)

    - used for provide control signal to synchronize

    the components of microprocessor and timing for instruction

    to perform the operation.

    READ (Active low) and WRITE (Active low)

    - used to indicate whether the operation isreading the data from memory or writing the data into memory

    respectively.

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    Input Output/Memory(Active low), S0 and S1

    - used to indicate whether the operation isbelongs to the memory or peripherals.

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    Interrupt Control Unit

    It receives hardware interrupt signals and sends

    an acknowledgement for receiving the interrupt signal.