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Arm® Cortex®-M0+ 32-bit MCU, 128 KB Flash, 36 KB RAM, 4x ... · This document provides information on STM32G070CB/KB/RB microcontrollers, such as description, functional overview,

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  • This is information on a product in full production.

    November 2018 DS12766 Rev 1 1/96

    STM32G070CB/KB/RB

    Arm® Cortex®-M0+ 32-bit MCU, 128 KB Flash, 36 KB RAM, 4x USART, timers, ADC, comm. I/Fs, 2.0-3.6V

    Datasheet - production data

    Features• Core: Arm® 32-bit Cortex®-M0+ CPU,

    frequency up to 64 MHz• -40°C to 85°C operating temperature• Memories

    – 128 Kbytes of Flash memory– 36 Kbytes of SRAM (32 Kbytes with HW

    parity check)• CRC calculation unit• Reset and power management

    – Voltage range: 2.0 V to 3.6 V– Power-on/Power-down reset (POR/PDR)– Low-power modes:

    Sleep, Stop, Standby– VBAT supply for RTC and backup registers

    • Clock management– 4 to 48 MHz crystal oscillator– 32 kHz crystal oscillator with calibration– Internal 16 MHz RC with PLL option– Internal 32 kHz RC oscillator (±5 %)

    • Up to 59 fast I/Os– All mappable on external interrupt vectors– Multiple 5 V-tolerant I/Os

    • 7-channel DMA controller with flexible mapping• 12-bit, 0.4 µs ADC (up to 16 ext. channels)

    – Up to 16-bit with hardware oversampling– Conversion range: 0 to 3.6V

    • 11 timers: 16-bit for advanced motor control, five 16-bit general-purpose, two basic 16-bit, two watchdogs, SysTick timer

    • Calendar RTC with alarm and periodic wakeup from Stop/Standby

    • Communication interfaces– Two I2C-bus interfaces supporting Fast-

    mode Plus (1 Mbit/s) with extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode

    – Four USARTs with master/slave synchronous SPI; two supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature

    – Two SPIs (32 Mbit/s) with 4- to 16-bit programmable bitframe, one multiplexed with I2S interface

    • Development support: serial wire debug (SWD)• All packages ECOPACK®2 compliant

    LQFP64 10 × 10 mmLQFP48 7 × 7 mmLQFP32 7 × 7 mm

    www.st.com

    http://www.st.com

  • Contents STM32G070CB/KB/RB

    2/96 DS12766 Rev 1

    Contents

    1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

    2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

    3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.1 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

    3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

    3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

    3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

    3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

    3.6 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14

    3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

    3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

    3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

    3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

    3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

    3.7.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

    3.8 Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

    3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

    3.10 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 19

    3.11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 19

    3.12 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.12.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 20

    3.12.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 21

    3.13 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.13.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

    3.13.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 22

    3.13.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

    3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

    3.14.2 General-purpose timers (TIM3, TIM14, TIM15, TIM16, TIM17) . . . . . . . 24

    3.14.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

  • DS12766 Rev 1 3/96

    STM32G070CB/KB/RB Contents

    4

    3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

    3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

    3.14.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

    3.15 Real-time clock (RTC), tamper (TAMP) and backup registers . . . . . . . . . 25

    3.16 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

    3.17 Universal synchronous/asynchronous receiver transmitter (USART) . . . 27

    3.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

    3.19 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.19.1 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

    4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 29

    5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

    5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

    5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

    5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

    5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

    5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

    5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

    5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

    5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

    5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

    5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43

    5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 43

    5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

    5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

    5.3.6 Wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

    5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

    5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

    5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

    5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

    5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

    5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

    5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

  • Contents STM32G070CB/KB/RB

    4/96 DS12766 Rev 1

    5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

    5.3.15 NRST input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

    5.3.16 Analog switch booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

    5.3.17 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 69

    5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

    5.3.19 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

    5.3.20 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

    5.3.21 Characteristics of communication interfaces . . . . . . . . . . . . . . . . . . . . . 76

    6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

    6.2 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

    6.3 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

    6.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

    7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

    8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

  • DS12766 Rev 1 5/96

    STM32G070CB/KB/RB List of tables

    6

    List of tables

    Table 1. STM32G070CB/KB/RB family device features and peripheral counts . . . . . . . . . . . . . . . . 10Table 2. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 13Table 3. Interconnect of STM32G070CB/KB/RB peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 4. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 5. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 6. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Table 7. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Table 8. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Table 9. SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Table 10. Terms and symbols used in Table 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Table 11. Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Table 12. Port A alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Table 13. Port B alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Table 14. Port C alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table 15. Port D alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Table 16. Port F alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Table 17. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Table 18. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Table 19. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Table 20. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Table 21. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Table 22. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 23. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Table 24. Current consumption in Run and Low-power run modes

    at different die temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Table 25. Typical current consumption in Run and Low-power run modes,

    depending on code executed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Table 26. Current consumption in Sleep and Low-power sleep modes . . . . . . . . . . . . . . . . . . . . . . . 49Table 27. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Table 28. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Table 29. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Table 30. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Table 31. Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Table 32. Low-power mode wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Table 33. Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Table 34. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Table 35. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Table 36. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Table 37. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Table 38. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Table 39. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Table 40. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Table 41. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Table 42. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Table 43. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Table 44. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 45. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 46. Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

  • List of tables STM32G070CB/KB/RB

    6/96 DS12766 Rev 1

    Table 47. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Table 48. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Table 49. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Table 50. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Table 51. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Table 52. Analog switch booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Table 53. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Table 54. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Table 55. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Table 56. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Table 57. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Table 58. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Table 59. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Table 60. IWDG min/max timeout period at 32 kHz LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Table 61. Minimum I2CCLK frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Table 62. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Table 63. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Table 64. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Table 65. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Table 66. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Table 67. LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Table 68. LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Table 69. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 70. STM32G070CB/KB/RB ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Table 71. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

  • DS12766 Rev 1 7/96

    STM32G070CB/KB/RB List of figures

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    List of figures

    Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 3. STM32G070RxT LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 4. STM32G070CxT LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 5. STM32G070KxT LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Figure 6. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Figure 7. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Figure 8. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure 9. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure 10. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Figure 11. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 12. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 13. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Figure 14. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Figure 15. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Figure 16. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Figure 17. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Figure 18. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Figure 19. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Figure 20. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Figure 21. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Figure 22. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Figure 23. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Figure 24. I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Figure 25. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Figure 26. Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Figure 27. LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Figure 28. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Figure 29. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Figure 30. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Figure 31. LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Figure 32. Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Figure 33. LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

  • Introduction STM32G070CB/KB/RB

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    1 Introduction

    This document provides information on STM32G070CB/KB/RB microcontrollers, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging, and ordering codes.

    Information on memory mapping and control registers is object of reference manual.

    Information on Arm®(a) Cortex®-M0+ core is available from the www.arm.com website.

    a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

  • DS12766 Rev 1 9/96

    STM32G070CB/KB/RB Description

    28

    2 Description

    The STM32G070CB/KB/RB mainstream microcontrollers are based on high-performance Arm® Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains and ready for the Internet of Things (IoT) solutions.

    The devices incorporate a memory protection unit (MPU), high-speed embedded memories (128 Kbytes of Flash program memory and 36 Kbytes of SRAM), DMA and an extensive range of system functions, enhanced I/Os and peripherals. The devices offer standard communication interfaces (two I2Cs, two SPIs / one I2S, and four USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels, a low-power RTC, an advanced control PWM timer, five general-purpose 16-bit timers, two basic two watchdog timers, and a SysTick timer.

    The devices operate within ambient temperatures from -40 to 85°C. They can operate with supply voltages from 2.0 V to 3.6 V. Optimized dynamic consumption combined with a comprehensive set of power-saving modes allows the design of low-power applications.

    VBAT direct battery input allows keeping RTC and backup registers powered.

    The devices come in packages with 32 to 64 pins.

  • Description STM32G070CB/KB/RB

    10/96 DS12766 Rev 1

    Table 1. STM32G070CB/KB/RB family device features and peripheral counts Peripheral STM32G070KB STM32G070CB STM32G070RB

    Flash memory (Kbyte) 128

    SRAM (Kbyte) 32 (with parity) or 36 (without parity)

    Tim

    ers

    Advanced control 1 (16-bit)

    General-purpose 5 (16-bit)

    Basic 2 (16-bit)

    SysTick 1

    Watchdog 2

    Com

    m.

    inte

    rface

    s

    SPI [I2S](1) 2 [1]

    I2C 2

    USART 4

    RTC Yes

    RNG(2) No

    AES(2) No

    Tamper pins 2

    GPIOs 29 43 59

    Wakeup pins 4 4 5

    12-bit ADC channels 11 ext.+ 2 int.14 ext.+ 3 int.

    16 ext.+ 3 int.

    Max. CPU frequency 64 MHz

    Operating voltage 2.0 - 3.6 V

    Operating temperatureAmbient: -40 - 85°C

    Junction: -40 - 105°C

    Number of pins 32 48 64

    1. The numbers in brackets denote the count of SPI interfaces configurable as I2S interface.

    2. RNG: Random number generator, AES: Advanced Encryption Standard

  • DS12766 Rev 1 11/96

    STM32G070CB/KB/RB Description

    28

    Figure 1. Block diagram

    MSv42183V1

    USART3/4

    USART1/2

    TIMER 16/17

    Power domain of analog blocks : VBAT

    6 channelsBRK, ETR input as AF

    System and peripheral

    clocks

    PA[15:0]

    PB[15:0]

    PC[15:0]

    PF4,3,1,0

    59 AF

    MOSI/SDMISO/MCK

    SCK/CKNSS/WS as AF

    SWCLKSWDIO

    as AF

    16x IN

    OSC_INOSC_OUT

    VBAT

    OSC32_IN OSC32_OUT

    RTC_OUT RTC_REFINRTC_TS

    MOSI, MISO, SCK, NSS,

    as AF

    HSI16

    LSI

    PLLPCLK

    VDD

    IR_OUT as AF1 channel as AF

    1 channel as AF

    4 ch., ETR as AF

    CPUCORTEX-M0+fmax = 64 MHz

    SWD

    NVIC

    EXTI

    SPI1/I2S

    SPI2

    AHB-to-APB

    RCCReset & clock control

    I/F

    XTAL OSC4-48 MHz

    IWDG

    SRAM36 KB

    I/FADC

    RTC, TAMPBackup regs

    I/F

    RC 16 MHz

    RC 32 kHz

    PLL

    deco

    der

    XTAL32 kHz

    Bus

    mat

    rix I/F

    VDD

    2 channels as AF

    RX, TX,CTS, RTS,CK as AF

    RX, TX,CTS, RTS,CK as AF

    TIM6

    TIM7

    Port D

    Port C

    Port B

    Port A

    VDDA

    SUPPLY SUPERVISION

    POWER

    VCORE

    PORReset

    Int

    VDD/VDDAVSS/VSSA

    NRSTPOR/PDR

    Voltageregulator

    USART3 & 4

    USART1 & 2

    TIM16 & 17

    TIM15

    TIM14

    TIM3

    TIM1

    GPIOs

    IOPORT

    HSE

    PLLRCLK

    LSE

    LSE

    T sensor

    TAMP_IN

    AP

    B

    AP

    B

    AH

    B

    CRC

    VREF+

    SCL, SDA as AF

    SCL, SDA, SMBA,SMBUS as AF I2C1

    I2C2DBGMCU

    WWDG

    PWRCTRL

    SYSCFG

    DMA

    DMAMUX

    Port F

    PD[9:0]

    VDDA VDDIO1

    Low-voltage detector

    VDD

    Parity

    Flash memory 128 KB

    VDDIO1

  • Functional overview STM32G070CB/KB/RB

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    3 Functional overview

    3.1 Arm® Cortex®-M0+ core with MPUThe Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:• a simple architecture, easy to learn and program• ultra-low power, energy-efficient operation• excellent code density• deterministic, high-performance interrupt handling• upward compatibility with Cortex-M processor family• platform security robustness, with integrated Memory Protection Unit (MPU).

    The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier.

    The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.

    Owing to embedded Arm core, the STM32G070CB/KB/RB devices are compatible with Arm tools and software.

    The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC) described in Section 3.12.1.

    3.2 Memory protection unitThe memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task.

    The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

    The MPU is optional and can be bypassed for applications that do not need it.

    3.3 Embedded Flash memorySTM32G070CB/KB/RB devices feature 128 Kbytes of embedded Flash memory available for storing code and data.

  • DS12766 Rev 1 13/96

    STM32G070CB/KB/RB Functional overview

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    Flexible protections can be configured thanks to option bytes:• Readout protection (RDP) to protect the whole memory. Three levels are available:

    – Level 0: no readout protection– Level 1: memory readout protection: the Flash memory cannot be read from or

    written to if either debug features are connected, boot in RAM or bootloader is selected

    – Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in RAM and bootloader selection are disabled. This selection is irreversible.

    • Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity.

    The whole non-volatile memory embeds the error correction code (ECC) feature supporting:• single error detection and correction• double error detection• readout of the ECC fail address from the ECC register

    3.4 Embedded SRAMSTM32G070CB/KB/RB devices have 32 Kbytes of embedded SRAM with parity. Hardware parity check allows memory data errors to be detected, which contributes to increasing functional safety of applications.

    When the parity protection is not required because the application is not safety-critical, the parity memory bits can be used as additional SRAM, to increase its total size to 36 Kbytes.

    The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

    Table 2. Access status versus readout protection level and execution modes

    Area Protection level

    User execution Debug, boot from RAM or boot from system memory (loader)

    Read Write Erase Read Write Erase

    User memory

    1 Yes Yes Yes No No No

    2 Yes Yes Yes N/A N/A N/A

    System memory

    1 Yes No No Yes No No

    2 Yes No No N/A N/A N/A

    Option bytes

    1 Yes Yes Yes Yes Yes Yes

    2 Yes No No N/A N/A N/A

    Backup registers

    1 Yes Yes N/A(1)

    1. Erased upon RDP change from Level 1 to Level 0.

    No No N/A(1)

    2 Yes Yes N/A N/A N/A N/A

  • Functional overview STM32G070CB/KB/RB

    14/96 DS12766 Rev 1

    3.5 Boot modesAt startup, the boot pin and boot selector option bit are used to select one of the three boot options:• boot from User Flash memory• boot from System memory• boot from embedded SRAM

    The boot pin is shared with a standard GPIO and can be disabled through the boot selector option bit. The boot loader is located in System memory. It manages the Flash memory reprogramming through USART on pins PA9/PA10, PC10/PC11 or PA2/PA3, through I2C-bus on pins PB6/PB7 or PB10/PB11, or through SPI on pins PA4/PA5/PA6/PA7 or PB12/PB13/PB14/PB15.

    3.6 Cyclic redundancy check calculation unit (CRC)The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

    Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location.

    3.7 Power supply management

    3.7.1 Power supply schemesThe STM32G070CB/KB/RB devices require a 2.0 V to 3.6 V operating supply voltage (VDD). Several different power supplies are provided to specific peripherals:• VDD = 2.0 to 3.6 V

    VDD is the external power supply for the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD/VDDA pin.

    • VDDA = 2.0 V to 3.6 VVDDA is the analog power supply for the A/D converter. VDDA voltage level is identical to VDD voltage as it is provided externally through VDD/VDDA pin.

    • VDDIO1 = VDDVDDIO1 is the power supply for the I/Os. VDDIO1 voltage level is identical to VDD voltage as it is provided externally through VDD/VDDA pin.

    • VBAT = 1.55 V to 3.6 VVBAT is the power supply (through a power switch) for RTC, TAMP, low-speed external 32.768 kHz oscillator and backup registers when VDD is not present. VBAT is provided

  • DS12766 Rev 1 15/96

    STM32G070CB/KB/RB Functional overview

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    externally through VBAT pin. When this pin is not available on the package, VBAT bonding pad is internally bonded to the VDD/VDDA pin.

    • VREF+ is the input reference voltage for the ADC. When VDDA < 2 V, VREF+ must be equal to VDDA. When VDDA ≥ 2 V, it must be between 2 V and VDDA. It can be grounded when the ADC are not active.VREF+ is delivered through VREF+ pin. On packages without VREF+ pin, VREF+ is internally connected with VDD.

    • VCORE An embedded linear voltage regulator is used to supply the VCORE internal digital power. VCORE is the power supply for digital peripherals, SRAM and Flash memory. The Flash memory is also supplied with VDD.

    Figure 2. Power supply overview

    3.7.2 Power supply supervisorThe device has an integrated power-on/power-down (POR/PDR) reset active in all power modes and ensuring proper operation upon power-on and power-down. It maintains the device in reset when the supply voltage is below VPOR/PDR threshold, without the need for an external reset circuit.

    3.7.3 Voltage regulatorTwo embedded linear voltage regulators, main regulator (MR) and low-power regulator (LPR), supply most of digital circuitry in the device.

    The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power sleep and Stop modes.

    MSv47920V1

    VDDA domain

    RTC domain

    A/D converter

    Standby circuitry (Wakeup, IWDG)

    Voltage regulator

    Core

    SRAM

    Digitalperipherals

    Low-voltage detector

    LSE crystal 32.768 kHz oscBKP registers

    RCC BDCR registerRTC and TAMP

    I/O ring

    VCORE domainTemp. sensorReset block

    PLL, HSI

    Flash memory

    VDDIO1

    VREF+

    VDD domain

    VCORE

    VSS/VSSA

    VDD/VDDA

    VBAT

    VDDA

    VREF+

    VSSA

    VSS

    VDD

    VDDIO1 domain

  • Functional overview STM32G070CB/KB/RB

    16/96 DS12766 Rev 1

    In Standby mode, both regulators are powered down and their outputs set in high-impedance state, such as to bring their current consumption close to zero.

    3.7.4 Low-power modesBy default, the microcontroller is in Run mode after system or power reset. It is up to the user to select one of the low-power modes described below:

    • Sleep modeIn Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

    • Low-power run modeThis mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

    • Low-power sleep modeThis mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the Low-power run mode.

    • Stop 0 and Stop 1 modesIn Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while retaining the SRAM and register contents. All clocks in the VCORE domain are stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC).Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event. The main regulator remains active in Stop 0 mode while it is turned off in Stop 1 mode.

    • Standby modeThe Standby mode is used to achieve the lowest power consumption, with POR/PDR always active in this mode. The main regulator is switched off to power down VCORE domain. The low-power regulator is switched off. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are also powered down. The RTC can remain active (Standby mode with RTC, Standby mode without RTC).For each I/O, the software can determine whether a pull-up, a pull-down or no resistor shall be applied to that I/O during Standby mode.Upon entering Standby mode, register contents are lost except for registers in the RTC domain and standby circuitry.The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE (CSS on LSE).

  • DS12766 Rev 1 17/96

    STM32G070CB/KB/RB Functional overview

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    3.7.5 Reset mode During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce power consumption. In addition, when the reset source is internal, the built-in pull-up resistor on NRST pin is deactivated.

    3.7.6 VBAT operationThe VBAT power domain, consuming very little energy, includes RTC, and LSE oscillator and backup registers.

    In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for example, an external battery or an external supercapacitor. Two anti-tamper detection pins are available.

    The RTC domain can also be supplied from VDD/VDDA pin.

    By means of a built-in switch, an internal voltage supervisor allows automatic switching of RTC domain powering between VDD and voltage from VBAT pin to ensure that the supply voltage of the RTC domain (VBAT) remains within valid operating conditions. If both voltages are valid, the RTC domain is supplied from VDD/VDDA pin.

    An internal circuit for charging the battery on VBAT pin can be activated if the VDD voltage is within a valid range.

    Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT mode, as in that mode the VDD is not within a valid range.

    3.8 Interconnect of peripheralsSeveral peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

    Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes.

    Table 3. Interconnect of STM32G070CB/KB/RB peripherals

    Interconnect source Interconnect destination Interconnect action Run

    Lo

    w-p

    ower

    run

    Slee

    pLo

    w-p

    ower

    sle

    ep

    Stop

    TIMx

    TIMx Timer synchronization or chaining Y Y -

    ADCx Conversion triggers Y Y -

    DMA Memory-to-memory transfer trigger Y Y -

    ADCx TIM1 Timer triggered by analog watchdog Y Y -

    RTC TIM16 Timer input channel from RTC events Y Y -

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    3.9 Clocks and startupThe clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:• Clock prescaler: to get the best trade-off between speed and current consumption,

    the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

    • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register.

    • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

    • System clock source: three different sources can deliver SYSCLK system clock:– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It

    can supply clock to system PLL. The HSE can also be configured in bypass mode for an external clock.

    – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can supply clock to system PLL.

    – System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or HSI16 clocks.

    • Auxiliary clock source: two ultra-low-power clock sources for the real-time clock (RTC):– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive

    capability modes. The LSE can also be configured in bypass mode for using an external clock.

    – 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to clock an independent watchdog.

    All clocks sources (internal and external) TIM14,16,17

    Clock source used as input channel for RC measurement and trimming Y Y -

    CSSRAM (parity error)

    Flash memory (ECC error)TIM1,15,16,17 Timer break Y Y -

    CPU (hard fault) TIM1,15,16,17 Timer break Y - -

    GPIOTIMx External trigger Y Y -

    ADC Conversion external trigger Y Y -

    Table 3. Interconnect of STM32G070CB/KB/RB peripherals (continued)

    Interconnect source Interconnect destination Interconnect action Run

    Lo

    w-p

    ower

    run

    Slee

    pLo

    w-p

    ower

    sle

    ep

    Stop

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    • Peripheral clock sources: several peripherals (I2S, USARTs, I2Cs, ADC) have their own clock independent of the system clock.

    • Clock security system (CSS): in the event of HSE clock failure, the system clock is automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected and generate an interrupt. The CCS feature can be enabled by software.

    • Clock output: – MCO (microcontroller clock output) provides one of the internal clocks for

    external use by the application– LSCO (low speed clock output) provides LSI or LSE in all low-power modes

    (except in VBAT operation).

    Several prescalers allow the application to configure AHB and APB domain clock frequencies, 64 MHz at maximum.

    3.10 General-purpose inputs/outputs (GPIOs)Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of the GPIO pins are shared with special digital or analog functions.

    Through a specific sequence, this special function configuration of I/Os can be locked, such as to avoid spurious writing to I/O control registers.

    3.11 Direct memory access controller (DMA)Direct memory access (DMA) controller transfers data from a source to a destination, without making it transit through the CPU. DMA transfers are highly efficient; they save CPU resources and facilitate time-critical processing.

    The source and the destination of a DMA transfer can be a peripheral or a memory.

    The DMA transfer source and destination data types can be programmed independently. If different, the DMA controller performs data type conversion and adapts the addressing at the source and at the destination to their respective data types.

    DMA transfer size is the number of DMA transfer cycles to execute, programmable by software. One cycle transfers one data item of selected data type from the DMA transfer source to the DMA transfer destination. The DMA transfer starts at pre-programmed source and destination base addresses. It ends at source and destination addresses that depend on the DMA transfer size, source and destination data types, and on activation of address auto-increment operation.

    The DMA transfer starts upon a request from a peripheral or, in the specific case of memory-to-memory transfer, it starts when enabled by software.

    The DMA controller executes one DMA transfer cycle per DMA transfer request from a peripheral, until the total number of cycles reaches the pre-programmed DMA transfer size. The circular mode of operation allows to repeat the DMA transfer infinitely, without software intervention.

    In the specific case of memory-to-memory transfer, the DMA controller executes, if enabled by the software, the pre-programmed amount of cycles.

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    The DMA controller provides distinct DMA transfer channels. The channels can be individually configured in term of source and destination location, DMA transfer size, data type, priority level and operating mode. The DMA controller opens one channel at a time, according to channel priorities.

    Features of the DMA controller:• 7 DMA transfer channels, independently configurable by software• Per-channel DMA transfer trigger upon request from a peripheral• Per-channel DMA transfer triggered by software (memory-to-memory mode)• Programmable channel priority levels: very high, high, medium and low• By-default (hardware) channel priority levels, to arbitrate concurrent requests from

    channels with identical programmable priority levels• Byte (8-bit unit), half-word (16-bit unit) and word (32-bit unit) DMA transfer data types,

    programmable independently for the source and the destination• Automatic alignment of DMA transfer source and destination addresses according to

    their respective data types• Circular operating mode support• DMA Half Transfer, DMA Transfer Complete and DMA Transfer Error flags, logically

    OR-ed together in a single interrupt request per channel• Memory-to-memory, peripheral-to-memory, memory-to-peripheral and peripheral-to-

    peripheral DMA transfer types• DMA transfer size programmable up to 65535 DMA transfer cycles• Access to Flash memory, SRAM, APB and AHB peripherals as source and destination

    3.12 Interrupts and eventsThe device flexibly manages events causing interrupts of linear program execution, called exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC) and an extended interrupt/event controller (EXTI) are the assets contributing to handling the exceptions. Exceptions include core-internal events such as, for example, a division by zero and, core-external events such as logical level changes on physical lines. Exceptions result in interrupting the program flow, executing an interrupt service routine (ISR) then resuming the original program flow.

    The processor context (contents of program pointer and status registers) is stacked upon program interrupt and unstacked upon program resume, by hardware. This avoids context stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving time, code and power. The ability to abandon and restart load-multiple and store-multiple operations significantly increases the device’s responsiveness in processing exceptions.

    3.12.1 Nested vectored interrupt controller (NVIC)The configurable nested vectored interrupt controller is tightly coupled with the core. It handles physical line events associated with a non-maskable interrupt (NMI) and maskable interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.

    The tight coupling of the processor core with NVIC significantly reduces the latency between interrupt events and start of corresponding interrupt service routines (ISRs). The ISR vectors are listed in a vector table, stored in the NVIC at a base address. The vector

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    address of an ISR to execute is hardware-built from the vector table base address and the ISR order number used as offset.

    If a higher-priority interrupt event happens while a lower-priority interrupt event occurring just before is waiting for being served, the later-arriving higher-priority interrupt event is served first. Another optimization is called tail-chaining. Upon a return from a higher-priority ISR then start of a pending lower-priority ISR, the unnecessary processor context unstacking and stacking is skipped. This reduces latency and contributes to power efficiency.

    Features of the NVIC:• Low-latency interrupt processing• 4 priority levels• Handling of a non-maskable interrupt (NMI)• Handling of 32 maskable interrupt lines• Handling of 10 Cortex-M0+ exceptions• Later-arriving higher-priority interrupt processed first• Tail-chaining• Interrupt vector retrieval by hardware

    3.12.2 Extended interrupt/event controller (EXTI)The extended interrupt/event controller adds flexibility in handling physical line events and allows identifying wake-up events at processor wakeup from Stop mode.

    The EXTI controller has 33 channels, of which 16 with rising, falling or rising and falling edge detector capability. Any GPIO and a few peripheral signals can be connected to these channels.

    The channels can be independently masked.

    The EXTI controller can capture pulses shorter than the internal clock period.

    A register in the EXTI controller latches every event even in Stop mode, which allows the software to identify the origin of the processor's wake-up from Stop mode or, to identify the GPIO and the edge event having caused an interrupt.

    3.13 Analog-to-digital converter (ADC)A native 12-bit analog-to-digital converter is embedded into STM32G070CB/KB/RB devices. It can be extended to 16-bit resolution through hardware oversampling. The ADC has up to 16 external channels and 3 internal channels (temperature sensor, voltage reference, VBAT monitoring). It performs conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

    The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of ~2 MSps even with a low CPU speed. An auto-shutdown function guarantees that the ADC is powered off except during the active conversion phase.

    The ADC can be served by the DMA controller. It can operate in the whole VDD supply range.

    The ADC features a hardware oversampler up to 256 samples, improving the resolution to 16 bits (refer to AN2668).

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    An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

    The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions with timers.

    3.13.1 Temperature sensorThe temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.

    The temperature sensor is internally connected to an ADC input to convert the sensor output voltage into a digital value.

    The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor may vary from part to part due to process variation, the uncalibrated internal temperature sensor is suitable only for relative temperature measurements.

    To improve the accuracy of the temperature sensor, each part is individually factory-calibrated by ST. The resulting calibration data are stored in the part’s System memory, accessible in read-only mode.

    3.13.2 Internal voltage reference (VREFINT)

    The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC. VREFINT is internally connected to an ADC input. The VREFINT voltage is individually precisely measured for each part by ST during production test and stored in the part’s System memory. It is accessible in read-only mode.

    3.13.3 VBAT battery voltage monitoringThis embedded hardware feature allows the application to measure the VBAT battery voltage using an internal ADC input. As the VBAT voltage may be higher than VDDA and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third the VBAT voltage.

    Table 4. Temperature sensor calibration values Calibration value name Description Memory address

    TS_CAL1TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV)

    0x1FFF 75A8 - 0x1FFF 75A9

    Table 5. Internal voltage reference calibration values Calibration value name Description Memory address

    VREFINTRaw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV)

    0x1FFF 75AA - 0x1FFF 75AB

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    3.14 Timers and watchdogsThe device includes an advanced-control timer, six general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. Table 6 compares features of the advanced control, general purpose and basic timers.

    3.14.1 Advanced-control timer (TIM1)The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:• input capture• output compare• PWM output (edge or center-aligned modes) with full modulation capability (0-100%)• one-pulse mode output

    In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled, so as to turn off any power switches driven by these outputs.

    Many features are shared with those of the general-purpose TIMx timers (described in Section 3.14.2) using the same architecture, so the advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

    Table 6. Timer feature comparison

    Timer type Timer Counter resolutionCounter

    type

    Maximum operating frequency

    Prescaler factor

    DMA request

    generation

    Capture/compare channels

    Comple-mentary outputs

    Advanced- control TIM1 16-bit

    Up, down, up/down 64 MHz

    Integer from 1 to 216 Yes 4 3

    General-purpose

    TIM3 16-bit Up, down, up/down 64 MHzInteger from

    1 to 216 Yes 4 -

    TIM14 16-bit Up 64 MHz Integer from 1 to 216 No 1 -

    TIM15 16-bit Up 64 MHz Integer from 1 to 216 Yes 2 1

    TIM16TIM17 16-bit Up 64 MHz

    Integer from 1 to 216 Yes 1 1

    Basic TIM6TIM7 16-bit Up 64 MHzInteger from

    1 to 216 Yes - -

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    3.14.2 General-purpose timers (TIM3, TIM14, TIM15, TIM16, TIM17)There are six synchronizable general-purpose timers embedded in the device (refer to Table 6 for comparison). Each general-purpose timer can be used to generate PWM outputs or act as a simple timebase.• TIM3

    This is a full-featured general-purpose timer with 16-bit auto-reload up/downcounter and 16-bit prescaler.It has four independent channels for input capture/output compare, PWM or one-pulse mode output. It can operate in combination with other general-purpose timers via the Timer Link feature for synchronization or event chaining. It can generate independent DMA request and support quadrature encoders. Its counter can be frozen in debug mode.

    • TIM14This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one channel for input capture/output compare, PWM output or one-pulse mode output. Its counter can be frozen in debug mode.

    • TIM15, 16 and 17These are general-purpose timers featuring:– 16-bit auto-reload upcounter and 16-bit prescaler– 2 channels and 1 complementary channel for TIM15– 1 channel and 1 complementary channel for TIM16 and TIM17All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can operate together via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request. Their counters can be frozen in debug mode.

    3.14.3 Basic timers (TIM6 and TIM7)

    3.14.4 Independent watchdog (IWDG)The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI). Independent of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Its counter can be frozen in debug mode.

    3.14.5 System window watchdog (WWDG)The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked by the system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug mode.

    These timers can be used as generic 16-bit timebases.

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    3.14.6 SysTick timerThis timer is dedicated to real-time operating systems, but it can also be used as a standard down counter.

    Features of SysTick timer:• 24-bit down counter• Autoreload capability• Maskable system interrupt generation when the counter reaches 0• Programmable clock source

    3.15 Real-time clock (RTC), tamper (TAMP) and backup registersThe device embeds an RTC and five 32-bit backup registers, located in the RTC domain of the silicon die.

    The ways of powering the RTC domain are described in Section 3.7.6.

    The RTC is an independent BCD timer/counter.

    Features of the RTC:• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,

    month, year, in BCD (binary-coded decimal) format • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month• Programmable alarm• On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with

    a master clock• Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be

    used to improve the calendar precision• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal

    inaccuracy• Two anti-tamper detection pins with programmable filter• Timestamp feature to save a calendar snapshot, triggered by an event on the

    timestamp pin, a tamper event or by switching to VBAT mode• 17-bit auto-reload wakeup timer (WUT) for periodic events, with programmable

    resolution and period• Multiple clock sources and references:

    – A 32.768 kHz external crystal (LSE)– An external resonator or oscillator (LSE)– The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)– The high-speed external clock (HSE) divided by 32

    When clocked by LSE, the RTC operates in VBAT mode and in all low-power modes. When clocked by LSI, the RTC does not operate in VBAT mode, but it does in low-power modes.

    All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wake the device up from the low-power modes.

    The backup registers allow keeping 20 bytes of user application data in the event of VDD failure, if a valid backup supply voltage is provided on VBAT pin. They are not affected by the system reset, power reset, and upon the device’s wakeup from Standby mode.

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    3.16 Inter-integrated circuit interface (I2C)The device embeds two I2C-bus peripherals I2C1 and I2C2. Refer to Table 7 for the features.

    The I2C-bus interface handles communication between the microcontroller and the serial I2C-bus. It controls all I2C-bus-specific sequencing, protocol, arbitration and timing.

    Features of the I2C peripheral:• I2C-bus specification and user manual rev. 5 compatibility:

    – Slave and master modes, multimaster capability– Standard-mode (Sm), with a bitrate up to 100 kbit/s– Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses– Programmable setup and hold times– Clock stretching

    • System management bus (SMBus) specification rev 2.0 compatibility:– Hardware PEC (packet error checking) generation and verification with ACK

    control– Address resolution protocol (ARP) support– SMBus alert

    • Power system management protocol (PMBus™) specification rev 1.1 compatibility• Independent clock: a choice of independent clock sources allowing the I2C

    communication speed to be independent of the PCLK reprogramming• Wakeup from Stop mode on address match• Programmable analog and digital noise filters• 1-byte buffer with DMA capability

    Table 7. I2C implementation I2C features(1)

    1. X: supported

    I2C1 I2C2

    Standard mode (up to 100 kbit/s) X X

    Fast mode (up to 400 kbit/s) X X

    Fast Mode Plus (up to 1 Mbit/s) with extra output drive I/Os X X

    Programmable analog and digital noise filters X X

    SMBus/PMBus hardware support X -

    Independent clock X -

    Wakeup from Stop mode on address match X -

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    3.17 Universal synchronous/asynchronous receiver transmitter (USART)The device embeds universal synchronous/asynchronous receivers/transmitters (USART1, USART2, USART3, USART4) that communicate at speeds of up to 6 Mbit/s.

    They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. Some can also support SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have a clock domain independent of the CPU clock, which allows them to wake up the MCU from Stop mode. The wakeup events from Stop mode are programmable and can be: • start bit detection• any received data frame• a specific programmed data frame

    All USART interfaces can be served by the DMA controller.

    3.18 Serial peripheral interface (SPI)Two SPI interfaces allow communication at up to 32 Mbits/s in master and slave modes. It supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives 8 master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and hardware CRC calculation.

    The SPI interfaces can be served by the DMA controller.

    Table 8. USART implementation

    USART modes/features(1)

    1. X: supported

    USART1USART2

    USART3USART4

    Hardware flow control for modem X X

    Continuous communication using DMA X X

    Multiprocessor communication X X

    Synchronous mode X X

    Smartcard mode X -

    Single-wire half-duplex communication X X

    IrDA SIR ENDEC block X -

    LIN mode X -

    Dual clock domain and wakeup from Stop mode X -

    Receiver timeout interrupt X -

    Modbus communication X -

    Auto baud rate detection X -

    Driver Enable X X

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    One standard I2S interface (multiplexed with SPI1) supporting four different audio standards can operate as master or slave, in half-duplex communication mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master mode, it can output a clock for an external audio component at 256 times the sampling frequency.

    3.19 Development support

    3.19.1 Serial wire debug port (SW-DP)An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.

    Table 9. SPI/I2S implementationSPI features(1)

    1. X = supported.

    SPI1 SPI2

    Hardware CRC calculation X X

    Rx/Tx FIFO X X

    NSS pulse mode X X

    I2S mode X -

    TI mode X X

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    4 Pinouts, pin description and alternate functions

    Figure 3. STM32G070RxT LQFP64 pinout

    Figure 4. STM32G070CxT LQFP48 pinout

    MSv47927V1

    PA0

    PA1

    PA2

    PA3

    PA4

    PA5

    PA6

    PA7

    PC

    4P

    C5

    PB

    0P

    B1

    PB

    2P

    B10

    PB

    11P

    B12

    PC11PC12PC13

    PC14-OSC32_INPC15-OSC32_OUT

    VBATVREF+

    VDD/VDDAVSS/VSSA

    NRST

    PF0-OSC_INPF1-OSC_OUT

    PC0PC1PC2PC3

    PC8PA15PA14-BOOT0PA13PA12 [PA10]PA11 [PA9]PA10PD9PD8PC7PC6PA9PA8PB15PB14PB13

    PC

    9P

    D0

    PD

    1P

    D2

    PD

    3P

    D4

    PD

    5P

    D6

    PB

    3P

    B4

    PB

    5P

    B6

    PB

    7P

    B8

    PB

    9P

    C10Top view

    LQFP64

    1

    3456789

    10111213141516

    248

    4645444342414039383736353433

    47

    55 53 52 51 50 4956 5461 59 5764 63 62 60 58

    26 28 29 30 31 3225 2720 22 2417 18 19 21 23

    MSv47928V1

    PA2

    PA3

    PA4

    PA5

    PA6

    PA7

    PB

    0P

    B1

    PB

    2P

    B10

    PB

    11P

    B12

    PC13PC14-OSC32_IN

    PC15-OSC32_OUTVBAT

    VREF+VDD/VDDAVSS/VSSA

    NRST

    PF0-OSC_INPF1-OSC_OUT

    PA0PA1

    PA14-BOOT0PA13PA12 [PA10]PA11 [PA9]PA10PC7PC6PA9PA8PB15PB14PB13

    PA15

    PD

    0P

    D1

    PD

    2P

    D3

    PB

    3P

    B4

    PB

    5P

    B6

    PB

    7P

    B8

    PB

    9Top view

    LQFP48

    123456789101112

    363534333231302928272625

    39 3740 3845 43 4148 47 46 44 42

    22 2421 2316 18 2013 14 15 17 19

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    Figure 5. STM32G070KxT LQFP32 pinout

    MSv47929V1PA

    2PA

    3PA

    4PA

    5PA

    6PA

    7P

    B0

    PB

    1

    PB9PC14-OSC32_IN

    PC15-OSC32_OUTVDD/VDDAVSS/VSSA

    NRSTPA0PA1

    PA13PA12 [PA10]PA11 [PA9]PA10PC6PA9PA8PB2

    PA14

    -BO

    OT0

    PA15

    PB

    3P

    B4

    PB

    5P

    B6

    PB

    7P

    B8Top view

    LQFP32

    12345678

    2423222120191817

    29 27 2532 31 30 28 26

    12 14 169 10 11 13 15

    Table 10. Terms and symbols used in Table 11 Column Symbol Definition

    Pin name Terminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name.

    Pin type

    S Supply pin

    I Input only pin

    I/O Input / output pin

    I/O structure

    FT 5 V tolerant I/O

    TT 3.6 V tolerant I/O

    RST Bidirectional reset pin with embedded weak pull-up resistor

    Options for TT or FT I/Os

    _f I/O, Fm+ capable

    _a I/O, with analog switch function

    _c I/O, with specific electrical characteristics

    _d I/O, with specific electrical characteristics

    Note Upon reset, all I/Os are set as analog inputs, unless otherwise specified.

    Pin functions

    Alternate functions Functions selected through GPIOx_AFR registers

    Additional functions Functions directly selected/enabled through peripheral registers

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    Table 11. Pin assignment and description

    Pin Number

    Pin name

    (function upon reset) P

    in ty

    pe

    I/O s

    truc

    ture

    Not

    e Alternatefunctions

    Additionalfunctions

    LQFP

    32

    LQFP

    48

    LQFP

    64

    - - 1 PC11 I/O FT - USART3_RX, USART4_RX, TIM1_CH4 -

    - - 2 PC12 I/O FT - TIM14_CH1 -

    - 1 3 PC13 I/O FT (1)(2) TIM1_BKIN TAMP_IN1,RTC_TS,RTC_OUT1,WKUP2

    - 2 4PC14-

    OSC32_IN(PC14)

    I/O FT (1)(2) TIM1_BKIN2 OSC32_IN

    2 - -PC14-

    OSC32_IN(PC14)

    I/O FT (1)(2) TIM1_BKIN2 OSC32_IN,OSC_IN

    3 3 5PC15-

    OSC32_OUT(PC15)

    I/O FT (1)(2) OSC32_EN, OSC_EN, TIM15_BKIN OSC32_OUT

    - 4 6 VBAT S - - - -

    - 5 7 VREF+ S - - - -

    4 6 8 VDD/VDDA S - - - -

    5 7 9 VSS/VSSA S - - - -

    - 8 10PF0-OSC_IN

    (PF0)I/O FT - TIM14_CH1 OSC_IN

    - 9 11PF1-OSC_OUT

    (PF1)I/O FT - OSC_EN, TIM15_CH1N OSC_OUT

    6 10 12 NRST I/O FT - - NRST

    - - 13 PC0 I/O FT - - -

    - - 14 PC1 I/O FT - TIM15_CH1- -

    - - 15 PC2 I/O FT - SPI2_MISO, TIM15_CH2 -

    - - 16 PC3 I/O FT - SPI2_MOSI -

    7 11 17 PA0 I/O FT_a - SPI2_SCK, USART2_CTS, USART4_TXADC_IN0,

    TAMP_IN2,WKUP1

  • Pinouts, pin description and alternate functions STM32G070CB/KB/RB

    32/96 DS12766 Rev 1

    8 12 18 PA1 I/O FT_a -

    SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK,

    USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT

    ADC_IN1

    9 13 19 PA2 I/O FT_a - SPI1_MOSI/I2S1_SD, USART2_TX, TIM15_CH1ADC_IN2,

    WKUP4,LSCO

    10 14 20 PA3 I/O FT_a - SPI2_MISO, USART2_RX, TIM15_CH2, EVENTOUT ADC_IN3

    - 15 21 PA4 I/O TT_a - SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, EVENTOUT ADC_IN4, RTC_OUT2

    11 - - PA4 I/O TT_a - SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, EVENTOUT

    ADC_IN4, TAMP_IN1, RTC_TS,

    RTC_OUT1,WKUP2

    12 16 22 PA5 I/O TT_a - SPI1_SCK/I2S1_CK, USART3_TX, EVENTOUT ADC_IN5

    13 17 23 PA6 I/O FT_a -SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN,

    USART3_CTS, TIM16_CH1ADC_IN6

    14 18 24 PA7 I/O FT_a -SPI1_MOSI/I2S1_SD, TIM3_CH2,

    TIM1_CH1N, TIM14_CH1, TIM17_CH1

    ADC_IN7

    - - 25 PC4 I/O FT_a - USART3_TX, USART1_TX ADC_IN17

    - - 26 PC5 I/O FT_a - USART3_RX, USART1_RX ADC_IN18, WKUP5

    15 19 27 PB0 I/O FT_a - SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, USART3_RX ADC_IN8

    16 20 28 PB1 I/O FT_a -

    TIM14_CH1, TIM3_CH4, TIM1_CH3N,

    USART3_RTS_DE_CK, EVENTOUT

    ADC_IN9

    17 21 29 PB2 I/O FT_a - SPI2_MISO, USART3_TX, EVENTOUT ADC_IN10

    - 22 30 PB10 I/O FT_fa - USART3_TX, SPI2_SCK, I2C2_SCL ADC_IN11

    - 23 31 PB11 I/O FT_fa - SPI2_MOSI, USART3_RX, I2C2_SDA ADC_IN15

    Table 11. Pin assignment and description (continued)

    Pin Number

    Pin name

    (function upon reset) P

    in ty

    pe

    I/O s

    truc

    ture

    Not

    e Alternatefunctions

    Additionalfunctions

    LQFP

    32

    LQFP

    48

    LQFP

    64

  • DS12766 Rev 1 33/96

    STM32G070CB/KB/RB Pinouts, pin description and alternate functions

    39

    - 24 32 PB12 I/O FT_a - SPI2_NSS, TIM1_BKIN, TIM15_BKIN, EVENTOUT ADC_IN16

    - 25 33 PB13 I/O FT_f -SPI2_SCK, TIM1_CH1N,

    USART3_CTS, TIM15_CH1N, I2C2_SCL, EVENTOUT

    -

    - 26 34 PB14 I/O FT_f -

    SPI2_MISO, TIM1_CH2N, USART3_RTS_DE_CK, TIM15_CH1, I2C2_SDA,

    EVENTOUT

    -

    - 27 35 PB15 I/O FT_c -SPI2_MOSI, TIM1_CH3N,

    TIM15_CH1N, TIM15_CH2, EVENTOUT

    RTC_REFIN

    18 28 36 PA8 I/O FT_c - MCO, SPI2_NSS, TIM1_CH1, EVENTOUT -

    19 29 37 PA9 I/O FT_fd -MCO, USART1_TX, TIM1_CH2,

    SPI2_MISO, TIM15_BKIN, I2C1_SCL, EVENTOUT

    -

    20 30 38 PC6 I/O FT - TIM3_CH1 -

    - 31 39 PC7 I/O FT - TIM3_CH2 -

    - - 40 PD8 I/O FT - USART3_TX, SPI1_SCK/I2S1_CK -

    - - 41 PD9 I/O FT - USART3_RX, SPI1_NSS/I2S1_WS, TIM1_BKIN2 -

    21 32 42 PA10 I/O FT_fd -SPI2_MOSI, USART1_RX, TIM1_CH3, TIM17_BKIN, I2C1_SDA, EVENTOUT

    -

    22 33 43 PA11[PA9](3) I/O FT_f -SPI1_MISO/I2S1_MCK,

    USART1_CTS, TIM1_CH4, TIM1_BKIN2, I2C2_SCL

    -

    23 34 44 PA12[PA10](3) I/O FT_f -SPI1_MOSI/I2S1_SD,

    USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN, I2C2_SDA

    -

    24 35 45 PA13 I/O FT (4) SWDIO, IR_OUT, EVENTOUT -

    25 36 46 PA14-BOOT0 I/O FT (4) SWCLK, USART2_TX, EVENTOUT BOOT0

    Table 11. Pin assignment and description (continued)

    Pin Number

    Pin name

    (function upon reset) P

    in ty

    pe

    I/O s

    truc

    ture

    Not

    e Alternatefunctions

    Additionalfunctions

    LQFP

    32

    LQFP

    48

    LQFP

    64

  • Pinouts, pin description and alternate functions STM32G070CB/KB/RB

    34/96 DS12766 Rev 1

    26 37 47 PA15 I/O FT -

    SPI1_NSS/I2S1_WS, USART2_RX,

    USART4_RTS_DE_CK, USART3_RTS_DE_CK,

    EVENTOUT

    -

    - - 48 PC8 I/O FT - TIM3_CH3, TIM1_CH1 -

    - - 49 PC9 I/O FT - I2S_CKIN, TIM3_CH4, TIM1_CH2 -

    - 38 50 PD0 I/O FT_c - EVENTOUT, SPI2_NSS, TIM16_CH1 -

    - 39 51 PD1 I/O FT_d - EVENTOUT, SPI2_SCK, TIM17_CH1 -

    - 40 52 PD2 I/O FT_c - USART3_RTS_DE_CK, TIM3_ETR, TIM1_CH1N -

    - 41 53 PD3 I/O FT_d - USART2_CTS, SPI2_MISO, TIM1_CH2N -

    - - 54 PD4 I/O FT - USART2_RTS_DE_CK, SPI2_MOSI, TIM1_CH3N -

    - - 55 PD5 I/O FT -USART2_TX,

    SPI1_MISO/I2S1_MCK, TIM1_BKIN

    -

    - - 56 PD6 I/O FT - USART2_RX, SPI1_MOSI/I2S1_SD -

    27 42 57 PB3 I/O FT_a -SPI1_SCK/I2S1_CK, TIM1_CH2,

    USART1_RTS_DE_CK, EVENTOUT

    -

    28 43 58 PB4 I/O FT_a -SPI1_MISO/I2S1_MCK,

    TIM3_CH1, USART1_CTS, TIM17_BKIN, EVENTOUT

    -

    29 44 59 PB5 I/O FT - SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, I2C1_SMBA WKUP6

    30 45 60 PB6 I/O FT_fa -USART1_TX, TIM1_CH3,

    TIM16_CH1N, SPI2_MISO, I2C1_SCL, EVENTOUT

    -

    31 46 61 PB7 I/O FT_fa -USART1_RX, SPI2_MOSI,

    TIM17_CH1N, USART4_CTS, I2C1_SDA, EVENTOUT

    -

    Table 11. Pin assignment and description (continued)

    Pin Number

    Pin name

    (function upon reset) P

    in ty

    pe

    I/O s

    truc

    ture

    Not

    e Alternatefunctions

    Additionalfunctions

    LQFP

    32

    LQFP

    48

    LQFP

    64

  • DS12766 Rev 1 35/96

    STM32G070CB/KB/RB Pinouts, pin description and alternate functions

    39

    32 47 62 PB8 I/O FT_f -SPI2_SCK, TIM16_CH1,

    USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT

    -

    1 48 63 PB9 I/O FT_f -IR_OUT, TIM17_CH1,

    USART3_RX, SPI2_NSS, I2C1_SDA, EVENTOUT

    -

    - - 64 PC10 I/O FT - USART3_TX, USART4_TX, TIM1_CH3 -

    1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

    - The speed should not exceed 2 MHz with a maximum load of 30 pF

    - These GPIOs must not be used as current sources (for example to drive an LED).

    2. After a RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers as they are not reset by the system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0444 reference manual.

    3. Pin pair PA9/PA10 can be remapped in place of pin pair PA11/PA12 (default mapping), using SYSCFG_CFGR1 register.

    4. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.

    Table 11. Pin assignment and description (continued)

    Pin Number

    Pin name

    (function upon reset) P

    in ty

    pe

    I/O s

    truc

    ture

    Not

    e Alternatefunctions

    Additionalfunctions

    LQFP

    32

    LQFP

    48

    LQFP

    64

  • Pinouts, pin description and alternate functionsSTM

    32G070C

    B/K

    B/R

    B

    36/96D

    S12766 Rev 1

    Table 12. Port A alternate function mapping Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

    PA0 SPI2_SCK USART2_CTS - - USART4_TX - - -

    PA1 SPI1_SCK/I2S1_CKUSART2_RTS

    _DE_CK - - USART4_RX TIM15_CH1N I2C1_SMBA EVENTOUT

    PA2 SPI1_MOSI/I2S1_SD USART2_TX - - - TIM15_CH1 - -

    PA3 SPI2_MISO USART2_RX - - - TIM15_CH2 - EVENTOUT

    PA4 SPI1_NSS/I2S1_WS SPI2_MOSI - - TIM14_CH1 - - EVENTOUT

    PA5 SPI1_SCK/I2S1_CK - - - USART3_TX - - EVENTOUT

    PA6 SPI1_MISO/I2S1_MCK TIM3_CH1 TIM1_BKIN - USART3_CTS TIM16_CH1 - -

    PA7 SPI1_MOSI/I2S1_SD TIM3_CH2 TIM1_CH1N - TIM14_CH1 TIM17_CH1 - -

    PA8 MCO SPI2_NSS TIM1_CH1 - - - - EVENTOUT

    PA9 MCO USART1_TX TIM1_CH2 - SPI2_MISO TIM15_BKIN I2C1_SCL EVENTOUT

    PA10 SPI2_MOSI USART1_RX TIM1_CH3 - - TIM17_BKIN I2C1_SDA EVENTOUT

    PA11 SPI1_MISO/I2S1_MCK USART1_CTS TIM1_CH4 - - TIM1_BKIN2 I2C2_SCL -

    PA12 SPI1_MOSI/I2S1_SDUSART1_RTS

    _DE_CK TIM1_ETR - - I2S_CKIN I2C2_SDA -

    PA13 SWDIO IR_OUT - - - - - EVENTOUT

    PA14 SWCLK USART2_TX - - - - - EVENTOUT

    PA15 SPI1_NSS/I2S1_WS USART2_RX - -USART4_RTS

    _DE_CKUSART3_RTS

    _DE_CK - EVENTOUT

  • STM32G

    070CB

    /KB

    /RB

    Pinouts, pin description and alternate functions

    DS12766 R

    ev 137/96

    Table 13. Port B alternate function mapping Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

    PB0 SPI1_NSS/I2S1_WS TIM3_CH3 TIM1_CH2N - USART3_RX - - -

    PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N - USART3_RTS_DE_CK - - EVENTOUT

    PB2 - SPI2_MISO - - USART3_TX - - EVENTOUT

    PB3 SPI1_SCK/I2S1_CK TIM1_CH2 - -USART1_RTS

    _DE_CK - - EVENTOUT

    PB4 SPI1_MISO/I2S1_MCK TIM3_CH1 - - USART1_CTS TIM17_BKIN - EVENTOUT

    PB5 SPI1_MOSI/I2S1_SD TIM3_CH2 TIM16_BKIN - - - I2C1_SMBA -

    PB6 USART1_TX TIM1_CH3 TIM16_CH1N - SPI2_MISO - I2C1_SCL EVENTOUT

    PB7 USART1_RX SPI2_MOSI TIM17_CH1N - USART4_CTS - I2C1_SDA EVENTOUT

    PB8 - SPI2_SCK TIM16_CH1 - USART3_TX TIM15_BKIN I2C1_SCL EVENTOUT

    PB9 IR_OUT - TIM17_CH1 - USART3_RX SPI2_NSS I2C1_SDA EVENTOUT

    PB10 - - - - USART3_TX SPI2_SCK I2C2_SCL -

    PB11 SPI2_MOSI - - - USART3_RX - I2C2_SDA -

    PB12 SPI2_NSS - TIM1_BKIN - - TIM15_BKIN - EVENTOUT

    PB13 SPI2_SCK - TIM1_CH1N - USART3_CTS TIM15_CH1N I2C2_SCL EVENTOUT

    PB14 SPI2_MISO - TIM1_CH2N - USART3_RTS_DE_CK TIM15_CH1 I2C2_SDA EVENTOUT

    PB15 SPI2_MOSI - TIM1_CH3N - TIM15_CH1N TIM15_CH2 - EVENTOUT

  • Pinouts, pin description and alternate functionsSTM

    32G070C

    B/K

    B/R

    B

    38/96D

    S12766 Rev 1

    Table 14. Port C alternate function mapping Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

    PC0 - - - - - - - -

    PC1 - - TIM15_CH1 - - - - -

    PC2 - SPI2_MISO TIM15_CH2 - - - - -

    PC3 - SPI2_MOSI - - - - - -

    PC4 USART3_TX USART1_TX - - - - - -

    PC5 USART3_RX USART1_RX - - - - - -

    PC6 - TIM3_CH1 - - - - - -

    PC7 - TIM3_CH2 - - - - - -

    PC8 - TIM3_CH3 TIM1_CH1 - - - - -

    PC9 I2S_CKIN TIM3_CH4 TIM1_CH2 - - - - -

    PC10 USART3_TX USART4_TX TIM1_CH3 - - - - -

    PC11 USART3_RX USART4_RX TIM1_CH4 - - - - -

    PC12 - - TIM14_CH1 - - - - -

    PC13 - - TIM1_BKIN - - - - -

    PC14 - - TIM1_BKIN2 - - - - -

    PC15 OSC32_EN OSC_EN TIM15_BKIN - - - - -

  • STM32G

    070CB

    /KB

    /RB

    Pinouts, pin description and alternate functions

    DS12766 R

    ev 139/96

    *

    Table 15. Port D alternate function mapping Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

    PD0 EVENTOUT SPI2_NSS TIM16_CH1 - - - - -

    PD1 EVENTOUT SPI2_SCK TIM17_CH1 - - - - -

    PD2 USART3_RTS_DE_CK TIM3_ETR TIM1_CH1N - - - - -

    PD3 USART2_CTS SPI2_MISO TIM1_CH2N - - - - -

    PD4 USART2_RTS_DE_CK SPI2_MOSI TIM1_CH3N - - - - -

    PD5 USART2_TX SPI1_MISO/I2S1_MCK TIM1_BKIN - - - - -

    PD6 USART2_RX SPI1_MOSI/I2S1_SD - - - - - -

    PD8 USART3_TX SPI1_SCK/I2S1_CK - - - - - -

    PD9 USART3_RX SPI1_NSS/I2S1_WS TIM1_BKIN2 - - - - -

    Table 16. Port F alternate function mapping Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

    PF0 - - TIM14_CH1 - - - - -

    PF1 OSC_EN - TIM15_CH1N - - - - -

  • Electrical characteristics STM32G070CB/KB/RB

    40/96 DS12766 Rev 1

    5 Electrical characteristics

    5.1 Parameter conditionsUnless otherwise specified, all voltages are referenced to VSS.

    TBD indicates a value to be defined.

    5.1.1 Minimum and maximum valuesUnless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TA(max) (given by the selected temperature range).

    Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ).

    5.1.2 Typical valuesUnless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested.

    Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ).

    5.1.3 Typical curvesUnless otherwise specified, all typical curves are given only as design guidelines and are not tested.

    5.1.4 Loading capacitorThe loading conditions used for pin parameter measurement are shown in Figure 6.

    5.1.5 Pin input voltageThe input voltage measurement on a pin of the device is described in Figure 7.

    Figure 6. Pin loading conditions Figure 7. Pin input voltage

    MS19210V1

    MCU pin

    C = 50 pF

    MS19211V1

    MCU pin

    VIN

  • DS12766 Rev 1 41/96

    STM32G070CB/KB/RB Electrical characteristics

    83

    5.1.6 Power supply scheme

    Figure 8. Power supply scheme

    Caution: Power supply pin pair (VDD/VDDA and VSS/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

    5.1.7 Current consumption measurement

    Figure 9. Current consumption measurement scheme

    MSv47984V1

    VDD

    Backup circuitry(LSE, RTC and

    backup registers)

    Kernel logic(CPU, digital and

    memories)

    Leve

    l shi

    fter

    IOlogicIN

    OUT

    Regulator

    GPIOs

    1.55 V to 3.6 V

    1 x 100 nF+ 1 x 4.7 μF

    VDD/VDDA

    VBAT

    VCORE

    Power switch

    VDDIO1

    ADCVREF+VREF-

    VSS/VSSA

    VREF

    100 nF

    VSS

    VSSA

    VDDA

    VDD

    VREF+

    MSv47901V1

    IDDVBATVBAT

    IDDVDD

    (VDDA)

    VBAT

    VDD/VDDA

  • Electrical characteristics STM32G070CB/KB/RB

    42/96 DS12766 Rev 1

    5.2 Absolute maximum ratingsStresses above the absolute maximum ratings listed in Table 17, Table 18 and Table 19 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

    Table 17. Voltage characteristics Symbol Ratings Min Max Unit

    VDD - VSSExternal supply voltage -0.3 4.0

    V

    VBAT - VSS

    VIN(1)Input voltage on FT_xx pins except FT_c VSS - 0.3 VDD + 4.0(2)

    Input voltage on FT_c pins VSS - 0.3 5.5

    Input voltage on any other pin VSS - 0.3 4.0

    1. Refer to Table 18 for the maximum allowed injected current values.

    2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

    Table 18. Current characteristics Symbol Ratings Max Unit

    IVDD/VDDA Current into VDD/VDDA power pin (source)(1) 100

    mA

    IVSS/VSSA Current out of VSS/VSSA ground pin (sink)(1) 100

    IIO(PIN)

    Output current sunk by any I/O and control pin except FT_f 15

    Output current sunk by any FT_f pin 20

    Output current sourced by any I/O and control pin 15

    ∑IIO(PIN)Total output current sunk by sum of all I/Os and control pins(2) 80

    Total output current sourced by sum of all I/Os and control pins(2) 80

    IINJ(PIN)(3) Injected current on a FT_xx pin -5 / NA

    (4)

    Injected current on a TT_a pin(5) -5 / 0

    ∑|IINJ(PIN)| Total injected current (