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ARM Cortex-M0. CORTEX-M0 Structure Discussion 3. August 23, 2012 Paul Nickelsberg Orchid Technologies Engineering and Consulting, Inc. www.orchid-tech.com. Cortex-M0 Structure Discussion 3. Topics Today CORTEX-M0 Power Management CORTEX-M0 Fault Handling CORTEX-M0 Stack Structures - PowerPoint PPT Presentation
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ARM Cortex-M0
August 23, 2012Paul Nickelsberg
Orchid Technologies Engineering and Consulting, Inc.
www.orchid-tech.com
CORTEX-M0 Structure Discussion 3
Cortex-M0 Structure Discussion 3
Topics Today• CORTEX-M0 Power Management• CORTEX-M0 Fault Handling• CORTEX-M0 Stack Structures• CORTEX-M0 SVC/WFE/WFI Instructions
Cortex-M0 Power ManagementOur discussion focuses on Cortex-M0 Power Managementas distinct from additional power management features which may be implemented by a particular device vendor
Cortex-M0 Power ManagementLow Power Instruction Execution
Sleep Mode Support
Deep Sleep Mode Support
Wake-Up Interrupt Controller
WFE / WFI Instruction Support
Device Specific Power ManagementPeripheral Power On/Off Control
Phase Locked Loop Control
Peripheral Clock Source Control
Peripheral Clock Rate Control
State Saving Registers
Real Time Clock Features
On-Chip Oscillator Support
Cortex-M0 Power ManagementLow Power Instruction Execution
App
rox
Cur
rent
in m
A
Approx Speed in MHz
Cortex-M0 Power Management
• Sleep ModeStops Processor Clock
• Deep Sleep ModeStops System Clock, Power off PLL, and Memory
• Mode Selection made using SCB Register
Cortex-M0 Power Modes
Cortex-M0 Power Management
• WFI InstructionExecution of WFI Instruction causes processor to immediately enter selected sleep mode
• WFE InstructionExecution of WFE Instruction causes processor to enter selected sleep mode if event bit is set
• Exit Processor ExceptionIf SLEEPONEXIT bit is set in SCB Register, processor enters selected sleep mode on return from exception to thread mode
Cortex-M0 Entry into Power Saving Modes
Cortex-M0 Power Management
• Wake-Up from WFI or SLEEPONEXITUpon receipt of Prioritized Interrupt, processor immediately resumes execution of instructions
• Wakeup from WFEUpon receipt of Prioritized Interrupt or external event signal, processor immediately resumes execution of instructions
• Wakeup using WICUpon receipt of Wake-up Interrupt Controller Signal, processor immediately resumes execution of instruction. This feature is optional and when implemented usually applies to Deep Sleep wakeup only
Cortex-M0 Exit from Power Saving Modes
Cortex-M0 Power Management
Normal Instruction Execution WFI
Normal Instruction ExecutionSleepIR
Q
Time
Full Pwr
Low Pwr
Cortex-M0 Fault Handling• HARDFAULT Vector
The HARDFAULT Vector catches processor faults
• Processor Faults• SVC Instruction Priority Error• BKPT w/o Debugger• System Generated Bus Error• Attempted execution of instruction in XN Memory Area• Attempted execution of undefined instruction• Attempted load or store to unaligned address
• Processor Lockup (Double Fault)Occurs when Fault occurs in NMI or HARDFAULT Handler
Cortex-M0 Fault Handling
Normal Instruction ExecutionB
ad In
stru
ctio
n
Normal Instruction ExecutionHardFault
RES
ET
Bad
Inst
ruct
ion
Lock Up
Reset or NMI restarts processor
HardFault Exception preempts all other exceptions
Cortex-M0 Stack Structure• Cortex-M0 Stack pushes data onto the stack
from higher to lower addresses
SP ContentSP + 0x1C PSRSP + 0x18 PCSP + 0x14 LRSP + 0x10 R12SP + 0x0C R3SP + 0x08 R2SP + 0x04 R1SP + 0x00 R0
SP Here before Interrupt
SP Here after Interrupt
Meaning and Implications
Processor Architecture – 8 Bit World to 32 Bit World
Pro
cess
ing
Cap
abili
ty
8 Bit Architecture
32 Bit CORTEX-M0
- Low Power Instruction Execution- Sleep Power Mode- Deep Sleep Power Mode- WFI / WFE Sleep Entry- Fault Handling
