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11121B–ATARM–08-Mar-13 Description The Atmel SAMA5D3 series is a high-performance, power-efficient embedded MPU based on the ARM ® Cortex ® -A5 processor, achieving 536 MHz with power consumption levels below 0.5 mW in low-power mode. The device features a floating point unit for high-precision computing and accelerated data processing, and a high data bandwidth architecture. It integrates advanced user interface and connectivity peripherals and security features. The SAMA5D3 series features an internal multi-layer bus architecture associated with 39 DMA channels to sustain the high bandwidth required by the processor and the high-speed peripherals. The device offers support for DDR2/LPDDR/LPDDR2 and MLC NAND Flash memory with 24-bit ECC. The comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image composition, a touchscreen interface and a CMOS sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE1588, 10/100 EMAC, multiple CAN, UART, SPI and I2C. With its secure boot mechanism, hardware accelerated engines for encryption (AES, TDES) and hash function (SHA), the SAMA5D3 ensures anti-cloning, code protection and secure external data transfers. The SAMA5D3 series is optimized for control panel/HMI applications and applications that require high levels of connectivity in the industrial and consumer markets. Its low- power consumption levels make the SAMA5D3 particularly suited for battery-powered devices. There are four SAMA5D3 devices in this series. Table 1-1 “SAMA5D3 Devices” shows the differences in the embedded features. All other features are available on all derivatives; this includes the three USB ports as well as the encryption engine and secure boot features. ARM-based Embedded MPU SAMA5D3 Series DATASHEET

Atmel 11121 32 Bit Cortex A5 Microcontroller SAMA5D3 Datasheet

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Text of Atmel 11121 32 Bit Cortex A5 Microcontroller SAMA5D3 Datasheet

ARM-based Embedded MPUSAMA5D3 SeriesDATASHEET

DescriptionThe Atmel SAMA5D3 series is a high-performance, power-efficient embedded MPU based on the ARM Cortex -A5 processor, achieving 536 MHz with power consumption levels below 0.5 mW in low-power mode. The device features a floating point unit for high-precision computing and accelerated data processing, and a high data bandwidth architecture. It integrates advanced user interface and connectivity peripherals and security features. The SAMA5D3 series features an internal multi-layer bus architecture associated with 39 DMA channels to sustain the high bandwidth required by the processor and the high-speed peripherals. The device offers support for DDR2/LPDDR/LPDDR2 and MLC NAND Flash memory with 24-bit ECC. The comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image composition, a touchscreen interface and a CMOS sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE1588, 10/100 EMAC, multiple CAN, UART, SPI and I2C. With its secure boot mechanism, hardware accelerated engines for encryption (AES, TDES) and hash function (SHA), the SAMA5D3 ensures anti-cloning, code protection and secure external data transfers. The SAMA5D3 series is optimized for control panel/HMI applications and applications that require high levels of connectivity in the industrial and consumer markets. Its lowpower consumption levels make the SAMA5D3 particularly suited for battery-powered devices. There are four SAMA5D3 devices in this series. Table 1-1 SAMA5D3 Devices shows the differences in the embedded features. All other features are available on all derivatives; this includes the three USB ports as well as the encryption engine and secure boot features.

11121BATARM08-Mar-13

1.

Featuresz

Corez

ARM Cortex-A5 Processor with ARM v7-A Thumb2 Instruction Setz

CPU Frequency up to 536 MHz

z z

32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA) Fully Integrated MMU and Floating Point Unit (VFPv4) One 160 Kbyte Internal ROM Single-cycle Access at System Speed, Embedded Boot Loader: Boot on NAND Flash, SDCard, eMMC, serial DataFlash, selectable Order One 128 Kbyte Internal SRAM, Single-cycle Access at System Speed High Bandwidth 32-bit Multi-port Dynamic Ram Controller supporting 512 Mbyte 8 bank DDR2/LPDDR/LPDDR2 Independent Static Memory Controller with SLC/MLC NAND Support with up to 24-bit Error Correcting Code (PMECC) Power-on Reset Cells, Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real-time Clock Boot Mode Select Option, Remap Command Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillators Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator One 400 to 1000 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed 39 DMA Channels including two 8-channel 64-bit Central DMA Controllers 64-bit Advanced Interrupt Controller Three Programmable External Clock Signals Programmable Fuse Box with 256 fuse bits, 192 of them available for Customer Shut Down Controller Battery Backup Registers Clock Generator and Power Management Controller Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities LCD TFT Controller with Overlay, Alpha-blending, Rotation, Scaling and Color Space Conversion ITU-R BT. 601/656 Image Sensor Interface Three HS/FS/LS USB Ports with On-Chip Transceiversz z

z

Memoriesz z z z

z

System running up to 166 MHzz z z z z z z z z

z

Low Power Managementz z z z

z

Peripheralsz z z

One Device Controller One Host Controller with Integrated Root Hub (3 Downstream Ports)

z z z z z z z z z z

One 10/100/1000 Mbps Gigabit Ethernet Mac Controller (GMAC) with IEEE1588 support One 10/100 Mbps Ethernet Mac Controller (EMAC) Two CAN Controllers with 8 Mailboxes, fully Compliant with CAN 2.0 Part A and 2.0 Part B Softmodem Interface Three High Speed Memory Card Hosts (eMMC 4.3 and SD 2.0) Two Master/Slave Serial Peripheral Interface Two Synchronous Serial Controllers Three Two-wire Interface up to 400 Kbits supporting I2C Protocol and SMBUS Four USARTs, two UARTs, one DBGU Two Three-channel 32-bit Timer/Counters

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

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z z z

One Four-channel 16-bit PWM Controller One 12-channel 12-bit Analog-to-Digital Converter with Resistive Touch-Screen function Write Protected Registers TRNG: True Random Number Generator Encryption Enginez z z

z

Securityz z

AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications TDES: Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512)

z

Atmel Secure Boot Solution Five 32-bit Parallel Input/Output Controllers 160 I/Os Input Change Interrupt Capability on Each I/O Line, Selectable Schmitt Trigger Input Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering Slew Rate Control on High Speed I/Os Impedance Control on DDR I/Os 324-ball LFBGA, pitch 0.8 mm

z

I/Oz z z z z z

z

Packagez

Table 1-1.

SAMA5D3 Devices SAMA5D31 SAMA5D33 X X X X X X X X SAMA5D34 X X X X X X X X X SAMA5D35

LCDC GMAC EMAC CAN0, CAN1 HSMCI2 UART0 UART1 TC1

X

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

3

2.

Block Diagram

Figure 2-1. SAMA5D3 Block DiagramDH S DH DP SD /HH M/ SD HH PA G1 SD 25 MA GT CK -G X GT CK 12 5 X GC EN GRX CKO -G C GRRS, TX K X G E GR ER CO R - L GT X0- GRX X GR D GM 0-G X7 V D TX7 ER C, G M ET EFC DI O X K EC EN R ER SD V, X E T 0- E E R X R X EM 0-ET X1 ER DC X1 ,E LC MD LCD-D D_ AT0 IO LC V -L D_ SY CD LC PC NC _ D_ K , L DA DE , LC CD T23 N, D_ _H LC D S IS I_D D_ ISP YN C PW IS OI_P IS M I _ C IS I_H K D11 SY NC , IS I_V SY NC DD R_ CA LP DD R_ CA LN

NT RS T TD I TD O TM TC S/SW K/S D WC IO LK JTA GS EL

TST

BMS

HH S HH DPC SD H H MC HH SDP SD B MB VB G

SysCFIQ IRQPIO

JTAG / SWDAICIn-Circuit Emulator

HS Trans

HS Trans

HS Trans

PIO

DDR_VREF DDR_A0-DDR_A13 DDR_D0-DDR_D31 DDR_DQM[3..0] DDR_DQS[3..0]

DRXD DTXD PCK0-PCK2

DBGU

PC PB

PA HS USB Device DMA GMAC 10/100/1000 EMAC 10/100 LCD ISI

Cortex-A5PLLA PLLUTMIICache 32 KB MMU BIU

VFP DCache 32 KB

HS EHCI USB HOST DMA

DDR2 LPDDR2 512 MB

XIN XOUT

Osc12 MHz

PMC

DMA

DMA

DMA

DMA

12 MHZ RC Osc WDT RCXIN32 XOUT32 SHDN WKUP VDDBU NRST OSC 32K

I/DPIT4 GPBR EBI

DDR_DQSN[3..0] DDR_CS DDR_CLK,DDR_CLKN DDR_CKE DDR_RAS, DDR_CAS DDR_WE DDR_BA[2..0] D0-D15 A21/NANDALE A22/NANDCLE NRD/NANDOE NWE/NWR0/NANDWE NCS3/NANDCS NANDRDY A0/NBS0 A1-A20 A23-A25 NWR1/NBS1 NCS0,NCS1,NCS2 NWAIT

Multi-Layer MatrixRTC RSTCTRNG SHA AES TDES DMA

SHDC POR POR PIOA PIOC PIOE

NAND Flash Controller MCL/SLC ECC (4 KB SRAM)

PIOB PIOD

ROM 160 KB

SRAM0 64 KB

SRAM1 64 KB

8-CH DMA0

8-CH DMA1

Peripheral Bridge

Reduced Static Memory Controller

PIO

DMA CAN0 CAN1 TWI0 TWI1 TWI2

DMA USART0 USART1 USART2 USART3

DMA

DMA SPI0 SPI1

DMA SSC0 SSC1

DMA MCI0/MCI1/MCI2 SD/SDIO eMMC TC0, TC1 TC2, TC3 TC4, TC5

DMA 4-CH PWM

UART0 UART1

Real-time Events

DMA 12-CH 12-bit ADC TouchScreen SMD

PIO

PN CA RX NT 0-C X0 A -C NR A X TW NT 1 TW D0 X1 CK -TW 0TW D2 CK CT 2 S RT 03 SCS03 RDK0X 3 TX 0-3 UR D0 D -3 UT X0NP UR X CS D0 D X 1, NP -UT 1 XD CS 1 2, NP C NP S3 CS SP 0 C M K O M SI TK ISO 0 TF -TK TD 0-T 1 F 0 RD -T 1 0 D RF -RD1 0 1 RK -RF 0 1 M -RK CI 1 M 0_C CI D M 1_ A CI C D 2 M _C A C D M I0_ A CI C M MC 1_CK CI I K M 0_D 2_C CI A K M 1_D [7..0 CI A ] 2 [ TI _D 3..0 O A ] TI A0 [3.. O -T 0] B TC 0 IO -T A PW LK0 IOB5 M -TC 5 LK PW H0 5 PW ML PW M 0-P MH FI W 3 0- M PW L3 M TS FI AD 3 TR AD IG 0U AD L 1 AD UR 2 AD LL GP 3 AD A LR 5- D4 G P TS PAD I AD 11 VR EF

DIB

SPI0_, SPI1_

CA

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

DI

BN

4

3.

Signal DescriptionTable 3-1 gives details on the signal names classified by peripheral.Signal Description List Function Type Active Level Frequency (MHz) Comments

Table 3-1.

Signal Name Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 VBG PCK0 - PCK2 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Bias Voltage Reference for USB Programmable Clock Output Input Output Input Output Analog Output

Shutdown, Wake-up Logic SHDN WKUP Shut-Down Control Wake-Up Input ICE and JTAG TCK/SWCLK TDI TDO TMS/SWDIO JTAGSEL Test Clock/Serial Wire Clock Test Data In Test Data Out Test Mode Select/Serial Wire Input/Output JTAG Selection Reset/Test NRST TST NTRST BMS Microcontroller Reset Test Mode Select Test Reset Signal Boot Mode Select I/O Input Input Input Debug Unit - DBGU DRXD DTXD Debug Receive Data Debug Transmit Data Input Output Advanced Interrupt Controller - AIC IRQ FIQ External Interrupt Input Fast Interrupt Input Input Input Low Input Input Output I/O Input Output Input

PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE PA0 - PAxx PB0 - PBxx PC0 - PCxx PD0 - PDxx PE0 - PExx Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C Parallel IO Controller D Parallel IO Controller E I/O I/O I/O I/O I/O

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

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Table 3-1.

Signal Description List (Continued) Function Type Active Level Frequency (MHz) Comments

Signal Name External Bus Interface - EBI D0 - D15 A0 - A25 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Static Memory Controller - HSMC NCS0 - NCS3 NWR0 - NWR1 NRD NWE NBS0 - NBS1 NANDOE NANDWE Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal NAND Flash Output Enable NAND Flash Write Enable Output Output Output Output Output Output Output DDR2/LPDDR Controller DDR_VREF DDR_CALP DDR_CALN DDR_CK, DDR_CKN DDR_CKE DDR_CS DDR_BA[2..0] DDR_WE DDR_RAS, DDR_CAS DDR_A[13..0] DDR_D[31..0] DQS[3..0] DQSN[3..0] DQM[3..0] Reference Voltage Positive Calibration Reference Negative Calibration Reference DDR2 differential clock DDR2 Clock Enable DDR2 Controller Chip Select Bank Select DDR2 Write Enable Row and Column Signal DDR2 Address Bus DDR2 Data Bus Differential Data Strobe DQSN must be connected to DDR_VREF for DDR2 memories Write Data Mask Input Input Input Output Output Output Output Output Output Output I/O/-PD I/O- PD I/O- PD Output

Low

Low Low Low Low Low Low Low

High Low Low Low Low

High Speed Multimedia Card Interface - HSMCI0-2 MCI0_CK, MCI1_CK, MCI2_CK MCI0_CDA,MCI1_C DA, MCI2_CDA MCI0_DA[7..0] MCI1_DA[3..0] MCI2_DA[3..0) Multimedia Card Clock Multimedia Card Command Multimedia Card 0 Data Multimedia Card 1 Data Multimedia Card 2 Data I/O I/O I/O I/O I/O

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

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Table 3-1.

Signal Description List (Continued) Function Type Active Level Frequency (MHz) Comments

Signal Name

Universal Synchronous Asynchronous Receiver Transmitter- USART0-3 SCKx TXDx RXDx RTSx CTSx USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send I/O Output Input Output Input

Universal Asynchronous Receiver Transmitter - UARTx [1..0] UTXDx URXDx UARTx Transmit Data UARTx Receive Data Output Input

Synchronous Serial Controller - SSCx [1..0] TDx RDx TKx RKx TFx RFx SSC Transmit Data SSC Receive Data SSC Transmit Clock SSC Receive Clock SSC Transmit Frame Sync SSC Receive Frame Sync Timer/Counter - TCx [5..0] TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O Output Input I/O I/O I/O I/O

Serial Peripheral Interface - SPIx [1..0] SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS[3..1] Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select I/O I/O I/O I/O Output Low Low

Two-Wire Interface -TWIx [2..0] TWDx TWCKx Two-wire Serial Data Two-wire Serial Clock I/O I/O CAN controller - CANx CANRXx CANTXx CAN input CAN output Input Output Soft Modem - SMD DIBN DIBP Soft Modem Signal Soft Modem Signal I/O I/O

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

7

Table 3-1.

Signal Description List (Continued) Function Type Active Level Frequency (MHz) Comments

Signal Name

Pulse Width Modulation Controller- PWMC PWMH[3..0] PWML[3..0] PWMFIx PWM Waveform Output High PWM Waveform Output LOW PWM Fault Input Output Output Input USB Host High Speed Port - UHPHS HHSDPA HHSDMA HHSDPB HHSDMB HHSDPC HHSDMC USB Host Port A High Speed Data + USB Host Port A High Speed Data USB Host Port B High Speed Data + USB Host Port B High Speed Data USB Host Port C High Speed Data + USB Host Port C High Speed Data Analog Analog Analog Analog Analog Analog

USB Device High Speed Port - UDPHS DHSDP DHSDM USB Device High Speed Data + USB Device High Speed Data Analog Analog

GIgabit Ethernet 10/100/1000 - GMAC GTXCK G125CK G125CKO GTXEN GTX[7..0] GTXER GRXCK GRXDV GRX[7..0] GRXER GCRS GCOL GMDC GMDIO Transmit Clock or Reference Clock 125 MHz input Clock 125 MHz output Clock Transmit Enable Transmit Data Transmit Coding Error Receive Clock Receive Data Valid Receive Data Receive Error Carrier Sense and Data Valid Collision Detect Management Data Clock Management Data Input/Output Input Input Output Output Output Output Input Input Input Input Input Input Output I/O

RMII Ethernet 10/100 - EMAC EREFCK ETXEN ETX[1..0] ECRSDV ERX[1..0] ERXER Transmit Clock or Reference Clock Transmit Enable Transmit Data Carrier Sense/Data Valid Receive Data Receive Error Input Output Output Input Input Input

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

8

Table 3-1.

Signal Description List (Continued) Function Type Output I/O Active Level Frequency (MHz) Comments

Signal Name EMDC EMDIO Management Data Clock Management Data Input/Output

LCD Controller - LCDC LCDDAT[23..0] LCDVSYNC LCDHSYNC LCDPCK LCDDEN LCDPWM LCDDISP LCD Data Bus LCD Vertical Synchronization LCD Horizontal Synchronization LCD pixel Clock LCD Data Enable LCDPWM for Contrast Control LCD Display ON/OFF Output Output Output Output Output Output Output Image Sensor Interface - ISI ISI_D[11..0] ISI_HSYNC ISI_VSYNC ISI_PCK Image Sensor Data Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data clock Input input input input

Touch Screen Analog-to-Digital Converter - ADC AD0UL AD1UR AD2LL AD3LR AD4PI AD5-AD11 ADTRG ADVREF Upper Left Touch Panel Upper Right Touch Panel Lower Left Touch Panel Lower Right Touch Panel Panel Input 7 Analog Inputs ADC Trigger ADC Reference Analog Analog Analog Analog Analog Analog Input Analog

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

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4.

Package and PinoutThe SAMA5D3 product is available in a 324-ball LFBGA package.

4.1

Mechanical Overview of the 324-ball LFBGA PackageFigure 4-1 shows the orientation of the 324-ball BGA Package.

Figure 4-1. Orientation of the 324-ball LFBGA PackageBottom VIEWV U T R P N M L K J H G F E D C B A

1 2

3 4 5 6 7 8 9 10 11 12 13 14 15

16 17 18

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

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4.2

324-ball LFBGA Package PinoutSAMA5D3 Pinout for 324-ball LFBGA PackagePrimary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, STPIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST ISI_D0 ISI_D1 TWD2 TWCK2 PWMH0 PWML0 PWMH1 PWML1 I/O O O O O O ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 I I I I I I I I PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST URXD1 UTXD1 PWMH0 PWML0 TK1 TF1 PWMH1 PWML1 TD1 RK1 I O O O I/O I/O O O O I ISI_VSYNC ISI_HSYNC I I PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST

Table 4-1.

PinE3 F5 D2 F4 D1 J10 G4 J9 F3 J8 E2 K8 F2 G6 E1 H5 H3 H6 H4 H7 H2 J6 G2 J5 F1 J4 G3 J3 G1 K4 H1 K3 T2 N7 T3 N6 P5 T4 R4 U1

Power RailVDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1

I/O TypeGPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO_CLK2 GPIO GPIO GPIO GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC

SignalPA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

DirI/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Signal

Dir

SignalLCDDAT0 LCDDAT1 LCDDAT2 LCDDAT3 LCDDAT4 LCDDAT5 LCDDAT6 LCDDAT7 LCDDAT8 LCDDAT9 LCDDAT10 LCDDAT11 LCDDAT12 LCDDAT13 LCDDAT14 LCDDAT15 LCDDAT16 LCDDAT17 LCDDAT18 LCDDAT19 LCDDAT20 LCDDAT21 LCDDAT22 LCDDAT23 LCDPWM LCDDISP LCDVSYNC LCDHSYNC LCDPCK LCDDEN TWD0 TWCK0 GTX0 GTX1 GTX2 GTX3 GRX0 GRX1 GRX2 GRX3

DirO O O O O O O O O O O O O O O O O O O O O O O O O O O O O O I/O O O O O O I I I I

Signal

Dir

Signal

Dir

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

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Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, STPIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST GTX4 GTX5 GTX6 GTX7 GRX4 GRX5 GRX6 GRX7 G125CKO O O O O I I I I O PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST TIOA3 TIOB3 TCLK3 TIOA4 TIOB4 TCLK4 TIOA5 TIOB5 TCLK5 I/O I/O I I/O I/O I I/O I/O I PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST LCDDAT20 LCDDAT19 TIOA1 TIOB1 TCLK1 PCK2 I/O I/O I O LCDDAT18 LCDDAT17 LCDDAT16 LCDDAT21 O O O O O O PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST

PinR5 P3 R6 V3 P6 V1 R7 U3 P7 V2 V5 T6 N8 U4 M7 U5 M8 T5 N9 V4 M9 P8 M10 R9 D8 A4 E8 A3 A2 F8 B3 G8 B4 F7 A1 D7 C6 E7 B2 F6 B1 E6 C3

Power RailVDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0

I/O TypeGMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GMAC GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO MCI_CLK GPIO GPIO GPIO

SignalPB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18

DirI/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Signal

Dir

SignalGTXCK GTXEN GTXER GRXCK GRXDV GRXER GCRS GCOL GMDC GMDIO G125CK MCI1_CDA MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI1_CK SCK1 CTS1 RTS1 RXD1 TXD1 DRXD DTXD ETX0 ETX1 ERX0 ERX1 ETXEN ECRSDV ERXER EREFCK EMDC EMDIO MCI2_CDA MCI2_DA0 MCI2_DA1 MCI2_DA2 MCI2_DA3 MCI2_CK TK0 TF0 TD0

DirI O O I I I I I O I/O I I/O I/O I/O I/O I/O I/O I/O I O I O I O O O I I O I I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O O

SignalPWMH2 PWML2 RF1 RD1 PWMH3 PWML3 CANRX1 CANTX1

DirO O I/O I O O I O

Signal

Dir

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

12

Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, STPIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST TWD1 TWCK1 PWMFI0 PWMFI2 I/O O I I ISI_D11 ISI_D10 ISI_D9 ISI_D8 ISI_PCK PWMFI1 I I I I I O PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST TIOA0 TIOB0 TCLK0 I/O I/O I PWMH2 PWML2 PWMH3 PWML3 O O O O PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 O O O CANRX0 CANTX0 PWMFI3 I O I PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST

PinD6 C4 D5 C2 G9 C1 H10 H9 D4 H8 G5 D3 E4 K5 P1 K6 R1 L7 P2 L8 R2 K7 U2 K9 M5 K10 N4 L9 N3 L10 N5 M6 T1 N2 M3 M2 L3 M1 N1 L1 L2 K1 K2

Power RailVDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA

I/O TypeGPIO GPIO GPIO GPIO GPIO GPIO_CLK GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO MCI_CLK GPIO GPIO GPIO_CLK GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA GPIO_ANA

SignalPC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29

DirI/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Signal

Dir

SignalRK0 RF0 RD0 SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 URXD0 UTXD0 FIQ MCI0_CDA MCI0_DA0 MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI0_DA4 MCI0_DA5 MCI0_DA6 MCI0_DA7 MCI0_CK SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 SCK0 CTS0 RTS0 RXD0 TXD0 ADTRG AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9

DirI/O I/O I I/O I/O I/O I/O O O O I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I O I I I I I I I I I I I

Signal

Dir

Signal

Dir

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

13

Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, STPIO, I, PU, ST PIO, I, PU, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST SCK3 CTS3 RTS3 RXD3 TXD3 SCK2 I/O I O I O I/O A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST CTS2 RTS2 RXD2 TXD2 TIOA2 TIOB2 TCLK2 I O I O I/O I/O I LCDDAT22 LCDDAT23 O O A,I, PD, ST A,I, PD, ST A,I, PD, ST A,I, PD, ST PIO,I, PD, ST PIO, I, PD, ST PIO, I, PD, ST PIO, I, PD, ST PWML1 O PIO,I, PD, ST I, PD, I I O I O O I, ST I, PU, ST

PinJ1 J2 P13 R14 R13 V18 P14 U18 T18 R15 P17 P15 P18 R16 N16 R17 N17 R18 N18 P16 M18 N15 M15 N14 M17 M13 M16 N12 M14 M12 L13 L15 L14 L16 U15 U9 U8 V8 U16 V16 T12 T10 V9

Power RailVDDANA VDDANA VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDBU VDDIOP0 VDDIOP0 VDDIOP0 VDDBU VDDBU VDDBU VDDBU VDDIOP0

I/O TypeGPIO_ANA GPIO_ANA EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI SYSC SYSC CLOCK CLOCK CLOCK CLOCK SYSC SYSC RSTJTAG

SignalPD30 PD31 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31 TST BMS XIN XOUT XIN32 XOUT32 SHDN WKUP NRST

DirI/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I O I O O I I/O

Signal

Dir

SignalAD10 AD11 A0/NBS0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21/NANDALE A22/NANDCLE A23 A24 A25 NCS0 NCS1 NCS2 NWR1/NBS1 NWAIT IRQ

DirI I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O I I

SignalPCK0 PCK1

DirO O

Signal

Dir

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

14

Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, STI, PU, ST I, ST O SWDIO SWCLK I/O I I, ST I, ST I, PD O, PU O, PU I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD I, PD O, PU I, PU O, PU O, PU I O O O O O O O O O O O O O O

PinP11 R8 M11 N10 P9 T9 V6 U6 K12 K15 K14 K16 K13 K17 J12 K18 J14 J16 J13 J17 J15 J18 H16 H18 L12 L18 L17 K11 C13 B10 C11 A9 D11 B9 E10 D10 A8 C10 B8 F11 A7 D9 A6

Power RailVDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDBU VDDIOP0 VDDIOP0 VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR

I/O TypeRSTJTAG RSTJTAG RSTJTAG RSTJTAG RSTJTAG SYSC DIB DIB EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI EBI

SignalNTRST TDI TDO TMS TCK JTAGSEL DIBP DIBN D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 NCS3/NANDCS NANDRDY NRD/NANDOE NWE/NANDWE DDR_VREF

DirI I O I I I O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I O O I O O O O O O O O O O O O O O

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

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Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, STHiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ O O O O I, PD I, PD I, PD I, PD I, PU I, PU I, PU

PinH12 H17 H13 G17 G16 H15 F17 G15 F16 E17 G14 E16 D17 C18 D16 C17 B16 B18 C15 A18 C16 C14 D15 B14 A15 A14 E12 A11 B11 F12 A10 E11 G12 E15 B15 D12 E18 G18 B17 B13 D18 F18 A17

Power RailVDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR

I/O TypeDDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO

SignalDDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31 DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3 DDR_DQS0 DDR_DQS1 DDR_DQS2 DDR_DQS3 DDR_DQSN0 DDR_DQSN1 DDR_DQSN2

DirI/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O I/O I/O I/O I/O I/O I/O I/O

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

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Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, STI, PU O O O O O O O O O O O O I O, PD O, PD O, PD O, PD DHSDP DHSDM O, PD O, PD I I

PinA13 C8 B12 A12 B7 C12 E13 G11 A5 B5 E9 B6 F9 R11 U14 V14 U12 V12 U10 V10 V15 T13 C5, C7, D14, T15, T7, U17, V7 A16, C9, N13, T14, T8, V17 D13, F14, G10, G13, H11 E14, F10, F13, F15, H14 P12, T16 J11, T17 G7, V11 L11, M4

Power RailVDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR VBG VDDUTMII VDDUTMII VDDUTMII VDDUTMII VDDUTMII VDDUTMII VDDBU GNDBU

I/O TypeDDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO DDR_IO VBG USBHS USBHS USBHS USBHS USBHS USBHS power supply ground

SignalDDR_DQSN3 DDR_CS DDR_CLK DDR_CLKN DDR_CKE DDR_CALN DDR_CALP DDR_RAS DDR_CAS DDR_WE DDR_BA0 DDR_BA1 DDR_BA2 VBG HHSDPC HHSDMC HHSDPB HHSDMB HHSDPA HHSDMA VDDBU GNDBU

DirI/O O O O O I I O O O O O O I I/O I/O I/O I/O I/O I/O I I

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

VDDCORE

power supply

VDDCORE

I

I

GNDCORE

ground

GNDCORE

I

I

VDDIODDR

power supply

VDDIODDR

I

I

GNDIODDR

ground

GNDIODDR

I

I

VDDIOM

power supply

VDDIOM

I

I

GNDIOM

ground

GNDIOM

I

I

VDDIOP0

power supply

VDDIOP0

I

I

VDDIOP1

power supply

VDDIOP1

I

I

SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

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Table 4-1.

SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, STI

PinE5, J7, N11, U7 V13 U13 R12 R10 P10 U11 T11 L6 L4 L5 R3 P4

Power RailGNDIOP

I/O TypeGround

SignalGNDIOP

DirI

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

VDDUTMIC VDDUTMII GNDUTMI VDDPLLA GNDPLL VDDOSC GNDOSC VDDANA GNDANA VDDANA VDDFUSE GNDFUSE

Power supply Power supply Ground Power supply Ground Power supply Ground Power supply Ground Power supply Power supply Ground

VDDUTMIC VDDUTMII GNDUTMI VDDPLLA GNDPLL VDDOSC GNDOSC VDDANA GNDANA ADVREF VDDFUSE GNDFUSE

I I I I I I I I I I I I

I I I I I I I I I I I I

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4.3

Input/Output DescriptionSAMA5 I/O Types DescriptionVoltage Range 1.65-3.6V 1.65-3.6V 1.65-3.6V 3.0-3.6V 1.65-1.95V, 3.0-3.6V 3.0-3.6V 1.65-3.6V 3.0-3.6V 1.65-3.6V 3.0-3.6V I/O I/O I/O I Pull-up Analog Pull-up Switchable Switchable Switchable Switchable Switchable Reset State Typ Value (Ohm) 100K 100K 100K 100K 100K 100K Switchable Reset State Reset State 100K 100K 15K Reset State Reset State Pull-down Switchable Switchable Switchable Pull-down Typ Value (Ohm) 100K 100K 100K Schmitt Trigger Switchable Switchable Switchable Switchable

Table 4-2.I/O Type GPIO GPIO_CLK GPIO_CLK2 GPIO_ANA EBI RSTJTAG SYSC USBHS CLOCK DIB

When Reset State is indicated, the configuration is defined by the Reset State column of the Pin Description table (see Table 4-1 on page 11).

Table 4-3.I/O Type GPIO MCI_CLK GPIO_CLK GPIO_CLK2 GPIO_ANA

SAMA5 I/O Type Assignation and FrequencyI/O Frequency (MHz) 33 52 66 75 25 Load (pF) 40 20 20 20 20 16 mA, 40 mA (peak) Fan-out Drive Control High/Medium/Low High/Medium/Low High/Medium/Low High/Medium/Low Fixed to Medium High/Medium/Low 1.8V/3.3V High/Medium/Low Fixed to Low Fixed to Medium No No No No High/Medium/Low Signal Name All PIO lines except the lines indicated further on in this table MCI0CK, MCI1CK,MCI2CK SPI0CK, SPI1CK, ETXCLK,ERXCLK LCDDOTCK ADx

EBI DDR_IO RST JTAG SYSC VBG USBHS CLOCK GMAC

66 166 3 10 0.25 0.25 480 50 125

50 20 10 10 10 10 20 50 15

All EBI signals All DDR signals NRST, NTRST, BMS TCK, TDI, TMS, TDO WKUP, SHDN, JTAGSEL, TST, SHDN VBG HHSDPC, HHSDPB, HHSDPA/DHSDP, HHSDMC, HHSDMB, HHSDMA/DHSDM XIN, XOUT, XIN32, XOUT32 Gigabit Ethernet I/Os

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5.5.1

Power ConsiderationsPower SuppliesTable 5-1 defines the power supply rails and the estimated power consumption at typical voltage.Table 5-1. Name SAMA5D3 Power supplies Voltage Range, Nominal 1.1-1.32V, 1.2V 1.7-1.9V, 1.8V 1.14-1.30, 1.2V 1.65-1.95V, 1.8V 3.0-3.6V, 3.3V 1.65-3.6V 1.65-3.6V 1.65-3.6V 1.1-1.32V, 1.2V 3.0-3.6V, 3.3V 1.1-1.32V, 1.2V 1.65-3.6V 3.0-3.6V, 3.3V 2.25-2.75V, 2.5V Associated Ground Powers The core, including the processor, the embedded memories and the peripherals LPDDR/DDR2 Interface I/O lines LPDDR2 Interface I/O lines NAND and HSMC Interface I/O lines Peripheral I/O lines Peripheral I/O lines The Slow Clock oscillator, the internal 32 kHz RC Oscillator and a part of the System Controller The USB device and host UTMI+ core The UTMI PLL The USB device and host UTMI+ interface The PLLA cell Main Oscillator cell and VBG if 3.0VUDPHS_CTRL &= ~AT91C_UDPHS_EN_UDPHS; AT91C_BASE_UDPHS->UDPHS_CTRL |= AT91C_UDPHS_EN_UDPHS; // With OR without DMA !!! for( i=1; iUDPHS_IPFEATURES & AT91C_UDPHS_DMA_CHANNEL_NBR)>>4); i++ ) { // RESET endpoint canal DMA: // DMA stop channel command AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command // Disable endpoint AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLDIS |= 0XFFFFFFFF; // Reset endpoint config AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLCFG = 0; // Reset DMA channel (Buff count and Control field) AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0x02; // NON STOP command // Reset DMA channel 0 (STOP) AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command // Clear DMA channel status (read the register for clear it) AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS = AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS; }

32.6.10 Handling Transactions with USB V2.0 Device Peripheral32.6.10.1 Setup Transaction The setup packet is valid in the DPR while RX_SETUP is set. Once RX_SETUP is cleared by the application, the UDPHS accepts the next packets sent over the device endpoint. When a valid setup packet is accepted by the UDPHS:z z z z

The UDPHS device automatically acknowledges the setup packet (sends an ACK response) Payload data is written in the endpoint Sets the RX_SETUP interrupt The BYTE_COUNT field in the UDPHS_EPTSTAx register is updated

An endpoint interrupt is generated while RX_SETUP in the UDPHS_EPTSTAx register is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect RX_SETUP polling UDPHS_EPTSTAx or catching an interrupt, read the setup packet in the FIFO, then clear the RX_SETUP bit in the UDPHS_EPTCLRSTA register to acknowledge the setup stage. If STALL_SNT was set to 1, then this bit is automatically reset when a setup token is detected by the device. Then, the device still accepts the setup stage. (See Section 32.6.10.15 STALL on page 766).

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32.6.10.2 NYET NYET is a High Speed only handshake. It is returned by a High Speed endpoint as part of the PING protocol. High Speed devices must support an improved NAK mechanism for Bulk OUT and control endpoints (except setup stage). This mechanism allows the device to tell the host whether it has sufficient endpoint space for the next OUT transfer (see USB 2.0 spec 8.5.1 NAK Limiting via Ping Flow Control). The NYET/ACK response to a High Speed Bulk OUT transfer and the PING response are automatically handled by hardware in the UDPHS_EPTCTLx register (except when the user wants to force a NAK response by using the NYET_DIS bit). If the endpoint responds instead to the OUT/DATA transaction with an NYET handshake, this means that the endpoint accepted the data but does not have room for another data payload. The host controller must return to using a PING token until the endpoint indicates it has space available.Figure 32-8. NYET Example with Two Endpoint Banks

data 0 ACK

data 1 NYET

PING

ACK

data 0 NYET

PING

NACK

PING

ACK

t=0

t = 125 s

t = 250 s

t = 375 s

t = 500 s

t = 625 s

E: empty E': begin to empty F: full

Bank 1 E Bank 0 F

Bank 1 F Bank 1 F Bank 0 E' Bank 0 E

Bank 1 F Bank 0 E

Bank 1 F Bank 0 F

Bank 1 E' Bank 0 F

Bank 1 E Bank 0 F

32.6.10.3 Data IN 32.6.10.4 Bulk IN or Interrupt IN Data IN packets are sent by the device during the data or the status stage of a control transfer or during an (interrupt/bulk/isochronous) IN transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel. There are three ways for an application to transfer a buffer in several packets over the USB:z z z

packet by packet (see 32.6.10.5 below)64 KB (see 32.6.10.5 below)

DMA (see 32.6.10.6 below)

32.6.10.5 Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host) The application can write one or several banks. A simple algorithm can be used by the application to send packets regardless of the number of banks associated to the endpoint. Algorithm Description for Each Packet:z z z

The application waits for TXRDY flag to be cleared in the UDPHS_EPTSTAx register before it can perform a write access to the DPR. The application writes one USB packet of data in the DPR through the 64 KB endpoint logical memory window. The application sets TXRDY flag in the UDPHS_EPTSETSTAx register.

The application is notified that it is possible to write a new packet to the DPR by the TXRDY interrupt. This interrupt can be enabled or masked by setting the TXRDY bit in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register. Algorithm Description to Fill Several Packets: Using the previous algorithm, the application is interrupted for each packet. It is possible to reduce the application overhead by writing linearly several banks at the same time. The AUTO_VALID bit in the UDPHS_EPTCTLx must be set by writing the AUTO_VALID bit in the UDPHS_EPTCTLENBx register.

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The auto-valid-bank mechanism allows the transfer of data (IN and OUT) without the intervention of the CPU. This means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware.z z z

The application checks the BUSY_BANK_STA field in the UDPHS_EPTSTAx register. The application must wait that at least one bank is free. The application writes a number of bytes inferior to the number of free DPR banks for the endpoint. Each time the application writes the last byte of a bank, the TXRDY signal is automatically set by the UDPHS. If the last packet is incomplete (i.e., the last byte of the bank has not been written) the application must set the TXRDY bit in the UDPHS_EPTSETSTAx register.

The application is notified that all banks are free, so that it is possible to write another burst of packets by the BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the BUSY_BANK flag in the UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers. This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism does not operate. A Zero Length Packet can be sent by setting just the TXRDY flag in the UDPHS_EPTSETSTAx register. 32.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buffer from the memory to the DPR or from the DPR to the processor memory under the UDPHS control. The DMA can be used for all transfer types except control transfer. Example DMA configuration: 1. 2. 3. Program UDPHS_DMAADDRESS x with the address of the buffer that should be transferred. Enable the interrupt of the DMA in UDPHS_IEN Program UDPHS_ DMACONTROLx:z z

Size of buffer to send: size of the buffer to be sent to the host. END_B_EN: The endpoint can validate the packet (according to the values programmed in the AUTO_VALID and SHRT_PCKT fields of UDPHS_EPTCTLx.) (See UDPHS Endpoint Control Disable Register (Isochronous Endpoint) on page 791 and Figure 32-13. Autovalid with DMA) END_BUFFIT: generate an interrupt when the BUFF_COUNT in UDPHS_DMASTATUSx reaches 0. CHANN_ENB: Run and stop at end of buffer

z z

The auto-valid-bank mechanism allows the transfer of data (IN & OUT) without the intervention of the CPU. This means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware. A transfer descriptor can be used. Instead of programming the register directly, a descriptor should be programmed and the address of this descriptor is then given to UDPHS_DMANXTDSC to be processed after setting the LDNXT_DSC field (Load Next Descriptor Now) in UDPHS_DMACONTROLx register. The structure that defines this transfer descriptor must be aligned. Each buffer to be transferred must be described by a DMA Transfer descriptor (see UDPHS DMA Channel Transfer Descriptor on page 810). Transfer descriptors are chained. Before executing transfer of the buffer, the UDPHS may fetch a new transfer descriptor from the memory address pointed by the UDPHS_DMANXTDSCx register. Once the transfer is complete, the transfer status is updated in the UDPHS_DMASTATUSx register. To chain a new transfer descriptor with the current DMA transfer, the DMA channel must be stopped. To do so, INTDIS_DMA and TXRDY may be set in the UDPHS_EPTCTLENBx register. It is also possible for the application to wait for the c omple tion of all trans fers. In t his ca se the LDNXT_DSC f ield in the las t trans fer desc ripto r UDPHS_DMACONTROLx register must be set to 0 and CHANN_ENB set to 1. Then the application can chain a new transfer descriptor. The INTDIS_DMA can be used to stop the current DMA transfer if an enabled interrupt is triggered. This can be used to stop DMA transfers in case of errors. The application can be notified at the end of any buffer transfer (ENB_BUFFIT bit in the UDPHS_DMACONTROLx register).

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Figure 32-9. Data IN Transfer for Endpoint with One BankPrevous Data IN TX Microcontroller Loads Data in FIFO Data is Sent on USB Bus

USB Bus Packets

Token IN

Data IN 1

ACK

Token IN

NAK

Token IN

Data IN 2

ACK

TXRDY Flag (UDPHS_EPTSTAx) Set by firmware

Cleared by hardware

Set by the firmware Interrupt Pending

Cleared by hardware Interrupt Pending Payload in FIFO

TX_COMPLT Flag (UDPHS_EPTSTAx)

Set by hardware DPR access by firmware

Cleared by firmware DPR access by hardware Data IN 2

Cleared by firmware

FIFO Content

Data IN 1

Load in progress

Figure 32-10. Data IN Transfer for Endpoint with Two BanksMicrocontroller Load Data IN Bank 0 USB Bus Packets Microcontroller Load Data IN Bank 1 UDPHS Device Send Bank 0 Microcontroller Load Data IN Bank 0 UDPHS Device Send Bank 1

Token IN

Data IN

ACK

Token IN

Data IN

ACK

Set by Firmware, Cleared by Hardware Data Payload Written switch to next bank in FIFO Bank 0 Virtual TXRDY bank 0 (UDPHS_EPTSTAx) Virtual TXRDY bank 1 (UDPHS_EPTSTAx)

Cleared by Hardware Data Payload Fully Transmitted

Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending Set by Hardware Interrupt Cleared by Firmware Set by Hardware

TX_COMPLT Flag (UDPHS_EPTSTAx) FIFO (DPR) Bank 0

Written by Microcontroller

Read by USB Device

Written by Microcontroller

FIFO (DPR) Bank1

Written by Microcontroller

Read by UDPHS Device

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Figure 32-11. Data IN Followed By Status OUT Transfer at the End of a Control TransferDevice Sends the Last Data Payload to Host USB Bus Packets Device Sends a Status OUT to Host ACK ACK

Token IN

Data IN

ACK

Token OUT

Data OUT (ZLP)

Token OUT

Data OUT (ZLP)

Interrupt PendingRXRDY (UDPHS_EPTSTAx) Set by Hardware Cleared by Firmware TX_COMPLT (UDPHS_EPTSTAx) Set by Hardware Cleared by Firmware

Note:

A NAK handshake is always generated at the first status stage token.

Figure 32-12. Data OUT Followed by Status IN TransferHost Sends the Last Data Payload to the Device Device Sends a Status IN to the Host

USB Bus Packets

Token OUT

Data OUT

ACK

Token IN

Data IN

ACK

Interrupt Pending RXRDY (UDPHS_EPTSTAx) Set by Hardware TXRDY (UDPHS_EPTSTAx) Set by Firmware Clear by Hardware

Cleared by Firmware

Note:

Before proceeding to the status stage, the software should determine that there is no risk of extra data from the host (data stage). If not certain (non-predictable data stage length), then the software should wait for a NAK-IN interrupt before proceeding to the status stage. This precaution should be taken to avoid collision in the FIFO.

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Figure 32-13. Autovalid with DMABank (system) Bank 0 Bank 1 Bank 0 Bank 1

Write

write bank 0

write bank 1 bank 1 is full

write bank 0 bank 0 is full

bank 0 is full

Bank 1

Bank 0 IN data 0 IN data 1 IN data 0

Bank (usb)

Bank 0

Bank 1

Bank 0

Bank 1

Virtual TXRDY Bank 0

Virtual TXRDY Bank 1

TXRDY (Virtual 0 & Virtual 1)

Note:

In the illustration above Autovalid validates a bank as full, although this might not be the case, in order to continue processing data and to send to DMA.

32.6.10.7 Isochronous IN Isochronous-IN is used to transmit a stream of data whose timing is implied by the delivery rate. Isochronous transfer provides periodic, continuous communication between host and device. It guarantees bandwidth and low latencies appropriate for telephony, audio, video, etc. If the endpoint is not available (TXRDY_TRER = 0), then the device does not answer to the host. An ERR_FL_ISO interrupt is generated in the UDPHS_EPTSTAx register and once enabled, then sent to the CPU. The STALL_SNT command bit is not used for an ISO-IN endpoint. 32.6.10.8 High Bandwidth Isochronous Endpoint Handling: IN Example For high bandwidth isochronous endpoints, the DMA can be programmed with the number of transactions (BUFF_LENGTH field in UDPHS_DMACONTROLx) and the system should provide the required number of packets per microframe, otherwise, the host will notice a sequencing problem. A response should be made to the first token IN recognized inside a microframe under the following conditions:z

If at least one bank has been validated, the correct DATAx corresponding to the programmed Number Of Transactions per Microframe (NB_TRANS) should be answered. In case of a subsequent missed or corrupted token IN inside the microframe, the USB 2.0 Core available data bank(s) that should normally have been transmitted during that microframe shall be flushed at its end. If this flush occurs, an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx).

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z z

If no bank is validated yet, the default DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). Then, no data bank is flushed at microframe end. If no data bank has been validated at the time when a response should be made for the second transaction of NB_TRANS = 3 transactions microframe, a DATA1 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). If and only if remaining untransmitted banks for that microframe are available at its end, they are flushed and an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx). If no data bank has been validated at the time when a response should be made for the last programmed transaction of a microframe, a DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). If and only if the remaining untransmitted data bank for that microframe is available at its end, it is flushed and an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx). If at the end of a microframe no valid token IN has been recognized, no data bank is flushed and no error condition is reported.

z

z

At the end of a microframe in which at least one data bank has been transmitted, if less than NB_TRANS banks have been validated for that microframe, an error condition is flagged (ERR_TRANS is set in UDPHS_EPTSTAx). Cases of Error (in UDPHS_EPTSTAx)z z

ERR_FL_ISO: There was no data to transmit inside a microframe, so a ZLP is answered by default. ERR_FLUSH: At least one packet has been sent inside the microframe, but the number of token IN received is lesser than the number of transactions actually validated (TXRDY_TRER) and likewise with the NB_TRANS programmed. ERR_TRANS: At least one packet has been sent inside the microframe, but the number of token IN received is lesser than the number of programmed NB_TRANS transactions and the packets not requested were not validated. ERR_FL_ISO + ERR_FLUSH: At least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token IN. ERR_FL_ISO + ERR_TRANS: At least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token IN and the data can be discarded at the microframe end. ERR_FLUSH + ERR_TRANS: The first token IN has been answered and it was the only one received, a second bank has been validated but not the third, whereas NB_TRANS was waiting for three transactions. ERR_FL_ISO + ERR_FLUSH + ERR_TRANS: The first token IN has been treated, the data for the second Token IN was not available in time, but the second bank has been validated before the end of the microframe. The third bank has not been validated, but three transactions have been set in NB_TRANS.

z

z z z z

32.6.10.9 Data OUT 32.6.10.10 Bulk OUT or Interrupt OUT Like data IN, data OUT packets are sent by the host during the data or the status stage of control transfer or during an interrupt/bulk/isochronous OUT transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel. 32.6.10.11 Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device) Algorithm Description for Each Packet:z z z z

The application enables an interrupt on RXRDY_TXKL. When an interrupt on RXRDY_TXKL is received, the application knows that UDPHS_EPTSTAx register BYTE_COUNT bytes have been received. The application reads the BYTE_COUNT bytes from the endpoint. The application clears RXRDY_TXKL. If the application does not know the size of the transfer, it may not be a good option to use AUTO_VALID. Because if a zero-length-packet is received, the RXRDY_TXKL is automatically cleared by the AUTO_VALID hardware and if the endpoint interrupt is triggered, the software will not find its originating flag when reading the UDPHS_EPTSTAx register.

Note:

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Algorithm to Fill Several Packets:z z

The application enables the interrupts of BUSY_BANK and AUTO_VALID. When a BUSY_BANK interrupt is received, the application knows that all banks available for the endpoint have been filled. Thus, the application can read all banks available.

If the application doesnt know the size of the receive buffer, instead of using the BUSY_BANK interrupt, the application must use RXRDY_TXKL. 32.6.10.12 Bulk OUT or Interrupt OUT: Sending a Buffer Using DMA (Host To Device) To use the DMA setting, the AUTO_VALID field is mandatory. See 32.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) for more information. DMA Configuration Example: 1. 2. 3. First program UDPHS_DMAADDRESSx with the address of the buffer that should be transferred. Enable the interrupt of the DMA in UDPHS_IEN Program the DMA Channelx Control Register:z z z z z

Size of buffer to be sent. END_B_EN: Can be used for OUT packet truncation (discarding of unbuffered packet data) at the end of DMA buffer. END_BUFFIT: Generate an interrupt when BUFF_COUNT in the UDPHS_DMASTATUSx register reaches 0. END_TR_EN: End of transfer enable, the UDPHS device can put an end to the current DMA transfer, in case of a short packet. END_TR_IT: End of transfer interrupt enable, an interrupt is sent after the last USB packet has been transferred by the DMA, if the USB transfer ended with a short packet. (Beneficial when the receive size is unknown.) CHANN_ENB: Run and stop at end of buffer.

z

For OUT transfer, the bank will be automatically cleared by hardware when the application has read all the bytes in the bank (the bank is empty). Notes: 1. 2. When a zero-length-packet is received, RXRDY_TXKL bit in UDPHS_EPTSTAx is cleared automatically by AUTO_VALID, and the application knows of the end of buffer by the presence of the END_TR_IT. If the host sends a zero-length packet, and the endpoint is free, then the device sends an ACK. No data is written in the endpoint, the RXRDY_TXKL interrupt is generated, and the BYTE_COUNT field in UDPHS_EPTSTAx is null.

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Figure 32-14. Data OUT Transfer for Endpoint with One BankHost Sends Data Payload Microcontroller Transfers Data Host Sends the Next Data Payload Host Resends the Next Data Payload

USB Bus Packets

Token OUT

Data OUT 1

ACK

Token OUT

Data OUT 2

NAK

Token OUT

Data OUT 2

ACK

RXRDY (UDPHS_EPTSTAx)

Interrupt Pending Set by Hardware Cleared by Firmware, Data Payload Written in FIFO Data OUT 2 Written by UDPHS Device

FIFO (DPR) Content

Data OUT 1 Written by UDPHS Device

Data OUT 1 Microcontroller Read

Figure 32-15. Data OUT Transfer for an Endpoint with Two BanksHost sends first data payload Microcontroller reads Data 1 in bank 0, Host sends second data payload Microcontroller reads Data 2 in bank 1, Host sends third data payload

USB Bus Packets

Token OUT

Data OUT 1

ACK

Token OUT

Data OUT 2

ACK

Token OUT

Data OUT 3

Virtual RXRDY Bank 0

Interrupt pending Set by Hardware, Data payload written in FIFO endpoint bank 0 Set by Hardware Data Payload written in FIFO endpoint bank 1

Cleared by Firmware

Cleared by Firmware Interrupt pending

Virtual RXRDY Bank 1 RXRDY = (virtual bank 0 | virtual bank 1) (UDPHS_EPTSTAx) FIFO (DPR) Bank 0 Data OUT 1 Write by UDPHS Device FIFO (DPR) Bank 1

Data OUT 1 Read by Microcontroller

Data OUT 3 Write in progress

Data OUT 2 Write by Hardware

Data OUT 2 Read by Microcontroller

32.6.10.13 High Bandwidth Isochronous Endpoint OUTFigure 32-16. Bank Management, Example of Three Transactions per Microframe

USB bus Transactions

MDATA0

MDATA1

DATA2

MDATA0

MDATA1

DATA2

t=0 RXRDY Microcontroller FIFO (DPR) Access

t = 52.5 s (40% of 125 s)

t = 125 s RXRDY

USB line

Read Bank 1

Read Bank 2

Read Bank 3

Read Bank 1

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USB 2.0 supports individual High Speed isochronous endpoints that require data rates up to 192 Mb/s (24 MB/s): 3x1024 data bytes per microframe. To support such a rate, two or three banks may be used to buffer the three consecutive data packets. The microcontroller (or the DMA) should be able to empty the banks very rapidly (at least 24 MB/s on average). NB_TRANS field in UDPHS_EPTCFGx register = Number Of Transactions per Microframe. If NB_TRANS > 1 then it is High Bandwidth. Example:z

If NB_TRANS = 3, the sequence should be eitherz z z

MData0 MData0/Data1 MData0/Data1/Data2 MData0 MData0/Data1 Data0

z

If NB_TRANS = 2, the sequence should be eitherz z

z

If NB_TRANS = 1, the sequence should bez

32.6.10.14 Isochronous Endpoint Handling: OUT Example The user can ascertain the bank status (free or busy), and the toggle sequencing of the data packet for each bank with the UDPHS_EPTSTAx register in the three bit fields as follows:z z z

TOGGLESQ_STA: PID of the data stored in the current bank CURBK: Number of the bank currently being accessed by the microcontroller. BUSY_BANK_STA: Number of busy bank

This is particularly useful in case of a missing data packet. If the inter-packet delay between the OUT token and the Data is greater than the USB standard, then the ISO-OUT transaction is ignored. (Payload data is not written, no interrupt is generated to the CPU.) If there is a data CRC (Cyclic Redundancy Check) error, the payload is, none the less, written in the endpoint. The ERR_CRC_NTR flag is set in UDPHS_EPTSTAx register. If the endpoint is already full, the packet is not written in the DPRAM. The ERR_FL_ISO flag is set in UDPHS_EPTSTAx. If the payload data is greater than the maximum size of the endpoint, then the ERR_OVFLW flag is set. It is the task of the CPU to manage this error. The data packet is written in the endpoint (except the extra data). If the host sends a Zero Length Packet, and the endpoint is free, no data is written in the endpoint, the RXRDY_TXKL flag is set, and the BYTE_COUNT field in UDPHS_EPTSTAx register is null. The FRCESTALL command bit is unused for an isochonous endpoint. Otherwise, payload data is written in the endpoint, the RXRDY_TXKL interrupt is generated and the BYTE_COUNT in UDPHS_EPTSTAx register is updated.

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32.6.10.15 STALL STALL is returned by a function in response to an IN token or after the data phase of an OUT or in response to a PING transaction. STALL indicates that a function is unable to transmit or receive data, or that a control pipe request is not supported.z

OUT

To stall an endpoint, set the FRCESTALL bit in UDPHS_EPTSETSTAx register and after the STALL_SNT flag has been set, set the TOGGLE_SEG bit in the UDPHS_EPTCLRSTAx register.z

IN

Set the FRCESTALL bit in UDPHS_EPTSETSTAx register.Figure 32-17. Stall Handshake Data OUT TransferUSB Bus Packets Token OUT Data OUT Stall PID

FRCESTALL Set by Firmware Cleared by Firmware Interrupt Pending

STALL_SNT Set by Hardware Cleared by Firmware

Figure 32-18. Stall Handshake Data IN TransferUSB Bus Packets

Token IN

Stall PID

FRCESTALL Set by Firmware Cleared by Firmware Interrupt Pending STALL_SNT Set by Hardware Cleared by Firmware

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32.6.11 Speed IdentificationThe high speed reset is managed by the hardware. At the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset. At the end of the reset process (full or high), the ENDRESET interrupt is generated. Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of the device.

32.6.12 USB V2.0 High Speed Global InterruptInterrupts are defined in Section 32.7.3 UDPHS Interrupt Enable Register (UDPHS_IEN) and in Section 32.7.4 UDPHS Interrupt Status Register (UDPHS_INTSTA).

32.6.13 Endpoint InterruptsInterrupts are enabled in UDPHS_IEN (see Section 32.7.3 UDPHS Interrupt Enable Register) and individually masked in UDPHS_EPTCTLENBx (see Section 32.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)).Table 32-5. Endpoint Interrupt Source Masks SHRT_PCKT BUSY_BANK NAK_OUT NAK_IN/ERR_FLUSH STALL_SNT/ERR_CRC_NTR RX_SETUP/ERR_FL_ISO TXRDY_TRER TX_COMPLT RXRDY_TXKL ERR_OVFLW MDATA_RX DATAX_RX Short Packet Interrupt Busy Bank Interrupt NAKOUT Interrupt NAKIN/Error Flush Interrupt Stall Sent/CRC error/Number of Transaction Error Interrupt Received SETUP/Error Flow Interrupt TX Packet Read/Transaction Error Interrupt Transmitted IN Data Complete Interrupt Received OUT Data Interrupt Overflow Error Interrupt MDATA Interrupt DATAx Interrupt

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Figure 32-19. UDPHS Interrupt Control Interface(UDPHS_IEN) DET_SUSPD MICRO_SOF USB Global IT Sources INT_SOF ENDRESET WAKE_UP ENDOFRSM UPSTR_RES Global IT mask Global IT sources

(UDPHS_EPTCTLENBx) SHRT_PCKT BUSY_BANK NAK_OUT NAK_IN/ERR_FLUSH STALL_SNT/ER_CRC_NTR EPT0 IT Sources RX_SETUP/ERR_FL_ISO TXRDY_TRER TX_COMPLT RXRDY_TXKL ERR_OVFLW MDATA_RX DATAX_RX EP mask EP sources (UDPHS_IEN) EPT_x EP sources EP mask (UDPHS_IEN) EPT_0 husb2dev interrupt

EPT1-6 IT Sources

(UDPHS_EPTCTLx) INTDIS_DMA disable DMA channelx request

(UDPHS_DMACONTROLx) EN_BUFFIT

mask (UDPHS_IEN) DMA_x mask

DMA CH x

END_TR_IT mask DESC_LD_IT

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32.6.14 Power Modes32.6.14.1 Controlling Device States A USB device has several possible states. Refer to Chapter 9 (USB Device Framework) of the Universal Serial Bus Specification, Rev 2.0.Figure 32-20. UDPHS Device State Diagram

Attached

Hub Reset Hub or Configured Deconfigured Bus Inactive Powered Bus Activity Power Interruption Reset Bus Inactive Default Reset Address Assigned Bus Inactive Address Bus Activity Device Deconfigured Device Configured Bus Inactive Suspended Bus Activity Suspended Bus Activity Suspended Suspended

Configured

Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 A on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake-up request to the host, e.g., waking up a PC by moving a USB mouse. The wake-up feature is not mandatory for all devices and must be negotiated with the host.

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32.6.14.2 Not Powered State Self powered devices can detect 5V VBUS using a PIO. When the device is not connected to a host, device power consumption can be reduced by the DETACH bit in UDPHS_CTRL. Disabling the transceiver is automatically done. HSDM, HSDP, FSDP and FSDP lines are tied to GND pull-downs integrated in the hub downstream ports. 32.6.14.3 Entering Attached State When no device is connected, the USB FSDP and FSDM signals are tied to GND by 15 K pull-downs integrated in the hub downstream ports. When a device is attached to an hub downstream port, the device connects a 1.5 K pull-up on FSDP. The USB bus line goes into IDLE state, FSDP is pulled-up by the device 1.5 K resistor to 3.3V and FSDM is pulled-down by the 15 K resistor to GND of the host. After pull-up connection, the device enters the powered state. The transceiver remains disabled until bus activity is detected. In case of low power consumption need, the device can be stopped. When the device detects the VBUS, the software must enable the USB transceiver by enabling the EN_UDPHS bit in UDPHS_CTRL register. The software can detach the pull-up by setting DETACH bit in UDPHS_CTRL register. 32.6.14.4 From Powered State to Default State (Reset) After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmasked flag ENDRESET is set in the UDPHS_IEN register and an interrupt is triggered. Once the ENDRESET interrupt has been triggered, the device enters Default State. In this state, the UDPHS software must:z

Enable the default endpoint, setting the EPT_ENABL flag in the UDPHS_EPTCTLENB[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 in EPT_0 of the UDPHS_IEN register. The enumeration then begins by a control transfer. Configure the Interrupt Mask Register which has been reset by the USB reset detection Enable the transceiver.

z z

In this state, the EN_UDPHS bit in UDPHS_CTRL register must be enabled. 32.6.14.5 From Default State to Address State (Address Assigned) After a Set Address standard device request, the USB host peripheral enters the address state. Warning: before the device enters address state, it must achieve the Status IN transaction of the control transfer, i.e., the UDPHS device sets its new address once the TX_COMPLT flag in the UDPHS_EPTCTL[0] register has been received and cleared. To move to address state, the driver software sets the DEV_ADDR field and the FADDR_EN flag in the UDPHS_CTRL register. 32.6.14.6 From Address State to Configured State (Device Configured) Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the BK_NUMBER, EPT_TYPE, EPT_DIR and EPT_SIZE fields in the UDPHS_EPTCFGx registers and enabling them by setting the EPT_ENABL flag in the UDPHS_EPTCTLENBx registers, and, optionally, enabling corresponding interrupts in the UDPHS_IEN register. 32.6.14.7 Entering Suspend State (Bus Activity) When a Suspend (no bus activity on the USB bus) is detected, the DET_SUSPD signal in the UDPHS_STA register is set. This triggers an interrupt if the corresponding bit is set in the UDPHS_IEN register. This flag is cleared by writing to the UDPHS_CLRINT register. Then the device enters Suspend Mode. In this state bus powered devices must drain less than 500 A from the 5V VBUS. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The UDPHS device peripheral clocks can be switched off. Resume event is asynchronously detected.

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32.6.14.8 Receiving a Host Resume In Suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks disabled (however the pull-up should not be removed). Once the resume is detected on the bus, the signal WAKE_UP in the UDPHS_INTSTA is set. It may generate an interrupt if the corresponding bit in the UDPHS_IEN register is set. This interrupt may be used to wake-up the core, enable PLL and main oscillators and configure clocks. 32.6.14.9 Sending an External Resume In Suspend State it is possible to wake-up the host by sending an external resume. The device waits at least 5 ms after being entered in Suspend State before sending an external resume. The device must force a K state from 1 to 15 ms to resume the host.

32.6.15 Test Mode A device must support the TEST_MODE feature when in the Default, Address or Configured High Speed device states. TEST_MODE can be: z Test_J z Test_K z Test_Packet z Test_SEO_NAK(See Section 32.7.7 UDPHS Test Register on page 781 for definitions of each test mode.) const char test_packet_buffer[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, 0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, 0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, JJJJJJJKKKKKKK * 8 0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD, 0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E 10}, JK };

// JKJKJKJK * 9 // JJKKJJKK * 8 // JJKKJJKK * 8 // // JJJJJJJK * 8 // {JKKKKKKK *

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32.7Offset0x00 0x04

USB High Speed Device Port (UDPHS) User InterfaceRegisterUDPHS Control Register UDPHS Frame Number Register Reserved UDPHS Interrupt Enable Register UDPHS Interrupt Status Register UDPHS Clear Interrupt Register UDPHS Endpoints Reset Register Reserved UDPHS Test Register Reserved UDPHS Endpoint Configuration Register UDPHS Endpoint Control Enable Register UDPHS Endpoint Control Disable Register UDPHS Endpoint Control Register Reserved (for endpoint) UDPHS Endpoint Set Status Register UDPHS Endpoint Clear Status Register UDPHS Endpoint Status Register UDPHS Endpoint1 to 15 (2) Registers UDPHS DMA Next Descriptor Address Register UDPHS DMA Channel Address Register UDPHS DMA Channel Control Register UDPHS DMA Channel Status Register DMA Channel1 to 6(3)

Table 32-6. Register Mapping NameUDPHS_CTRL UDPHS_FNUM UDPHS_IEN UDPHS_INTSTA UDPHS_CLRINT UDPHS_EPTRST UDPHS_TST UDPHS_EPTCFG UDPHS_EPTCTLENB UDPHS_EPTCTLDIS UDPHS_EPTCTL UDPHS_EPTSETSTA UDPHS_EPTCLRSTA UDPHS_EPTSTA

AccessRead-write Read-only Read-write Read-only Write-only Write-only Read-write Read-write Write-only Write-only Read-only Write-only Write-only Read-only

Reset0x0000_0200 0x0000_0000 0x0000_0010 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000(1) 0x0000_0040

0x08 - 0x0C 0x10 0x14 0x18 0x1C 0x20 - 0xCC 0xE0 0xE4 - 0xE8 0x100 + endpoint * 0x20 + 0x00 0x100 + endpoint * 0x20 + 0x04 0x100 + endpoint * 0x20 + 0x08 0x100 + endpoint * 0x20 + 0x0C 0x100 + endpoint * 0x20 + 0x10 0x100 + endpoint * 0x20 + 0x14 0x100 + endpoint * 0x20 + 0x18 0x100 + endpoint * 0x20 + 0x1C 0x120 - 0x2FC 0x300 + channel * 0x10 + 0x00 0x300 + channel * 0x10 + 0x04 0x300 + channel * 0x10 + 0x08 0x300 + channel * 0x10 + 0x0C 0x310 - 0x36C

UDPHS_DMANXTDSC UDPHS_DMAADDRESS UDPHS_DMACONTROL UDPHS_DMASTATUS

Read-write Read-write Read-write Read-write

0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000

Registers

Notes: 1. The reset value for UDPHS_EPTCTL0 is 0x0000_0001. 2. The addresses for the UDPHS Endpoint registers shown here are for UDPHS Endpoint0. The structure of this group of registers is repeated successively for each endpoint according to the consecution of endpoint registers located between 0x120 and 0x2FC. 3. The DMA channel index refers to the corresponding EP number. When no DMA channel is assigned to one EP, the associated registers are reserved. This is the case for EP0, so DMA Channel 0 registers are reserved.

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32.7.1 UDPHS Control RegisterName: Address: Access:31 23 15 7 FADDR_EN

UDPHS_CTRL 0xF8030000 Read-write30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 PULLD_DIS 3 DEV_ADDR 26 18 10 REWAKEUP 2 25 17 9 DETACH 1 24 16 8 EN_UDPHS 0

DEV_ADDR: UDPHS AddressThis field contains the default address (0) after power-up or UDPHS bus reset (read), or it is written with the value set by a SET_ADDRESS request received by the device firmware (write).

FADDR_EN: Function Address Enable0 = Device is not in address state (read), or only the default function address is used (write). 1 = Device is in address state (read), or this bit is set by the device firmware after a successful status phase of a SET_ADDRESS transaction (write). When set, the only address accepted by the UDPHS controller is the one stored in the UDPHS Address field. It will not be cleared afterwards by the device firmware. It is cleared by hardware on hardware reset, or when UDPHS bus reset is received.

EN_UDPHS: UDPHS Enable0 = UDPHS is disabled (read), or this bit disables and resets the UDPHS controller (write). Switch the host to UTMI. 1 = UDPHS is enabled (read), or this bit enables the UDPHS controller (write). Switch the host to UTMI.

DETACH: Detach Command0 = UDPHS is attached (read), or this bit pulls up the DP line (attach command) (write). 1 = UDPHS is detached, UTMI transceiver is suspended (read), or this bit simulates a detach on the UDPHS line and forces the UTMI transceiver into suspend state (Suspend M = 0) (write). See PULLD_DIS description below.

REWAKEUP: Send Remote Wake Up0 = Remote Wake Up is disabled (read), or this bit has no effect (write). 1 = Remote Wake Up is enabled (read), or this bit forces an external interrupt on the UDPHS controller for Remote Wake UP purposes. An Upstream Resume is sent only after the UDPHS bus has been in SUSPEND state for at least 5 ms. This bit is automatically cleared by hardware at the end of the Upstream Resume.

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PULLD_DIS: Pull-Down DisableWhen set, there is no pull-down on DP & DM. (DM Pull-Down = DP Pull-Down = 0). Note: If the DETACH bit is also set, device DP & DM are left in high impedance state. (See DETACH description above.)DETACH 0 0 1 1 PULLD_DIS 0 1 0 1 DP Pull up Pull up Pull down High impedance state DM Pull down High impedance state Pull down High impedance state Condition Not recommended VBUS present No VBUS VBUS present & software disconnect

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32.7.2 UDPHS Frame Number RegisterName: Address: Access:31 FNUM_ERR 23 15 7

UDPHS_FNUM 0xF8030004 Read-only30 22 14 6 29 21 13 28 20 12 27 19 26 18 25 17 9 24 16 8

11 10 FRAME_NUMBER 3 2

5 FRAME_NUMBER

4

1 MICRO_FRAME_NUM

0

MICRO_FRAME_NUM: Microframe NumberNumber of the received microframe (0 to 7) in one frame.This field is reset at the beginning of each new frame (1 ms). One microframe is received each 125 microseconds (1 ms/8).

FRAME_NUMBER: Frame Number as defined in the Packet Field FormatsThis field is provided in the last received SOF packet (see INT_SOF in the UDPHS Interrupt Status Register).

FNUM_ERR: Frame Number CRC ErrorThis bit is set by hardware when a corrupted Frame Number in Start of Frame packet (or Micro SOF) is received. This bit and the INT_SOF (or MICRO_SOF) interrupt are updated at the same time.

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32.7.3 UDPHS Interrupt Enable RegisterName: Address: Access:31 DMA_7 23 EPT_15 15 EPT_7 7 UPSTR_RES

UDPHS_IEN 0xF8030010 Read-write30 DMA_6 22 EPT_14 14 EPT_6 6 ENDOFRSM 29 DMA_5 21 EPT_13 13 EPT_5 5 WAKE_UP 28 DMA_4 20 EPT_12 12 EPT_4 4 ENDRESET 27 DMA_3 19 EPT_11 11 EPT_3 3 INT_SOF 26 DMA_2 18 EPT_10 10 EPT_2 2 MICRO_SOF 25 DMA_1 17 EPT_9 9 EPT_1 1 DET_SUSPD 24 16 EPT_8 8 EPT_0 0

DET_SUSPD: Suspend Interrupt Enable 0 = Disable Suspend Interrupt. 1 = Enable Suspend Interrupt. MICRO_SOF: Micro-SOF Interrupt Enable 0 = Disable Micro-SOF Interrupt. 1 = Enable Micro-SOF Interrupt. INT_SOF: SOF Interrupt Enable 0 = Disable SOF Interrupt. 1 = Enable SOF Interrupt. ENDRESET: End Of Reset Interrupt Enable 0 = Disable End Of Reset Interrupt. 1 = Enable End Of Reset Interrupt. Automatically enabled after USB reset. WAKE_UP: Wake Up CPU Interrupt Enable 0 = Disable Wake Up CPU Interrupt. 1 = Enable Wake Up CPU Interrupt. ENDOFRSM: End Of Resume Interrupt Enable 0 = Disable Resume Interrupt. 1 = Enable Resume Interrupt. UPSTR_RES: Upstream Resume Interrupt Enable 0 = Disable Upstream Resume Interrupt. 1 = Enable Upstream Resume Interrupt. EPT_x: Endpoint x Interrupt Enable 0 = Disable the interrupts for this endpoint. 1 = Enable the interrupts for this endpoint. DMA_x: DMA Channel x Interrupt Enable 0 = Disable the interrupts for this channel. 1 = Enable the interrupts for this channel. SAMA5D3 Series [DATASHEET]11121BATARM08-Mar-13

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32.7.4 UDPHS Interrupt Status RegisterName: Address: Access:31 DMA_7 23 EPT_15 15 EPT_7 7 UPSTR_RES

UDPHS_INTSTA 0xF8030014 Read-only30 DMA_6 22 EPT_14 14 EPT_6 6 ENDOFRSM 29 DMA_5 21 EPT_13 13 EPT_5 5 WAKE_UP 28 DMA_4 20 EPT_12 12 EPT_4 4 ENDRESET 27 DMA_3 19 EPT_11 11 EPT_3 3 INT_SOF 26 DMA_2 18 EPT_10 10 EPT_2 2 MICRO_SOF 25 DMA_1 17 EPT_9 9 EPT_1 1 DET_SUSPD 24 16 EPT_8 8 EPT_0 0 SPEED

SPEED: Speed Status0 = Reset by hardware when the hardware is in Full Speed mode. 1 = Set by hardware when the hardware is in High Speed mode

DET_SUSPD: Suspend Interrupt0 = Cleared by setting the DET_SUSPD bit in UDPHS_CLRINT register 1 = Set by hardware when a UDPHS Suspend (Idle bus for three frame periods, a J state for 3 ms) is detected. This triggers a UDPHS interrupt when the DET_SUSPD bit is set in UDPHS_IEN register.

MICRO_SOF: Micro Start Of Frame Interrupt0 = Cleared by setting the MICRO_SOF bit in UDPHS_CLRINT register. 1 = Set by hardware when an UDPHS micro start of frame PID (SOF) has been detected (every 125 us) or synthesized by the macro. This triggers a UDPHS interrupt when the MICRO_SOF bit is set in UDPHS_IEN. In case of detected SOF, the MICRO_FRAME_NUM field in UDPHS_FNUM register is incremented and the FRAME_NUMBER field doesnt change. Note: The Micro Start Of Frame Interrupt (MICRO_SOF), and the Start Of Frame Interrupt (INT_SOF) are not generated at the same time.

INT_SOF: Start Of Frame Interrupt0 = Cleared by setting the INT_SOF bit in UDPHS_CLRINT. 1 = Set by hardware when an UDPHS Start Of Frame PID (SOF) has been detected (every 1 ms) or synthesized by the macro. This triggers a UDPHS interrupt when the INT_SOF bit is set in UDPHS_IEN register. In case of detected SOF, in High Speed mode, the MICRO_FRAME_NUMBER field is cleared in UDPHS_FNUM register and the FRAME_NUMBER field is updated.

ENDRESET: End Of Reset Interrupt0 = Cleared by setting the ENDRESET bit in UDPHS_CLRINT. 1 = Set by hardware when an End Of Reset has been detected by the UDPHS controller. This triggers a UDPHS interrupt when the ENDRESET bit is set in UDPHS_IEN.

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WAKE_UP: Wake Up CPU Interrupt0 = Cleared by setting the WAKE_UP bit in UDPHS_CLRINT. 1 = Set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered non-idle signal from the UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when the WAKE_UP bit is set in UDPHS_IEN register. When receiving this interrupt, the user has to enable the device controller clock prior to operation. Note: This interrupt is generated even if the device controller clock is disabled.

ENDOFRSM: End Of Resume Interrupt0 = Cleared by setting the ENDOFRSM bit in UDPHS_CLRINT. 1 = Set by hardware when the UDPHS controller detects a good end of resume signal initiated by the host. This triggers a UDPHS interrupt when the ENDOFRSM bit is set in UDPHS_IEN.

UPSTR_RES: Upstream Resume Interrupt0 = Cleared by setting the UPSTR_RES bit in UDPHS_CLRINT. 1 = Set by hardware when the UDPHS controller is sending a resume signal called upstream resume. This triggers a UDPHS interrupt when the UPSTR_RES bit is set in UDPHS_IEN.

EPT_x: Endpoint x Interrupt0 = Reset when the UDPHS_EPTSTAx interrupt source is cleared. 1 = Set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN.

DMA_x: DMA Channel x Interrupt0 = Reset when the UDPHS_DMASTATUSx interrupt source is cleared. 1 = Set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN.

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32.7.5 UDPHS Clear Interrupt RegisterName: Address: Access:31 23 15 7 UPSTR_RES

UDPHS_CLRINT 0xF8030018 Write only30 22 14 6 ENDOFRSM 29 21 13 5 WAKE_UP 28 20 12 4 ENDRESET 27 19 11 3 INT_SOF 26 18 10 2 MICRO_SOF 25 17 9 1 DET_SUSPD 24 16 8 0

DET_SUSPD: Suspend Interrupt Clear0 = No effect. 1 = Clear the DET_SUSPD bit in UDPHS_INTSTA.

MICRO_SOF: Micro Start Of Frame Interrupt Clear0 = No effect. 1 = Clear the MICRO_SOF bit in UDPHS_INTSTA.

INT_SOF: Start Of Frame Interrupt Clear0 = No effect. 1 = Clear the INT_SOF bit in UDPHS_INTSTA.

ENDRESET: End Of Reset Interrupt Clear0 = No effect. 1 = Clear the ENDRESET bit in UDPHS_INTSTA.

WAKE_UP: Wake Up CPU Interrupt Clear0 = No effect. 1 = Clear the WAKE_UP bit in UDPHS_INTSTA.

ENDOFRSM: End Of Resume Interrupt Clear0 = No effect. 1 = Clear the ENDOFRSM bit in UDPHS_INTSTA.

UPSTR_RES: Upstream Resume Interrupt Clear0 = No effect. 1 = Clear the UPSTR_RES bit in UDPHS_INTSTA.

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32.7.6 UDPHS Endpoints Reset RegisterName: Address: Access:31 23 15 EPT_15 7 EPT_7

UDPHS_EPTRST 0xF803001C Write only30 22 14 EPT_14 6 EPT_6 29 21 13 EPT_13 5 EPT_5 28 20 12 EPT_12 4 EPT_4 27 19 11 EPT_11 3 EPT_3 26 18 10 EPT_10 2 EPT_2 25 17 9 EPT_9 1 EPT_1 24 16 8 EPT_8 0 EPT_0

EPT_x: Endpoint x Reset0 = No effect. 1 = Reset the Endpointx state. Setting this bit clears the Endpoint status UDPHS_EPTSTAx register, except for the TOGGLESQ_STA field.

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32.7.7 UDPHS Test RegisterName: Address: Access:31 23 15 7

UDPHS_TST 0xF80300E0 Read-write30 22 14 6 29 21 13 5 OPMODE2 28 20 12 4 TST_PKT 27 19 11 3 TST_K 26 18 10 2 TST_J 25 17 9 1 SPEED_CFG 24 16 8 0

SPEED_CFG: Speed ConfigurationSpeed Configuration:Value 0 1 2 3 HIGH_SPEED FULL_SPEED Name NORMAL Description Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode Reserved Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake.

TST_J: Test J Mode0 = No effect. 1 = Set to send the J state on the UDPHS line. This enables the testing of the high output drive level on the D+ line.

TST_K: Test K Mode0 = No effect. 1 = Set to send the K state on the UDPHS line. This enables the testing of the high output drive level on the D- line.

TST_PKT: Test Packet Mode0 = No effect. 1 = Set to repetitively transmit the packet stored in the current bank. This enables the testing of rise and fall times, eye patterns, jitter, and any other dynamic waveform specifications.

OPMODE2: OpMode20 = No effect. 1 = Set to force the OpMode signal (UTMI interface) to 10, to disable the bit-stuffing and the NRZI encoding. Note: For the Test mode, Test_SE0_NAK (see Universal Serial Bus Specification, Revision 2.0: 7.1.20, Test Mode Support). Force the device in High Speed mode, and configure a bulk-type endpoint. Do not fill this endpoint for sending NAK to the host.

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Upon command, a ports transceiver must enter the High Speed receive mode and remain in that mode until the exit action is taken. This enables the testing of output impedance, low level output voltage and loading characteristics. In addition, while in this mode, upstream facing ports (and only upstream facing ports) must respond to any IN token packet with a NAK handshake (only if the packet CRC is determined to be correct) within the normal allowed device response time. This enables testing of the device squelch level circuitry and, additionally, provides a general purpose stimulus/response test for basic functional testing.

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32.7.8 UDPHS Endpoint Configuration RegisterName: Address: UDPHS_EPTCFGx [x=0..15] 0xF8030100 [0], 0xF8030120 [1], 0xF8030140 [2], 0xF8030160 [3], 0xF8030180 [4], 0xF80301A0 [5], 0xF80301C0 [6], 0xF80301E0 [7], 0xF8030200 [8], 0xF8030220 [9], 0xF8030240 [10], 0xF8030260 [11], 0xF8030280 [12], 0xF80302A0 [13], 0xF80302C0 [14], 0xF80302E0 [15] Read-write30 22 14 6 BK_NUMBER 29 21 13 5 EPT_TYPE 28 20 12 4 27 19 11 3 EPT_DIR 26 18 10 2 25 17 9 NB_TRANS 1 EPT_SIZE 0 24 16 8

Access:31 EPT_MAPD 23 15 7

EPT_SIZE: Endpoint SizeSet this field according to the endpoint size in bytes (see Section 32.6.6 Endpoint Configuration). Endpoint Size (1)Value 0 1 2 3 4 5 6 7 Name 8 16 32 64 128 256 512 1024 Description 8 bytes 16 bytes 32 bytes 64 bytes 128 bytes 256 bytes 512 bytes 1024 bytes

Note:

1. 1024 bytes is only for isochronous endpoint.

EPT_DIR: Endpoint Direction0 = Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. 1 = Set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. For Control endpoints this bit has no effect and should be left at zero.

EPT_TYPE: Endpoint TypeSet this field according to the endpoint type (see Section 32.6.6 Endpoint Configuration). (Endpoint 0 should always be configured as control)

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Endpoint TypeValue 0 1 2 3 Name CTRL8 ISO BULK INT Description Control endpoint Isochronous endpoint Bulk endpoint Interrupt endpoint

BK_NUMBER: Number of BanksSet this field according to the endpoints number of banks (see Section 32.6.6 Endpoint Configuration). Number of BanksValue 0 1 2 3 Name 0 1 2 3 Description Zero bank, the endpoint is not mapped in memory One bank (bank 0) Double bank (Ping-Pong: bank0/bank1) Triple bank (bank0/bank1/bank2)

NB_TRANS: Number Of Transaction per MicroframeThe Number of transactions per microframe is set by software. Note: Meaningful for high bandwidth isochronous endpoint only.

EPT_MAPD: Endpoint Mapped0 = The user should reprogram the register with correct values. 1 = Set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:

The fifo max capacity (FIFO_MAX_SIZE in UDPHS_IPFEATURES register) The number of endpoints/banks already allocated The number of allowed banks for this endpoint

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32.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)Name: Access:31 SHRT_PCKT 23 15 NAK_OUT 7

UDPHS_EPTCTLENBx [x=0..15] Write-only30 22 14 NAK_IN 6 29 21 13 STALL_SNT 5 28 20 12 RX_SETUP 4 NYET_DIS 27 19 11 TXRDY 3 INTDIS_DMA 26 18 BUSY_BANK 10 TX_COMPLT 2 25 17 9 RXRDY_TXKL 1 AUTO_VALID 24 16 8 ERR_OVFLW 0 EPT_ENABL

This register view is relevant only if EPT_TYPE=0x0, 0x2 or 0x3 in UDPHS Endpoint Configuration Register on page 783 For additional Information, see UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints) on page 793.

EPT_ENABL: Endpoint Enable0 = No effect. 1 = Enable endpoint according to the device configuration.

AUTO_VALID: Packet Auto-Valid Enable0 = No effect. 1 = Enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers.

INTDIS_DMA: Interrupts Disable DMA0 = No effect. 1 = If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.

NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)0 = No effect. 1 = Forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.

ERR_OVFLW: Overflow Error Interrupt Enable0 = No effect. 1 = Enable Overflow Error Interrupt.

RXRDY_TXKL: Received OUT Data Interrupt Enable0 = No effect. 1 = Enable Received OUT Data Interrupt.

TX_COMPLT: Transmitted IN Data Complete Interrupt Enable0 = No effect. 1 = Enable Transmitted IN Data Complete Interrupt.

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TXRDY: TX Packet Ready Interrupt Enable0 = No effect. 1 = Enable TX Packet Ready/Transaction Error Interrupt.

RX_SETUP: Received SETUP0 = No effect. 1 = Enable RX_SETUP Interrupt.

STA