Atmel 11269 32 Bit Cortex A5 Microcontroller SAMA5D3 Xplained User Guide

ARM-based Embedded MPUs

SAMA5D3 Xplained

USER GUIDE

Introduction

This user guide introduces the Atmel® SAMA5D3 Xplained evaluation kit and describes the development and debugging capabilities for applications running on a SAMA5D36 ARM®-based embedded microprocessor unit (eMPU).

SAMA5D

3XPLAINE

D

11269A–ATARM–20-Feb-14

Scope

This guide provides details on the SAMA5D3 Xplained evaluation kit. It is made up of four main sections: Section 1. describes the evaluation kit content and its main features. Section 2. provides instructions to power up the SAMA5D3 Xplained board. Section 3. provides an overview of the SAMA5D3 Xplained board. Section 4. describes the SAMA5D3 Xplained board components.

Contents

Boards One SAMA5D3 Xplained board

Cables One micro-AB type USB cable

A welcome letter

Related Items

Atmel SAMA5D3 Series Datasheet SAMA5D3 Xplained Getting Started

2SAMA5D3 Xplained User Guide [USER GUIDE]11269A–ATARM–20-Feb-14

http://www.atmel.com/products/microcontrollers/arm/sama5d3.aspx?tab=documents

http://www.atmel.com/Images/Atmel_11270_32-bit-Cortex-SAMA5D3-Microcontroller_SAMA5D3-Xplained_Getting-Started.pdf


Table of Contents

1. Evaluation Kit Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.1 Electrostatic Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2 Power Supply Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2. Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1 Power up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.2 Sample Code and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3. Hardware Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.2 Equipment List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.3 Board features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4. Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84.1 Board Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84.2 Function Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94.3 Other Connector Details and PIO Usage Summary . . . . . . . . . . . . . . . . . . . . 344.4 SAMA5D3 Xplained Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59


1. Evaluation Kit Specifications

1.1 Electrostatic WarningWarning: ESD-Sensitive Electronic Equipment!

The evaluation kit is shipped in a protective anti-static package. The board system must not be subject to high electrostatic potentials.

We strongly recommend using a grounding strap or similar ESD protective device when handling the board in hostile ESD environments (offices with synthetic carpet, for example). Avoid touching the component pins or any other metallic element on the board.

1.2 Power Supply WarningWarning: Hardware Power Supply Limitation

Using a power adapter greater than 5Vcc (e.g. the 12Vcc power adapters from other kits such as Arduino kits) may damage the board.

Warning:Hardware Power Budget

Using the USB as the main power source (max. 500 mA) is acceptable only with the use of the on-board peripherals and low-power LCD extension.

When external peripheral or add-on boards need to be powered, we recommend the use of an external power adapter connected to a J2 DC Jack (can provide up to 1.2A on the 3.3V node).

Table 1-1. Evaluation Kit Specifications

Characteristic Specifications

Temperature:

- Operating

- Storage

0°C to +70°C

-40°C to +85°C

Relative Humidity 0 to 90% (non-condensing)

RoHS status Compliant

Ordering code ATSAMA5D3-XPLD

Electrostaticsensitivedevice


2. Power UpSeveral power source options are available to power up the SAMA5D3 Xplained board.

The board can be: USB-powered through the USB Micro-AB connector (J6 connector - default configuration) Powered through an external AC-to-DC adapter connected via a 2.1 mm center-positive plug into the optional

power jack of the board. The recommended output voltage range of the power adapter is 5V at 2A. Powered through the Arduino shield.

Warning: Unlike Arduino Uno boards, the SAMA5D3 Xplained board runs at 3.3V. The maximum voltage that the I/O pins can tolerate is 3.3V. Providing higher voltages (e.g. 5V) to an I/O pin could damage the board.

2.1 Power up the BoardUnpack the board, taking care to avoid electrostatic discharge. Simply connect the USB Micro-AB cable to the connector (J6).Then, connect the other end of the cable to a free USB port of your PC.

2.2 Sample Code and Technical SupportAfter booting up the board, you can run sample code or your own application on the board. You can download sample code and get technical support from the Atmel website.

Linux software and demos can be found on the website Linux4SAM.

Table 2-1. Electrical Characteristics

Electrical Parameter Values

Input voltage 5 VCC

Maximum input voltage 6 VCC

Max DC 3.3V current available 1.2A

I/O Voltage 3.3V only

http://www.atmel.com/

http://www.at91.com/linux4sam/bin/view/Linux4SAM/

3. Hardware Introduction

3.1 IntroductionThe Atmel SAMA5D3 Xplained board is a fully-featured evaluation platform for Atmel SAMA5D3 series microcontrollers. It allows users to extensively evaluate, prototype and create application-specific designs.

3.2 Equipment ListThe SAMA5D3 Xplained board is built around the integration of a Cortex®-A5-based microcontroller (BGA 324 package) with external memory, dual Ethernet physical layer transceiver, two SD/MMC interfaces, two host USB ports and one device USB port, one 24-bit RGB LCD interface and one debug interface. Seven headers, compatible with Arduino R3, are available for various shield connections.


3.3 Board features

Table 3-1. Board Specifications

Characteristics Specifications

PCB characteristics 125 x 75 x 20mm (10-layers)

Processor SAMA5D36 (324-ball BGA package) ARM Cortex-A5 Processor with ARM v7-A Thumb2® instruction set, core frequency up to 536 MHz.

Processor clock sources12-MHz crystal oscillator

32.768-kHz crystal oscillator

Memory2x 1Gb DDR2 (16M x 16 bits x 8 banks)

1x 2Gb SLC NAND Flash (256M x 8 bits)

Optional on-board memoryOne Serial EEPROM SPI

One 1-Wire EEPROM

SD/MMCOne 8-bit SD card connector

One optional 4-bit Micro-SD card connector

USBTwo USB Hosts with power switch

One Micro-AB USB device

Display interface One LCD interface connector, LCD TFT Controller with overlay, alpha-blending, rotation, scaling and color space conversion

EthernetOne Gigabit Ethernet PHY (GRMII 10/100/1000)

One Ethernet PHY (RMII 10/100)

Debug portOne JTAG interface connector

One serial DBGU interface (3.3V level)

Expansion connectorsArduino R3 compatible set of headers

The SAMA5D36 GPIO,TWI, SPI, USART, UART, Audio and ISI interfaces are accessible through these headers.

Board supply voltage5V from USB or power jack or Arduino shield

On-board power regulation is performed by a Power Management Unit (PMU)

Battery On-board optional power Cap for CMOS backup

User interfaceReset, wakeup and free user pushbutton

One red user/power LED and one blue user LED


4. Board Components

4.1 Board OverviewThe full-featured SAMA5D3 Xplained board integrates several peripherals and interface connectors, as shown in Figure 4-1.

Figure 4-1. SAMA5D3 Xplained Board Overview

ATSAMA5D36 CU

1401 AXXXXXXXXXX ARM

J15 PIO Expansion

1Gb DDR2 Memory

1Gb DDR2 Memory

2Gb Nand Flash Memory

System Buttons

JTAG Interface

LCD Connector

Ethernet 10/100

GigaBit Ethernet

J18 PIO Expansion

Free User Push Button

ADC Inputs and CAN Interfaces

Debug Interface

SAMA5D36

Voltages and Reset Interface

ADC Inputs Expansion

Optional Supply Input

USB A DeviceSupply Input

SPI Interface

J20 PIO Expansion

J19 PIO Expansion

XX

USB Host Interfaces

ectorA

t


The SAMA5D3 Xplained board is equipped with the following interface connectors: J2: Main power supply J6: USB A device, that supports USB device using a Micro-AB connector J7 (upper): USB B Host, that supports USB host using a type A connector J7 (lower): USB C Host, that supports USB host using a type A connector J23: Serial DBGU 3.3V level J24: JTAG, 20-pin IDC connector J11: Micro-SD connector J10: SD/MMC connector J12: Gigabit Ethernet ETH0 J13: Ethernet ETH1 J22: Expansion connector with all LCD controller signals for display module connection (QTouch®, TFT LCD

display with Touch Screen and backlight C41: Optional SuperCap J14 to J21: Seven expansion connectors with Arduino R3 compatible PIO signals Various test points located throughout the board

4.2 Function Blocks

Figure 4-2. Evaluation Kit Architecture

JTAGDBGU

JTAG & DBGU

SERIALDATAMicro SD

CARD

10/100/1000FAST ETHERNET

10/100ETHERNETSD

CARDLCD

Connector FLASH ETH0 ETH1

PIO A,...EPIO A,...E

SinglePMU

Solution5V INPUT

ATMEL

SAMA5D36

CORTEX-A5 PROCESSOR 2GbDDR2

SDRAM

2GbNANDFLASH

USBDEVICE

USBHostx2

ANALOG Reference

VBAT

USERLEDS

PIO

Exp

ansio

n H

eaders

Power rails

USB A,B,C

ResetForce PwrOn

PushButtons

EBI

5V & 3V3

(Up to 4Gb)

(Up to 4Gb)


4.2.1 Processor

The SAMA5D3 Xplained board is built around the SAMA5D36, a Cortex-A5 application processor which combines high-performance computing device with low-power consumption and a wide range of communication peripherals. It features a combination of user interface functionalities and high data rate IOs, including LCD controller, touchscreen, camera interface, Gigabit and 10/100 Ethernet ports, high-speed USB and SDIO.

The ARM Cortex-A5 supports the latest generation of DDR2 and NAND Flash memory interfaces for program and data storage. An internal 166-MHz multi-layer bus architecture associated with 24 DMA channels and two 64-Kbyte SRAM blocks, sustains the high bandwidth required by the processor and the high-speed peripherals.

4.2.2 Clock Circuitry

The SAMA5D3 Xplained evaluation board features four clock sources: Two clocks are alternatives for the SAMA5D3 series processor main clock Two crystal oscillators are used for the GETH and Ethernet MII/RMII chip

4.2.3 Power Supplies

The on-board power supply generation is based on the Active-Semi® Power Management Unit (PMU) featuring a 3-channel (3.3V / 1.8V /1.2V or 1.0V) topology. For a maximum efficiency, these supply channels are generated by three integrated step-down converters.

In addition to these 3 DCDC channels, 4 LDO channels with low noise and high PSRR performance are available for the application. These channels are disabled at startup by default and can be turned on and adjusted under software control through an I²C link. They are also used to supply the 2.5V VDDFUSE and the 3.3V VDDANA power inputs of the processor.

The power supply sequencing of the three primary channels is controlled by the PMU itself in perfect compliance with the SAMAD3 requirements. The turn-on sequence is: 3.3V first, then 1.8V and finally 1.2V.

Table 4-2 summarizes the power specifications.

Table 4-1. Main Components Associated with the Clock Systems

Quantity Description Component Assignment

1 Crystal for internal clock, 12 MHz Y1

1 Crystal for RTC clock, 32.768 kHz Y2

1 Oscillator for ethernet clock RGMII, 25 MHz Y3

1 Oscillator for ethernet clock RMII, 25 MHz Y4

Table 4-2. Supply Group Configuration

Nominal Name Power domains Power source

3.0V VDDBUThe slow clock oscillator, the internal 32K RC, the internal 12M RC and a part of the system controller

Optional on-board battery

3.3V VDDIOP0 A part of peripheral I/O lines

PMU

3.3V VDDIOP1 A part of peripheral I/O lines

3.3V VDDUTMII The three USB interfaces

3.3V VDDOSC The main oscillator cells

3.3V VDDANA The analog-to-digital converter

1.2V VDDCORE The core, including the processor, the embedded memories and the peripherals


Note: Jumper footprints are available on board to measure power consumption on main power lines. By default, the jumpers are not implemented. They are short-circuited by a thin PCB wire. To use this functionality, open the short circuit and mount a 2-pin jumper.

Figure 4-3. Board Power Management Schematic

1.2V VDDUTMIC The USB UTMI + core

PMU1.2V VDDPLLA The PLLA cell

1.8V VDDIODDR DDR2 interface I/O lines

1.8V VDDIOM NAND, NOR Flash and SMC interface I/O lines

3.0V to

3.3VADVREF ADC reference voltage J15 header

2.5V VDDFUSE Fuse box for programming PMU

Table 4-2. Supply Group Configuration (Continued)

Nominal Name Power domains Power source

BP

2

BP

1

5V_MAIN

VDDCORE

VDDIOP1

VDDIOP0

VDDANA

VDDPLLA

VDDOSC

VDDIODDR

VDDIOM

AVDDL_PLL

DVDDL

AVDDL

FUSE_2V5

5V_MAIN

3V3

3V3

VDDUTMIC

3V3

TWCK_PMIC[7]TWD_PMIC[7]

NRST[5,9,10,11]

SHDN[5]

PC31[7]

WKUP[5]PE30[7] (1V2)

(1V8)

(3V3)

(3V3)

(2V5)

RESETWAKUP orForce Power ON

AutoPWRON(option)

PC27PC26

C10100nFC10100nF

L9 2.2uHL9 2.2uH

R14

50K

R14

50K

C212.2uFC212.2uF

BP2BP2

C41uFC41uF

C1310uFC1310uF

R16 0RR16 0R

C232.2uFC232.2uF

R17 2R2R17 2R2

C20100nFC20100nF

MN1 ACT8865MN1 ACT8865

GN

DP

12

9

GN

DA

2

INL45 5VP131

INL67 6

GN

DP

22

8

VP226

GN

DP

31

4

EX

PA

D3

3

VP316

NC225

VDDREF23

nRST011

nIRQ12

nPBSTAT13

VSEL20

NC118

PWRHLD10

PWREN17

SCL21

SDA22

REFBP32

nPBIN9

SW1 30

OUT1 1

OUT2 24SW2 27

SW3 15

OUT3 19

OUT4 3

OUT5 4

OUT6 7

OUT7 8

C24.7uFC24.7uF

JP1 DNP(JUMPER)JP1 DNP(JUMPER)

1 2

Q1

IRLML2502

Q1

IRLML2502

1

3

2

C51uFC51uF

R19

100K 1%

R19

100K 1%

C14.7uFC14.7uF

R15

0R

R15

0R

L11180ohm at 100MHz

L11180ohm at 100MHz

1 2

L8180ohm at 100MHz

L8180ohm at 100MHz

1 2

C1847nFC1847nF

C222.2uFC222.2uF


1 2

R11 0RR11 0R

TP2SMD

TP2SMD

C264.7uFC264.7uF

C6

1uF

C6

1uF

R61.5K 1%

R61.5K 1%

L5 2.2uHL5 2.2uH


1 2

C25100nF

C25100nF

L6

10uH60mA

L6

10uH60mA

C34.7uFC34.7uF


1 2

R71.5K 1%R7

1.5K 1%

C114.7uFC114.7uF

R5 2R2R5 2R2

R810KR810K

R41RR41R

C17100nFC17100nF

C910uFC910uF

L7 2.2uHL7 2.2uH

C19100nF

C19100nF

L12

10uH60mA

L12

10uH60mA

C74.7uFC74.7uF

R186 0RR186 0R

L3180ohm at 100MHz

L3180ohm at 100MHz

1 2

L1180ohm at 100MHz

L1180ohm at 100MHz

1 2

R12 49.9K

L10180ohm at 100MHz

L10180ohm at 100MHz

1 2

C1510uFC1510uF

TP1SMD

TP1SMD

C14100nFC14100nFR18 1KR18 1K

C13010nFC13010nF

C1610uFC1610uF

C810uFC810uF

R9 DNP(0R)R9 DNP(0R)

C242.2uFC242.2uF

R13 0RR13 0R

R10 2R2R10 2R2

L4

10uH60mA

L4

10uH60mA

L2180ohm at 100MHz

L2180ohm at 100MHz

1 2

BP1BP1

C1210uFC1210uF


4.2.3.1 Power OptionsSeveral power options are available to configure the SAMA5D3 Xplained board powering scheme.

The power sources are selected by a set of 0R resistors.

The USB-powered operation is the default configuration. The power source is the USB device port (J6) connected to a PC or a mini-AB 5V DC supply. The USB supply is sufficient to power the board in most applications if USB host ports are not used. If USB host ports are used, it is recommended to use a DC supply source.

Schematic diagrams of various power options are illustrated in Figure 4-4.

Figure 4-4. Input Powering Scheme Option Schematic

Note: USB-powered operation is a good “single cable” solution because it combines powering and board control through a unique cable. Consequently, it eliminates the need for other wires and batteries. This power option is suitable for most projects that only require 5 volts at up to 500 mA.

4.2.3.2 Mains Power AdapterA mains power supply adapter can be used to provide power to the board. A regulated 5V DC supply of typically 2A is required but a current range of 3A is recommended if the USB ports and expansion headers are likely to be used. It needs a 2.1 mm plug with a center-hot configuration.

If you are using the USB host ports or expansion board Arduino shields, a higher current is required. To supply the full 500 mA per port, a mains power adapter must be used.

4.2.3.3 VBATBy default, VDDBU is delivered through the 3.3V node. An optional SuperCap (C41), used for real-time clock backup, is provided. The board does not come equipped with the SuperCap. When the SuperCap is not installed, an R185 must be installed. You must make sure that the R185 is removed prior to installing the SuperCap.

Figure 4-5. VBAT Powering Scheme Option Schematic

5V_MAINVbus[5]

5V_Ext[11]

R175 0RR175 0R

J2

DNP(DC JACK)

J2

DNP(DC JACK)

3

12

R176 DNP(0R)R176 DNP(0R)D4

P4SMAJ5.0A

D4

P4SMAJ5.0A12


R1 0RR1 0R



TDITMSTCKTDONTRST

NRST

VDDBU

3V3

3V3

TMS[11]TCK[11]TDO[11]

TDI[11]

NRST[4,9,10,11]

NTRST[11]

VBat[11]

(Super)-Capacitorenergy storage

Place TP4 to Bottom

Populate R185 ifno Super Cap (C41)

R25 10KR25 10K

R185

1.5K 1%

R185

1.5K 1%

D1

BAT54CLT1

D1

12

3

TP4

SMD

TP4

SMD

C2710nFC2710nF

C28100nFC28100nFC41

DNP(0.2F/3V3)

C41

DNP(0.2F/3V3)

TDOM11

TMSN10

TCKP9

NTRSTP11

TDIR8JTAGSELT9

BMSU9TSTU15

NRSTV9

VD

DB

UV

15

R231.5K 1%R231.5K 1%

R21100K 1%

R21100K 1%

R22DNP(100K)R22DNP(100K)

R20 100RR20 100R


4.2.4 Reset Circuitry

The reset sources for the SAMA5D3 Xplained board are: Power-on reset from the Power Management Unit (PMU), Reset Pushbutton BP2, JTAG reset from an in-circuit emulator (through JTAG interface)

4.2.5 Memory Organization

The SAMA5D3x-series processor features a DDR2/SDRAM memory interface and an External Bus Interface (EBI) to interface with a wide range of external memories and to almost any kind of parallel peripherals.

The memory devices that equip the SAMA5D3 Xplained evaluation kit are as follows: Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte). The board includes 2 Gbits of

on-board soldered DDR2 (double data rate) SDRAM. The footprints can also host two DDR2 (MT47H128M16RT) from Micron® for a total of 512 MBytes of DDR2 memory. The memory bus is 32 bits wide and operates with a frequency of up to 166 MHz (See Figure 4-6).

One NAND Flash (MT29F2G08ABAEAWP) connected to the processor. The default size is 256 MBytes. The footprint can also host a 4-Gbit Micron chip for a total of 512 MBytes of NAND Flash memory (See Figure 4-7).

Figure 4-6. DDR2 Schematic

DDR_A8DDR_D9DDR_D10DDR_D11DDR_D12DDR_D13

DDR_D15DDR_D14

DDR_A1

DDR_A9

DDR_A2 DDR_D2

DDR_A10

DDR_A3

DDR_A11

DDR_A4

DDR_A12

DDR_A5

DDR_D1

DDR_VREF

DDR_D0

DDR_A6

DDR_D4DDR_D3

DDR_A7DDR_D6DDR_D5

DDR_D7DDR_D8

DDR_A0

DDR_A8

DDR_D27DDR_D26DDR_D25

DDR_D31

DDR_D29DDR_D28

DDR_D30

DDR_A1

DDR_A9

DDR_A2

DDR_A10

DDR_D18DDR_A3

DDR_A11

DDR_A4

DDR_A12

DDR_A5

DDR_VREF

DDR_D17DDR_D16

DDR_A6

DDR_D19DDR_D20

DDR_D22DDR_A7 DDR_D23

DDR_D21

DDR_D24

DDR_A0

DDR_DQM0

DDR_DQS1

DDR_DQS0

DDR_CS

DDR_BA0DDR_BA1DDR_BA2

DDR_CKE

DDR_WE

DDR_CLK

DDR_RAS

DDR_CLKN

DDR_CAS

DDR_DQM2

DDR_DQS2

DDR_DQS3

DDR_CS

DDR_BA0DDR_BA1DDR_BA2

DDR_WE

DDR_CKE

DDR_RAS

DDR_CLK

DDR_CAS

DDR_CLKN

DDR_A13

DDR_DQM1DDR_DQM3

DDR_A13

VDDIODDRVDDIODDR

VDDIODDR

VDDIODDR

DDR_A[0..13]

DDR_D[0..31]

C98100nFC98100nF

C73 100nFC73 100nF

C100100nFC100100nF

C68 100nFC68 100nF

R39 4.7KR39 4.7K

C93 100nFC93 100nF

C90 100nFC90 100nF

C69 100nFC69 100nF

R41 4.7KR41 4.7K

C91 100nFC91 100nF

C70 100nFC70 100nF

C97 100nFC97 100nF

MT47H64M16HR

DDR2 SDRAM

MN5

MT47H64M16HR

DDR2 SDRAM

MN5

A0M8

A1M3

A2M7

A3N2

A4N8

A5N3

A6N7

A7P2

A8P8

A9P3

A10M2

BA0L2

ODTK9

DQ0 G8

DQ1 G2

DQ2 H7

DQ3 H3

DQ4 H1

DQ5 H9

DQ6 F1

DQ7 F9

UDQSB7

UDQSA8

LDMF3

VDD J9

VDD M9

VDDL J1

VREF J2

VDDQ E9

VSS A3

VSS E3

VDDQ A9

VDD E1

RFU1A2

RFU2E2

CKEK2

CKJ8

CKK8

CASL7

RASK7

WEK3

CSL8VDDQ C3

VDDQ C7

VDDQ C9

VSSQ D8

VSSQ E7

VSSQ F2

VSSQ F8

VDD A1

VSS J3

A11P7

BA1L3

A12R2

BA2L1

VSS N1

VSSDL J7

VSSQ B2

RFU3R3

DQ8 C8

DQ9 C2

DQ10 D7

DQ11 D3

DQ12 D1

DQ13 D9

DQ14 B1

DQ15 B9

VDD R1

VDDQ G1

VDDQ G7

VDDQ G9

VSS P9

VSSQ D2

VSSQ A7

VSSQ B8

VSSQ H2

VSSQ H8

VDDQ G3

VDDQ C1

UDMB3

LDQSE8LDQSF7

RFU4R7

A13R8

R40 4.7KR40 4.7K

C79 100nFC79 100nF

R36 DNP(1K)R36 DNP(1K)

C71 100nFC71 100nF

R42 4.7KR42 4.7K

MT47H64M16HR

DDR2 SDRAM

MN4

MT47H64M16HR

DDR2 SDRAM

MN4

A0M8

A1M3

A2M7

A3N2

A4N8

A5N3

A6N7

A7P2

A8P8

A9P3

A10M2

BA0L2

ODTK9

DQ0 G8

DQ1 G2

DQ2 H7

DQ3 H3

DQ4 H1

DQ5 H9

DQ6 F1

DQ7 F9

UDQSB7

UDQSA8

LDMF3

VDD J9

VDD M9

VDDL J1

VREF J2

VDDQ E9

VSS A3

VSS E3

VDDQ A9

VDD E1

RFU1A2

RFU2E2

CKEK2

CKJ8

CKK8

CASL7

RASK7

WEK3

CSL8VDDQ C3

VDDQ C7

VDDQ C9

VSSQ D8

VSSQ E7

VSSQ F2

VSSQ F8

VDD A1

VSS J3

A11P7

BA1L3

A12R2

BA2L1

VSS N1

VSSDL J7

VSSQ B2

RFU3R3

DQ8 C8

DQ9 C2

DQ10 D7

DQ11 D3

DQ12 D1

DQ13 D9

DQ14 B1

DQ15 B9

VDD R1

VDDQ G1

VDDQ G7

VDDQ G9

VSS P9

VSSQ D2

VSSQ A7

VSSQ B8

VSSQ H2

VSSQ H8

VDDQ G3

VDDQ C1

UDMB3

LDQSE8LDQSF7

RFU4R7

A13R8

C94 100nFC94 100nF

C78 100nFC78 100nF

C74 100nFC74 100nFR38 0RR38 0R

C95 100nFC95 100nF

C75 100nFC75 100nF

C96 100nFC96 100nF

R37 0RR37 0R

C88 100nFC88 100nF

C80 100nFC80 100nF

C89 100nFC89 100nF

C82 100nFC82 100nF

R35 DNP(1K)R35 DNP(1K)C66 100nFC66 100nF

C83 100nFC83 100nFC81 100nFC81 100nF

C84 100nFC84 100nF

C76 100nFC76 100nF

C86 100nFC86 100nFC85 100nFC85 100nF

C77 100nFC77 100nF

C67 100nFC67 100nF

C87 100nFC87 100nF

C92 100nFC92 100nF

C72 100nFC72 100nF

DDR_VREF

VDDIODDR

R461.5K 1%R461.5K 1%

R451RR451R

R471.5K 1%R471.5K 1%

C1014.7uFC1014.7uF

TP3

SMD

TP3

SMD

L16

10uH60mA

L16

10uH60mA

C102100nFC102100nF

C104100nFC104100nF

C1034.7uFC1034.7uF


Figure 4-7. NAND Flash Schematic

The following memory part numbers are recommended:

4.2.6 SD/MMC Interface

The SAMA5D3 Xplained board features two high-speed Multimedia Card Interfaces (MCI). The first interface is used as an 8-bit interface (MCI0), connected to a SD/MMC card slot (J10) located on the

bottom side of the PCB. The second interface is used as a 4-bit interface (MCI1), connected to an optional Micro-SD card connector (J11)

located on the top side of the PCB.

The MCI0 SD card power line is enabled by default. It is PIO-controlled through a MOSFET transistor.Note: The power source is VCC (3.3 volts).

4.2.6.1 J10 SD Card Slot When a card is inserted into the SD/MMC connector, the Card Detect pin (PE0) is tied to ground.

Figure 4-8. J10 SD Card Schematic

NRDNWE

M_EBI_D2

M_EBI_D4M_EBI_D3

M_EBI_D6M_EBI_D7

M_EBI_D5

M_EBI_D0M_EBI_D1

NANDRDY

PE21PE22

NCS3 VDDIOM

VDDIOM

(NANDCE)

(NANDCLE)(NANDALE)

C105100nFC105100nF

R48100K 1%

R48100K 1%

R50100K 1%

R50100K 1%

JP5

JUMPER

JP5

JUMPER

12

R49100K 1%

R49100K 1%

MN6MT29F2G08ABAEAWPMN6MT29F2G08ABAEAWP

WE18

N.C66

VCC 37

CE9

RE8

N.C1120

WP19

N.C55

N.C11

N.C22

N.C33

N.C44

DNU121

DNU222

N.C1223

N.C1324

R/B7

I/O8_N.C 26

I/O9_N.C 27

I/O10_N.C 28

I/O0 29

VCC_N.C 34

N.C1435

VSS 36

DNU338

VCC_N.C 39

VCC 12

VSS 13

ALE17

N.C811N.C710

N.C914

N.C1015

CLE16

VSS_N.C 25

I/O11_N.C 33

I/O1 30

I/O3 32I/O2 31

I/O15_N.C 47I/O14_N.C 46I/O13_N.C 45

I/O7 44I/O6 43I/O5 42I/O4 41

I/O12_N.C 40

VSS_N.C 48

C106100nFC106100nF

Table 4-3. Recommended Memories

Part Number Supplier Size Type

MT47H128M16 Micron 2 Gb (16 M x 16 x 8 banks) DDR2 - BGA

MT47H128M32 Micron 4 Gb (32 M x 16 x 8 banks) DDR2 - BGA

MT29F2G08 Micron 2 Gb NAND Flash - TSOP

MT29F4G08 Micron 4 Gb NAND Flash - TSOP

VDDIOP1VDD_MCI0

VDDIOP1

VDDIOM

PD1[7]

PE2 [7]

PD9[7]

PD0[7]PD4[7]PD3[7]

PE0[7]

PD6[7]PD7[7]PD8[7]

PD5[7]

PD2[7]

(MCI0_CD)

(MCI0_WP)

(MCI0_DA1)(MCI0_DA0)

(MCI0_CK)

(MCI0_CDA)(MCI0_DA3)(MCI0_DA2)



C10810uFC10810uF

R55

DNP(4.7K)

R55

DNP(4.7K)

R1

22

68

KR

12

26

8K

R182 22RR182 22R

R1

27

68

KR

12

76

8K

J10

7SDMM-B0-2211

J10

7SDMM-B0-2211

8

5

76

43219

141516

13121110

R5

41

0K

R5

41

0K

R1

24

68

KR

12

46

8K

R53100K 1%R53100K 1%

R57 0RR57 0R

R1

26

68

KR

12

66

8K

R1

21

68

KR

12

16

8K

Q3

IRLML6402

Q3

IRLML6402

1

3 2

R1

23

68

KR

12

36

8K

R5610KR5610K

R1

28

68

KR

12

86

8K

C109100nFC109100nF

R1

25

68

KR

12

56

8K


4.2.6.2 J11 SD Card Slot (optional)When a card is inserted into the Micro SD connector, the Card Detect pin is tied to ground. This is detected on pin PE1 of the main processor.

Figure 4-9. J11 Micro SD Card Schematic

4.2.7 Serial Peripheral Interface (SPI)

The SAMA5D3X-series processor features two high-speed Serial Peripheral Interfaces. One port is used to interface with the optional on-board serial DataFlash®.

There are four main signals used in the SPI interface; Clock, Data In, Data Out, and Chip Select.

Figure 4-10. Optional Serial DataFlash Schematic

VDDIOM

VDDIOP1

PB20[7]PB21[7]PB22[7]PB23[7]

PB19[7]PB24[7]

PE1[7]

(MCI1_DA1)

(MCI1_CK)(MCI1_CDA)


(MCI1_CD)

(MCI1_DA0)

Micro SD CARD INTERFACE - MCI1

C11010uFC11010uF

R183 22RR183 22R

J11

DNP(MCTF-0403)

J11

DNP(MCTF-0403)

DAT07

DAT18

DAT21

DAT32

VDD4

VSS6

CD9

PGND10

PGND 11

PGND 12

PGND 13

NC 14

NC 15

CMD3

CLK5

R1

29

68

KR

12

96

8K

R59

10K

R59

10K

R5

81

0K

R5

81

0K

R1

30

68

KR

13

06

8K

R1

12

DN

P(6

8K

)R

11

2D

NP

(68

K)

R1

31

68

KR

13

16

8K

R1

32

68

KR

13

26

8K

C111100nFC111100nF

PD11

PD12PD10

PD13

VDDIOP1

VDDIOP1

(SPI0_MIS0)(SPI0_MOSI)

(SPI0_SPCK)

(SPI0_CS)

C107100nFC107100nF

MN8

DNP(N25Q032A13ESE40F)

MN8

DNP(N25Q032A13ESE40F)

HOLD/DQ3 7

GND 4

VCC 8

S1

C6

DQO5

DQ12

W/Vpp/DQ2 3

JP6JUMPER

JP6JUMPER

1 2

R52100K 1%

R52100K 1%


4.2.8 Optional 1-Wire EEPROM

The SAMA5D3 Xplained board can use a 1-Wire device as “soft label” to store data such as chip type, manufacturer’s name, production date, etc.

Figure 4-11. Optional One-Wire EEPROM Schematic

4.2.9 10/100/100 Ethernet Port

The SAMA5D3 Xplained board features a MICREL PHY device (KSZ9031RN) operating at 10/100/1000 Mb/s. The board supports the RGMII interface mode. The Ethernet interface consists of four pairs of low-voltage differential pair signals designated from GRX± and GTX± plus control signals for link activity indicators. These signals are routed to the 10/100/1000 BaseT RJ45 connector (J12).

For monitoring and control purposes, LEDs are integrated in the RJ45 connectors to indicate activity, link, and speed status information for the corresponding ports.

For more information about the Ethernet controller device, refer to the MICREL KSZ9031RN datasheet.

Figure 4-12. Gigabit Ethernet Schematic

PE23

VDDIOM

R511.5KR511.5K

MN7

DNP(DS2431)

MN7

DNP(DS2431)

IO2

GN

D1

NC1 3

NC2 4

NC3 5

NC4 6

MN11

DNP(DS28E05)

MN11

DNP(DS28E05)

NC2

IO1

GND 3

PB3PB2PB1PB0

PB4PB5

PB6PB7

ETH0_A+ETH0_A-

ETH0_B-ETH0_C+ETH0_C-

ETH0_D+ETH0_D-

PB16PB11

PB13

PB9

PB17PB10

ETH0_LED2

XI

XO

ETH0_LED1

XI

XOPB18

PB8

ETH0_B+

VDDIOP1

DVDDL

AVDDL

AVDDH

AVDDL_PLL

VDDIOP1

VDDIOP1

VDDIOP1

VDDIOP1

PB[0..31]

[7,8,10,11]

NRST [4,5,10,11]

G125CK

GTX0GTX1GTX2GTX3

GRX0GRX1

GRX2GRX3

GTXCK

GTX_CTL

GRXCK

GRX_CTL

GMDC

GMDIOINT_GETHR

10Base-T/100Base-TX/1000BASE-T

R64

4.7K

R64

4.7K

R68 22RR68 22R

+ C12710uF

+ C12710uF

C112 20pFC112 20pF

R61 1KR61 1K

C12010nFC12010nF

R67

4.7K

R67

4.7K

C13610nFC13610nF

+ C11310uF

+ C11310uF

Y325MHz

Y325MHz

123 4

C12110nFC12110nF

C13510nFC13510nF

C12910nFC12910nF

+ C12610uF

+ C12610uF

C116 20pFC116 20pF

R69

4.7K

R69

4.7K

C11910nFC11910nF

L17180ohm at 100MHz

L17180ohm at 100MHz

1 2

C12210nFC12210nF

C11510nFC11510nF

R65

4.7K

R65

4.7K

C13410nFC13410nF

C12810nFC12810nF

C11810nFC11810nF

C11410nFC11410nF

C13310nFC13310nF

C12310nFC12310nF

KSZ9031RNI48-pin QFN

MN10KSZ9031RN

KSZ9031RNI48-pin QFN

MN10KSZ9031RN

VS

S_

PS

13

LE

D2

15

DV

DD

H1

6

LE

D1

17

DV

DD

L1

4

TX

D0

19

TX

D1

20

TX

D2

21

TX

D3

22

DV

DD

L1

8

DV

DD

L2

3

GT

X_

CL

K2

4

TX_EN 25DVDDL 26

RXD3 27

VSS 29DVDDL 30

RXD1 31RXD0 32

RX_DV 33DVDDH 34

RX_CLK 35MDC 36

MD

IO3

7IN

T_N

38

DV

DD

L3

9D

VD

DH

40

CL

K1

25

_N

DO

41

RE

SE

T_

N4

2L

DO

_O

43

XO

45

XI

46

AV

DD

H4

7IS

ET

48

AVDDH1

TXRXP_A2

TXRXM_A3

TXRXP_B5

TXRXM_B6

TXRXP_C7

TXRXM_C8

TXRXP_D10

TXRXM_D11

AVDDH12

RXD2 28

AV

DD

L_

PL

L4

4

P_

GN

D4

9

AVDDL4

AVDDL9

R66

4.7K

R66

4.7K

R63 12.1K 1%R63 12.1K 1%

C13810nFC13810nF

R60 4.7KR60 4.7K

+ C11710uF

+ C11710uF

C13710nFC13710nF R70 22RR70 22R

+ C13210uF

+ C13210uF

R62 22RR62 22R

EARTH_ETH0ETH0_GND

R73 0RR73 0RL18 180ohm at 100MHzL18 180ohm at 100MHz

1 2

ETH0_B+ETH0_B-

ETH0_D+ETH0_D-

ETH0_A+ETH0_A-

ETH0_C+ETH0_C-

ETH0_LED1

ETH0_LED2

AVDDH

VDDIOP1

EARTH_ETH0

ETH0_GND

LINK

ACT

Left Green LED

Right Yellow LED

C124

100nF

C124

100nF

R7

14

70

RR

71

47

0R

J12

48F-01GY2DPL2NL

J12

48F-01GY2DPL2NL

TD2+3

TD1+1

TD1-2

TD3+7

TD3-8

RCT6

TD2-4

GRLA 11

GRLC 12

TD4+9

TD4-10

TCT5

YELC 13

YELA 14

GND 15

GND 16

GND 17

GND 18

R7

24

70

RR

72

47

0R


C125

DNP(10uF 0805)

C125

DNP(10uF 0805)


4.2.10 Ethernet 10/100 Port

The SAMA5D3 Xplained board features a MICREL PHY device (KSZ8081RNB) operating at 10/100 Mb/s. The board supports RMII interface modes. The Ethernet interface consists of two pairs of low-voltage differential pair signals designated from GRX± and GTX± plus control signals for link activity indicators. These signals are routed to the 10/100 BaseT RJ45 connector (J13).

For monitoring and control purposes, a LED functionality is added on the RJ45 connectors to indicate activity, link, and speed status information for the corresponding ports.

For more information about the Ethernet controller device, refer to the MICREL KSZ8081RNB controller manufacturer's datasheet.

Figure 4-13. RMII Ethernet Schematic

4.2.11 Indicators

Two LEDs are available on the SAMA5D3 Xplained board. Both can be software-controlled by the user. The red LED indicates that power is applied to the board (by default). It can be controlled via software. The blue LED is mainly controlled by one GPIO line.

Figure 4-14. LED Indicators Schematic

ETH1_XO

ETH1_XI

ETH1_XO

ETH1_XI

ETH1_LED0

ETH1_LED0

TX+TX+

TX-

RX+

RX-RX-

RX+

TX-

ETH1_LED1ETH1_LED1

VDDIOP1 VDDIOP0

VDDIOP0E1_AVDDT

VDDIOP0

EARTH_ETH1EARTH_ETH1

GND_ETH1

VDDIOP0

EARTH_ETH1GND_ETH1

VDDIOP0

NRST [4,5,9,11]

ETH1_PC2 [7]ETH1_PC3 [7]

ETH1_PC0 [7]

ETH1_PC5 [7]ETH1_PC6 [7]

ETH1_PC7 [7]

ETH1_PC4 [7]

ETH1_PC8 [7]ETH1_PC9 [7]PB12 [7]

ETH1_PC1 [7]

10Base-T/100Base-TX

ACT

LINK

+ C14810uF

+ C14810uF

L19

180ohm at 100MHz

L19

180ohm at 100MHz1 2

MN9

KSZ8081RNB

MN9

KSZ8081RNB

RXC/B-CAST_OFF 19

CRS/CONFIG1 29

COL/CONFIG0 28

TXD1 25

TXD0 24

TXEN 23

RXD3/PHYAD0 13

RXD2/PHYAD1 14

RXD1/PHYAD2 15

RXD0/DUPLEX 16

RXDV/CONFIG2 18

RXER/ISO 20

MDC 12

MDIO 11

INTRP/NAND 21

VDDA_3V3 3

VDDIO 17

RESET 32

TXP7

TXM6

RXP5

RXM4

VDD_1V22

GND1

PADDLE33

TXC22

TXD226

TXD327

REXT10

XO8

XI9

LED0/NWAYEN30

LED1/SPEED31

R1

16

10

KR

11

61

0K

+ C14610uF

+ C14610uF

R1

20

10

KR

12

01

0K+ C144

10uF

+ C14410uF

C139100nFC139100nF

R1

14

10

KR

11

41

0K

R1

15

10

KR

11

51

0K

C147 20pFC147 20pF

C140100nFC140100nF C141 2.2uFC141 2.2uF

R79 470RR79 470R

Y425MHz

Y425MHz

123 4

C142 100nFC142 100nF

R80 470RR80 470R

C149

20pF

C149

20pF

R766.49k/1% R766.49k/1% C143100nFC143100nF

R75

1K

R75

1K

C145100nFC145100nF

R74

1K

R74

1K

R1

13

10

KR

11

31

0K

R81 0RR81 0R

R7810KR78

10K

L20180ohm at 100MHz

L20180ohm at 100MHz

1 2

R7710KR77

10K

R1

17

10

KR

11

71

0K

R1

18

10

KR

11

81

0K

1

2

3

6

4

5

7

8

75

75

75 75

1nF

TD+

TD-

CT

NC

RD-

CT

TX+

TX-

RX+

RX-

RD+

Left Green LED Right yellow LED

J1313F-64GYD2PL2NL

1

2

3

6

4

5

7

8

75

75

75 75

1nF

TD+

TD-

CT

NC

RD-

CT

TX+

TX-

RX+

RX-

RD+

Left Green LED Right yellow LED

J1313F-64GYD2PL2NL

1

2

7

8

3

6

5

4

9

10

11

12

1314

1516

R1

19

10

KR

11

91

0K

PE23

PE24

3V3

PE[0..31][4,7,8,11]

LEDD3

RED

D3

RED

R34470RR34470R

R33 100K 1%R33 100K 1%

Q2IRLML2502Q2IRLML2502

1

32

R32470RR32470R

D2

BLUE

D2

BLUE


4.2.12 USB

The SAMA5D3 Xplained board features three USB communication ports: Port A: High-speed (EHCI) and full-speed (OHCI) host multiplexed with high-speed USB device Micro-AB

connector (J6) Port B: High-speed (EHCI) and full-speed (OHCI) host, standard type A connector (J7 upper port) Port C: Full-speed OHCI host, standard type A connector (J7 lower port)

The two USB host ports are equipped with 500-mA high-side power switch for self-powered and bus-powered applications.

The USB device port A (J6) features a VBUS insert detection function through the ladder-type resistors R26 and R27.

Figure 4-15. USB Interface Schematic

4.2.13 Pushbutton Switches

The following pushbuttons switches are available: One board reset button (BP2). When pressed and released, this pushbutton causes a power-on reset of the whole

board. One wakeup pushbutton that brings the processor out of Low-power mode (BP1) One user pushbutton (BP3)

HHSDPC

HHSDMAHHSDPA

HHSDMBHHSDPB

HHSDMC

HHSDMCHHSDPC

HHSDMBHHSDPB

5V_USBB 5V_USBC

5V_USBB

5V_USBC

GNDUTMIGNDUTMI

EARTH_USB

5V_MAIN

EARTH_USB

EARTH_USB_A

PE5 [7]

Vbus[4]

PE9[7,11]

PE4 [7]

PE3 [7]

OVCUR_USB

USB A DEVICE INTERFACE

(VBUS_SENSE)

J7_USB_A_Up J7_USB_B_DownEN5V_USBC

EN5V_USBB

C6010pFC6010pF

32.768KY2Y2

11233 44

R27

200K

R27

200K

C5C533 20pF20pFpp

MN3

SP2526A-2E

MN3

SP2526A-2E

ENA 1

FLGA 2

ENB 4

OUTA8

GNG6 FLGB 3

IN7

OUTB5

J6UBAF-1015PJ6UBAF-1015P

MN2HSAMA5D3x_BGA324

MN2HSAMA5D3x_BGA324

GN

DC

OR

E_

1AA

1166

GN

DC

OR

E_

2CC

99

GN

DIO

DD

R_

1EE

1144

GN

DIO

DD

R_

2F

10

F1

0

GN

DIO

DD

R_

3F

13

F1

3

GN

DIO

DD

R_

4F

15

F1

5

GN

DIO

DD

R_

5H

1H

144

GN

DIO

P_

1JJ77

GN

DIO

M_

1J1

J1

11

GN

DA

NA

L4

ADVREF

VDDANA

GN

DIO

P_

2N

1N

111

GN

DC

OR

E_

3N

1N

133

GN

DF

US

EPP

44

GN

DP

LL

PP11

00

GN

DU

TM

I_1

R1

2

VDDPLLA

VBGR11

GN

DC

OR

E_

4T

8T

8

GN

DO

SC

T1

1T

11

GN

DB

UT

13

T1

3

GN

DC

OR

E_

5T

14

T1

4

GN

DIO

M_

2T

17

T1

7

GN

DIO

P_

3UU

77

VDDOSC

VDDUTMII

XIN32U16

XOUTV8

VDDUTMIC

XOUT32V16

GN

DC

OR

E_

6VV

1177

GN

DIO

P_

4EE

55

HHSDMAV10

HHSDPAU10

HHSDMCV14

HHSDPCU14

HHSDPBU12HHSDMBV12

DIBNU6

DIBPV6

C61100nFC61100nF

L21 180ohm at 100MHzL21 180ohm at 100MHz

1 2

C5C566 20pF20pF

12MHz

333 4444

C64100nFC64100nF

R305.62K 1%R305.62K 1%

L13180ohm at 100MHz

L13180ohm at 100MHz

1 2

C6210uFC6210uF C63

100nFC63100nF

L15180ohm at 100MHz

L15180ohm at 100MHz

1 2

A

B

J7Dual USB A

A

B

J7Dual USB A

5

8

67

9 10

1234

1112

R31 0RR31 0R

C5C511 20pF20pFpp

L14180ohm at 100MHz

L14180ohm at 100MHz

1 2

C6510uFC6510uF

R26 100K 1%R26 100K 1%

33333333333

EARTH_USB_A

VBUSDMDPID

GND

VBUSDMDPID

GND

12345

76

8


Figure 4-16. Pushbutton Schematic

4.2.14 LCD

The SAMA5D36 processor drives 24 bits of data and control signals to the LCD interface. Other signals are used to control the LCD and are also routed to the J22 connector: TWI, SPI, 2 GPIOs for interrupt, ID for 1-Wire EEPROM (ID_SYS) and power supply lines.

4.2.14.1 LCD ConnectorOne 1.27 mm pitch 50-pin header is provided to gain access to the LCD signals.

Figure 4-17. LCD Expansion Header Interface Schematic

4.2.14.2 LCD PowerTo operate correctly with various LCD modules, regardless of the processor, two voltage lines are available: 3V3 by default and 5V_MAIN, both selected by 0R resistors R92 and R93.

BP

2

BP

1RESET

WAKUP or Force Power ON

AutoPWRON(option)

R14

50K

R14

50K

BP2BP2

C20100nFC20100nF

GN

DP

12

9

GN

DA

2

GN

DP

22

8

REFBP32

nPBIN9

Q1

IRLML2502

Q1

IRLML2502

1

3

2R19

100K 1%

R19

100K 1%

R15

0R

R15

0R

C1847nFC1847nF

C25100nF

C25100nF

R12 49.9K

C13010nFC13010nF

BP1BP1

PE29[7,11]

Place TP5 to Bottom

BP3BP3

TP5

SMD

TP5

SMD

USER BUTTON

PA0PA1PA2PA3

PA4PA5PA6PA7

PA8PA9PA10PA11

PA15PA14PA13PA12

PA25

PA24

PC13PC12PC11

PC14

PC10PC15PE27PE28

PA29PA27PA26

PE8PE7

TWD_LCDTWCK_LCD

PE23

PD10

PD11

PD12

PD16

PD20

PD21

PD22

PD23

PE6NRST

TWCK_LCDTWD_LCD

PA28

3V35V_MAIN

TWCK_LCD[7]TWD_LCD[7]

LCD Connector

(ID_SYS)

(SPI0_SPCK)

(SPI0_MOSI)

(SPI0_MISO)

(SPI0_NPCS3)

(AD0)

(AD1)

(AD2)

(AD3)

(RST_LCD)

(LCDDAT0)(LCDDAT1)(LCDDAT2)(LCDDAT3)





(LCDDAT20)(LCDDAT21)(LCDDAT22)(LCDDAT23)(LCDPCK)

(LCDVSYNC)(LCDHSYNC)(LCDDEN)

(LCDDISP)

(LCDPWM)(IRQ2)IRQ1)

R101 22RR101 22R

R103 22RR103 22R

R93 0RR93 0R



R184 22RR184 22R


J22J22

FP520T1-50SR04

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950

5251


R94 0RR94 0R

R96 22RR96 22R


R97 22RR97 22R



4.2.15 Debug JTAG/ICE and DBGU

4.2.15.1 Debug JTAG/ICEA 2x10-pin JTAG header is implemented on the SAMA5D3 Xplained board to enable the software development and debugging of the board by using various JTAG emulators. The interface signals have a voltage level of 3.3V.

Figure 4-18. JTAG/ICE Interface Schematic

4.2.15.2 DBGUThe SAMA5D3 Xplained board has a dedicated serial port for debugging, which is accessible through the 6-pin male header J23. Various interfaces can be used as USB/Serial DBGU port bridge, such as FTDI TTL-232R-3V3 USB to TTL serial cable or basic breakout board for the 232/USB converter.

These interfaces are available on the following websites: Adafruit: http://www.adafruit.com/products/284 Sparkfun: https://www.sparkfun.com/products/9873

Figure 4-19. DBGU Interface Schematic

R171 and R172 are optional (not implemented) resistors that can be used for power selection. Power can be delivered either by the SAMA5D3 Xplained board or by the debug interface tool. To avoid a contention between your debug interface (e.g. FTDI) and the on-board power system, be careful during the installation of one of this resistor.

4.2.16 Expansion Ports

Five 8-pin, one 10-pin, one 6-pin and one 2x18-pin headers (J14 to J21) are implemented on the board to enable the PIO connection of various expansion cards that could be developed by users or by other sources. Due to multiplexing, different signals can be provided on each pin. These connectors are mechanically and footprint compatible with the

TCKTMS

RTCK

TDI

TDO

3V3

VDDIOP0

NRST [4,5,9,10]TDO [5]

TDI [5]

TCK [5]TMS [5]

NTRST [5]

JTAG

R106

100K 1%

R106

100K 1%

J24J24

12345678910111213151719

14161820

R105

100K 1%

R105

100K 1%

R108 0RR108 0R

R104

100K 1%

R104

100K 1%

R109 0RR109 0R

R107100K 1%R107100K 1%

R110 0RR110 0R

DEBUG(TXD)(RXD)

PE13

PE14

5V_MAIN3V33V3

PB31[7]PB30[7]

R1

90

68

K

J23

P101-1*06SGF-116A-NX

123456

R173 0R

R1

71

DN

P(0

R)

R174 0R

R1

89

68

K

R1

72

DN

P(0

R)


Arduino R3 shields. As the SAMA5D3 signals have a voltage level of 3.3V, 5-V level shields must not be used on the SAMA5D3 Xplained.

In addition to its standard IO functionality, the SAMA5D3 processor can provide alternate functions to external IO lines available on the J14 to J21 headers.

These alternate functions are: UARTs: UART0, UART1 USARTs: USART0, USART1, USART2, USART3 SPI: SPI1 I²C: TWI0, TWI1 Timer capture and compare: TIOA, TIOB Clock out: PCK0, PCK1, PCK2 PWMs: PWML0, PWMH0, PWML1, PWMH1 DIGITAL AUDIO: TD0, TK0, TF0, RD0, RK0, RF0 ISI: ISI[D0:D11], ISI_HSYNC, ISI_VSYNC, ISI_PCK CAN: CAN-RX0, CANTX0, CANRX1, CAN_TX1 Analog: AD[0:11], ADTRG, ADREF GPIO: MISC RESET VBAT

To get further details on the PIO multiplexing and alternate function selection, refer to the SAMA5D3 series datasheet.


4.2.16.1 Functions available through the Arduino HeadersThe following tables illustrate the functionalities provided by the SAMA5D3 Xplained board. They show the pins used to implement each functionality. Note: Some pins are multiplexed for different functionalities, which means that only one at a time can be active for

each pin.

Table 4-4. Function by PIO (part 1)

PIO NAME PCK ISI SSC CAN SPI

PC16 -- -- TK0 -- --

PC17 -- -- TF0 -- --

PC18 -- -- TD0 -- --

PC20/PD28 -- -- RF0 -- --

PC21/PD29 -- -- RD0 -- --

PC19/PD30 PCK0 -- RK0 -- --

PD30/PC15 PCK0/PCK2 -- -- -- --

PD31 PCK1 -- -- -- --

PB14 -- -- -- CANRX1 --

PD14 -- -- -- CANRX0 --

PB15 -- -- -- CANTX1 --

PD15 -- -- -- CANTX0 --

PC22/PC1 -- -- -- -- SPI1_MISO

PC24/PC0 -- -- -- -- SPI1_SPCK

PC23/PC2 -- -- -- -- SPI1_MOSI

PC25 -- -- -- -- SPI1_NPCS0

PC26/PA30 -- ISI_D11/VSYNC -- -- SPI1_NPCS1

PC27/PA31 -- ISI_D10/HSYNC -- -- SPI1_NPCS2

PC28 -- ISI_D9 -- -- SPI1_NPCS3

PC29 -- ISI_D8 -- -- --

PA23 -- ISI_D7 -- -- --

PA22 -- ISI_D6 -- -- --

PA21 -- ISI_D5 -- -- --

PA20 -- ISI_D4 -- -- --

PA19 -- ISI_D3 -- -- --

PA18 -- ISI_D2 -- -- --

PA17 -- ISI_D1 -- -- --

PA16 -- ISI_D0 -- -- --

PC30 -- ISI_PCK -- -- --

PA30 -- ISI_VSYNC -- -- --

PA31 -- ISI_HSYNC -- -- --


Table 4-5. Function by PIO (part 2)

PIO NAME TWI UART/USART ANALOG MISC

3V3/5V -- -- -- 3V3/5V

nRTS -- -- -- nRTS

GND -- -- -- GND

AREF -- -- AREF --

5V -- -- -- 5V

PC18 -- -- AD0 --

PD21 -- -- AD1 --

PD22 -- -- AD2 --

PD23 -- -- AD3 --

PD24 -- -- AD4 --

PD25 -- -- AD5 --

PD26 -- -- AD6 --

PD27 -- -- AD7 --

PC20/PD28 -- -- AD8 --

PC21/PD29 -- -- AD9 --

PC19/PD30 -- -- AD10 --

PD31 -- -- AD11 --

PD19/PB15 -- -- ADTRG --

PA19 TWCK2 -- -- --

PA18 TWD2 -- -- --

PC26 TWD1 -- -- --

PA30 TWD0 URXD1 -- --

PA31 TWCK0 UTXD1 -- --

PC26/PA30 TWD0/TWD1 URXD1 -- --

PC27/PA31 TWCK0/TWCK1 URTD1 -- --

PC30 -- UTXD0 -- --

PC29 -- URXD0 -- PWMFI2

PD14 -- SCK0 -- --

PD15 -- CTS0 -- --

PD18 -- TXD0 -- --

PD17 -- RXD0 -- --

PB25 -- SCK1 -- --

PB26 -- CTS1 -- --

PB29 -- TXD1 -- --

PB28 -- RXD1 -- --


PB27 -- RTS1 -- PWMH1

PE20 -- SCK2 -- --

PE23 -- CTS2 -- --

PE26 -- TXD2 -- --

PE25 -- RXD2 -- --

PE24 -- RTS2 -- --

PE15 -- SCK3 -- --

PE16 -- CTS3 -- --

PE19 -- TXD3 -- --

PE18 -- RXD3 -- --

PE17 -- RTS3 -- --

PC22/PC1 -- -- -- GPIO

PC23/PC2 -- -- -- GPIO

PC24/PC0 -- -- -- GPIO

PC9 -- -- -- GPIO

PE9 -- -- -- GPIO

PE10 -- -- -- GPIO

PE11 -- -- -- GPIO

PE12 -- -- -- GPIO

PE16 -- -- -- GPIO

PE31 -- -- -- IRQ/PWML1

PC28 -- -- -- PWMFI0

PA20 -- -- -- PWMH0

PA22 -- -- -- PWMH1

PA21 -- -- -- PWML0

PA23 -- -- -- PWML1

PE29 -- -- -- TCLK2

PC5 -- -- -- TCLK4

PC8 -- -- -- TCLK5

PC3 -- -- -- TIOA4

PC6 -- -- -- TIOA5

PC4 -- -- -- TIOB4

PC7 -- -- -- TIOB5

Table 4-5. Function by PIO (part 2) (Continued)

PIO NAME TWI UART/USART ANALOG MISC


4.2.16.2 J15 Header

Figure 4-20. J15 Header

Table 4-6. J15 Header IOs

Silkscreen PIO Function 1 Function 2 Function 3 PIO Function 4 Function 5

SCL0 PA31 TWCK0 UTXD1 ISI_HSYNC -- -- --

SDA0 PA30 TWD0 URXD1 ISI_VSYNC -- -- --

ARFE -- -- -- -- -- -- --

GND -- -- -- -- -- -- --

13 PC24 SPI1_SPCK -- -- PC0 ETX0 TIOA3

12 PC22 SPI1_MISO -- -- PC1 ETX1 TIOB3

11 PC23 SPI1_MOSI -- -- PC2 ERX0 TCLK3

10 PC25 SPI1_NPCS0 -- -- -- -- --

9 PC3 ERX1 TIOA4 -- -- -- --

8 PC4 ETXEN TIOB4 -- -- -- --


4.2.16.3 J18 Header



Silkscreen PIO Function 1 Function 2 Function 3

7 PC5 ECRSDV TCLK4 --

6 PC6 ERXER TIOA5 --

5 PC7 EREFCK TIOB5 --

4 PC28 SPI1_NPCS3 PWMFI0 ISI_D9

3 PC8 EMDC TCLK5 --

2 PC9 EMDIO -- --

1 PC30 UTXD0 ISI_PCK --

0 PC29 URXD0 PWMFI2 ISI_D8


4.2.16.4 J20 Header



Silkscreen PIO Function 1 Function 2 Function 3 PIO Function 4 Function 5 Function 6

TXD3 14 PE19 A19 TXD3 -- -- -- -- --

RXD3 15 PE18 A18 RXD3 -- -- -- -- --

TXD1 16 PB29 TXD1 -- -- -- -- -- --

RXD1 17 PB28 RXD1 -- -- -- -- -- --

TXD0 18 PD18 TXD0 -- -- -- -- -- --

RXD0 19 PD17 RXD0 -- -- -- -- -- --

SDA 20 PC26 SPI1_NPCS1 TXWD1 ISI_D11 PA30 TWD0 URXD1 ISI_VSYNC

SCL 21 PC27 SPI1_NPCS2 TWCK1 ISI_D10 PA31 TWCK0 UTXD1 ISI_HSYNC


4.2.16.5 J19 Header




PD30 PD30 AD10 PCK0 -- PC15 PCI2_CK PCK2

PC17 PC17 TF0 -- -- -- -- --

PB26 PB26 CTS1 GRX7 -- -- -- --

PE9 PE9 A9 -- -- -- -- --

PA17 PA17 LCDDAT17 ISI_D1 -- -- -- --

PA19 PA19 LCDDAT19 TWCk2 ISI_D3 -- -- --

PA21 PA21 LCDDAT21 PWML0 ISI_D5 -- -- --

PA23 PA23 LCDDAT23 PWML1 ISI_D7 -- -- --

PE15 PE15 A15 SCK3 -- -- -- --

PE17 PE17 A17 RTS3 -- -- -- --

PE11 PE11 A11 -- -- -- -- --

PE23 PE23 A23 CTS2 -- -- -- --

PE25 PE25 A25 RXD2 -- -- -- --

PE13 PE13 A13 -- -- -- -- --


PE29 PE29 NWR1/NBS1 TCLK2 -- -- -- --

PC26 PC26 SPI1_NPCS1 TXWD1 ISI_D11 -- -- --

PC16 PC16 TK0 -- -- -- -- --

PB25 PB25 SCK1 GRX6 -- -- -- --

PB27 PB27 RTS1 PWMH1 -- -- -- --

PE10 PE10 A10 -- -- -- -- --

PA16 PA16 LCDDAT16 ISI_D0 -- -- -- --

PA18 PA18 LCDDAT18 TWD2 ISI_D2 -- -- --

PA20 PA20 LCDDAT20 PWMH0 ISI_D4 -- -- --

PA22 PA22 LCDDAT22 PWMH1 ISI_D6 -- -- --

PE16 PE16 A16 CTS3 -- -- -- --

PE20 PE20 A20 SCK2 -- -- -- --

PE12 PE12 A12 -- -- -- -- --

PE24 PE24 A24 RTS2 -- -- -- --

PE26 PE26 NCS0 TXD2 -- -- -- --

PE14 PE14 A14 -- -- -- -- --

PE31 PE31 IRQ PWML1 -- -- -- --

PB15 PB15 GCOL CANTX1 -- -- -- --

Table 4-9. J19 Header IOs (Continued)



4.2.16.6 J16 Header



Silkscreen PIO Function 1

MISO1 PC22 SPI1_MISO

5V/3V3 -- Power supply

SPCK PC24 SPI1_SPCK

MOSI1 PC23 SPI1_MOSI

RST NRST System reset

GND -- Power ground


4.2.16.7 J14 Header

Figure 4-25. J14 Header Position


Silkscreen Function

VBAT VBAT supply

3V3 AREF. Reference voltage for the analog inputs of the SAMA5D36 processor.

RST System reset

3V3Main 3.3V supply - generated by the on-board regulator. Maximum sourced current is 1.2A. This regulator also provides the power supply to the SAMA5D36 microcontroller and components.

5V Main 5.0V supply

GND System ground

GND System ground

NC Not connected


4.2.16.8 J17 Header




A0 PC18 TD0 -- -- PD20 AD0 --

A1 PD21 AD1 -- -- -- -- --

A2 PD22 AD2 -- -- -- -- --

A3 PD23 AD3 -- -- -- -- --

A4 PD24 AD4 -- -- -- -- --

A5 PD25 AD5 -- -- -- -- --

A6 PD26 AD6 -- -- -- -- --

A7 PD27 AD7 -- -- -- -- --


4.2.16.9 J21 Header


Table 4-13. J21 Header IO


A8 PC20 RF0 -- -- PD28 AD8 --

A9 PC21 RD0 -- -- PD29 AD9 --

A10 PC19 RK0 -- -- PD30 AD10 PCK0

A11 PD31 PCK1 -- -- -- -- --

** PB14 GCRS CANRX1 -- -- -- --

** PD19 ADTRG -- -- PB15 GCOL CANTX1

CANRX0 PD14 SCK0 SPO_NPCS1 CANRX0 -- -- --

CANTX0 PD15 CTS0 SPI0_NPCS2 CANTX0 -- -- --


4.3 Other Connector Details and PIO Usage Summary

4.3.1 Power Supply

Figure 4-28. Power Supply Connector J2 (Optional)

Table 4-14. Power Supply Connector J2 Signal Description

Pin Mnemonic Signal Description

1 Center +5V

2 -- GND

3 -- Floating


4.3.2 JTAG/ICE Connector

Figure 4-29. JTAG port J24

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

Table 4-15. JTAG/ICE Connector J24 Signal Descriptions


1 VTref 3.3V power

This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators, and to control the output logic levels to the target. It is normally fed from VDD on the target board and must not have a series resistor.

2 Vsupply 3.3V power This pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to VDD or leave open in target system.

3 nTRST Target Reset - Active-low output signal that resets the target.

JTAG Reset. Output from SAM-ICE to the reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled High on the target to avoid unintentional resets when there is no connection.

4 GND Common ground.

5TDI Test Data Input - Serial data output line, sampled on the rising edge of the TCK signal.

JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU.


7 TMS Test Mode Select.

JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target's JTAG state machine, sampled on the rising edge of the TCK signal.


9TCK Test Clock - Output timing signal, for synchronizing test logic and control register access.

JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU.


11 RTCK - Input Return Test Clock signal from the target.

Some targets must synchronize the JTAG inputs to internal clocks. To fulfill this requirement, a returned and resynchronized TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.


13 TDO JTAG Test Data Output - Serial data input from the target.

JTAG data output from target CPU. Typically connected to TDO on target CPU.

14 GND Common ground

15 nSRST RESET Active-low reset signal. Target CPU reset signal.



4.3.3 USB Type A Dual Port

Figure 4-30. USB Type A Dual Port J19

17 RFU This pin is not connected.


19 RFU This pin is not connected.


Table 4-15. JTAG/ICE Connector J24 Signal Descriptions (Continued)


Table 4-16. USB Type A Dual Port J19 Signal Descriptions


A1 Vbus - USB_A 5V power

A2 DM - USB_A Data minus

A3 DP - USB_A Data plus

A4 GND Common ground

B1 Vbus - USB_A 5V power

B2 DM - USB_A Data minus

B3 DP - USB_A Data plus

B4 GND Common ground

Mechanical pins -- Shield


4.3.4 USB Micro-AB

Figure 4-31. USB Host/Device Micro-AB Connector J6

4.3.5 DEBUG Connector

Figure 4-32. DEBUG Connector J23

4.3.6 SD/MMC Plus MCI0

Figure 4-33. SD/MMC Socket J10

1 2 3 4 5

Table 4-17. USB Device Micro-AB Connector J6 Signal Descriptions


1 Vbus 5V power

2 DM Data minus

3 DP Data plus

4 ID On-the-go identification

5 GND Common ground

Table 4-18. DEBUG Connector J23 Signal Descriptions

Pin Mnemonic PIO Signal Description

1 -- PE13 --

2 TXD (transmitted data) PB31 RS232 serial data input signal

3 RXD (transmitted data) PB30 RS232 serial data output signal

4 -- -- Power line (5V/3V3)

5 -- PE14 --

6 GND -- Common ground


Table 4-19. SD/MMC Socket J10 Signal Descriptions


1 DAT3 PD4 Data bit

2 CMD PD0 Command line

3 VSS -- Command line

4 VCC -- Supply voltage 3.3V

5 CLK PD9 Clock / command line

6 CD PE0 Card detect

7 DAT0 PD1 Data bit

8 DAT1 PD2 Data bit

9 DAT2 PD3 Data bit

10 DAT4 PD5 Data bit




14 WP R57 Protect

15 VSS -- Common ground



4.3.7 MicroSD MCI1

Figure 4-34. MicroSD Socket J11

4.3.8 Gigabit Ethernet ETH0 RJ45 Socket J12

Figure 4-35. Gigabit Ethernet RJ45 Socket J12

4.3.9 Ethernet ETH1 RJ45 Socket J13

Figure 4-36. Ethernet RJ45 Socket J13

Table 4-20. MicroSD Socket J11 Signal Descriptions


1 DAT2 PB22 Data bit 2

2 CD/DAT3 PB23 Card detect / data bit 3

3 CMD PB19 Command line

4 VCC -- Supply voltage 3.3V

5 CLK PB24 Clock / command line




9 SW1 -- Not used, grounded

10 CARD DETECT PE1 Card detect

1 2 3 4 5 6 7 8

RJ-45

1 2 3 4 5 6 7 8

RJ-45


4.3.10 LCD Socket J22

Figure 4-37. LCD Socket J22

Table 4-21. LCD Socket J22 Signal Descriptions

PIN Signal Display Module Interface Function MCU Interface Function

1 ID_SYSExtension module identification (connected to 1-wire EEPROM available on LCD display module)

Extension module identification

2 GND GND GND

3 D0 Data line Data line




7 GND GND GND





12 GND GND GND





17 GND GND GND





22 GND GND GND





27 GND GND GND



4.3.11 PIO Usage

Most signals can also be configured as simple inputs or outputs from the processor.




32 GND GND GND

33 PCLK Pixel clock --

34 VSYNC/CS Vertical sync Chip select

35 HSYNC/WE Horizontal sync Write enable

36 DATA_ENABLE/RE Data enable Read enable

37 SPI_SCK -- SPI_SCK

38 SPI_MOSI -- SPI_MOSI

39 SPI_MISO -- SPI_MISO

40 SPI_CS -- SPI_CS

41 ENABLE Display enable signal Display enable signal

42 TWI_SDA I2C data line (maXTouch®) I2C data line (maXTouch)

43 TWI_SCL I2C clock line (maXTouch) I2C clock line (maXTouch)

44 IRQ1 maXTouch interrupt line maXTouch interrupt line

45 IRQ2 Interrupt line for other I2C devices Interrupt line for other I2C devices

46 PWM Backlight control Backlight control

47 RESET Reset for both display and maXTouch Reset for both display and maXTouch

48 VCC 3.3V or 5V supply (0R) 3.3V supply

49 VCC 3.3V or 5V supply (0R) 3.3V supply

50 GND GND GND

Table 4-21. LCD Socket J22 Signal Descriptions (Continued)

PIN Signal Display Module Interface Function MCU Interface Function

Table 4-22. PIO A Pin Assignment and Signal Description

Power Rail PIO Signal Signal Signal Main Board Function Extended Function

VDDIOP0 PA0 LCDDAT0 – – – LCDDAT0

















VDDIOP0 PA16 LCDDAT16 ISI_D0 – – ISI_D0

VDDIOP0 PA17 LCDDAT17 ISI_D1 – – ISI_D1

VDDIOP0 PA18 LCDDAT18 TWD2 ISI_D2 – TWD2/ISI_D2

VDDIOP0 PA19 LCDDAT19 TWCK2 ISI_D3 – TWCK2/ISI_D3

VDDIOP0 PA20 LCDDAT20 PWMH0 ISI_D4 – ISI_D4

VDDIOP0 PA21 LCDDAT21 PWML0 ISI_D5 – ISI_D5

VDDIOP0 PA22 LCDDAT22 PWMH1 ISI_D6 – ISI_D6

VDDIOP0 PA23 LCDDAT23 PWML1 ISI_D7 – ISI_D7

VDDIOP0 PA24 LCDPWM – – – LCDPWM

VDDIOP0 PA25 LCDDISP – – – LCDDISP

VDDIOP0 PA26 LCDVSYNC – – – LCDVSYNC

VDDIOP0 PA27 LCDHSYNC – – – LCDHSYNC

VDDIOP0 PA28 LCDPCK – – – LCDPCK

VDDIOP0 PA29 LCDDEN – – – LCDDEN

VDDIOP0 PA30 TWD0 URXD1 ISI_VSYNC TWD0 URXD1/ISI_VSYNC

VDDIOP0 PA31 TWCK0 UTXD1 ISI_HSYNC TWCK0 UTXD1/ISI_HSYNC

Table 4-23. PIO B Pin Assignment and Signal Description

Power Rail PIO Signal Signal Signal Main Board Function

Extended Function

VDDIOP1 PB0 GTX0 PWMH0 – GTX0 –

VDDIOP1 PB1 GTX1 PWML0 – GTX1 –

VDDIOP1 PB2 GTX2 TK1 – GTX2 –

VDDIOP1 PB3 GTX3 TF1 – GTX3 –

VDDIOP1 PB4 GRX0 PWMH1 – GRX0 –

VDDIOP1 PB5 GRX1 PWML1 – GRX1 –

VDDIOP1 PB6 GRX2 TD1 – GRX2 –

VDDIOP1 PB7 GRX3 RK1 – GRX3 –

Table 4-22. PIO A Pin Assignment and Signal Description

Power Rail PIO Signal Signal Signal Main Board Function Extended Function


VDDIOP1 PB8 GTXCK PWMH2 – GTXCK –

VDDIOP1 PB9 GTXEN PWML2 – GTXEN –

VDDIOP1 PB10 GTXER RF1 – INT_GETH --

VDDIOP1 PB11 GRXCK RD1 – GRXCK --

VDDIOP1 PB12 GRXDV PWMH3 – INT_ETH –

VDDIOP1 PB13 GRXER PWML3 – GRXER –

VDDIOP1 PB14 GCRS CANRX1 – – CANRX1

VDDIOP1 PB15 GCOL CANTX1 – – CANTX1

VDDIOP1 PB16 GMDC – – GMDC --

VDDIOP1 PB17 GMDIO – – GMDIO –

VDDIOP1 PB18 G125CK – – G125CK –

VDDIOP1 PB19 MCI1_CDA GTX4 – MCI1_CDA --

VDDIOP1 PB20 MCI1_DA0 GTX5 – MCI1_DA0 –

VDDIOP1 PB21 MCI1_DA1 GTX6 – MCI1_DA1 --

VDDIOP1 PB22 MCI1_DA2 GTX7 – MCI1_DA2 --

VDDIOP1 PB23 MCI1_DA3 GRX4 – MCI1_DA3 –

VDDIOP1 PB24 MCI1_CK GRX5 – MCI1_CK –

VDDIOP1 PB25 SCK1 GRX6 – – SCK1

VDDIOP1 PB26 CTS1 GRX7 – – CTS1

VDDIOP1 PB27 RTS1 PWMH1 – – RTS1

VDDIOP1 PB28 RXD1 – – – RXD1

VDDIOP1 PB29 TXD1 – – – TXD1

VDDIOP0 PB30 DRXD – – DRXD (DBGU) --

VDDIOP0 PB31 DTXD – – DTXD (DBGU) --

Table 4-24. PIO C Pin Assignment and Signal Description

Power Rail PIO Signal Signal SignalMain Board

Function Extended Function

VDDIOP0 PC0 ETX0 TIOA3 – ETX0 ETX0/TIOA3

VDDIOP0 PC1 ETX1 TIOB3 – ETX1 ETX1/TIOB3

VDDIOP0 PC2 ERX0 TCLK3 – ERX0 ERX0/TCLK3

VDDIOP0 PC3 ERX1 TIOA4 – ERX1 ERX1/TIOA4

VDDIOP0 PC4 ETXEN TIOB4 – ETXEN ETXEN/TIOB4

VDDIOP0 PC5 ECRSDV TCLK4 – ECRSDV ECRSDV/TCLK4

VDDIOP0 PC6 ERXER TIOA5 – ERXER ERXER/TIOA5

VDDIOP0 PC7 EREFCK TIOB5 – EREFCK EREFCK/TIOB5

Table 4-23. PIO B Pin Assignment and Signal Description (Continued)


Extended Function


VDDIOP0 PC8 EMDC TCLK5 – EMDC EMDC/TCLK5

VDDIOP0 PC9 EMDIO -- – EMDIO EMDIO

VDDIOP0 PC10 MCI2_CDA LCDDAT20 – – LCDDAT20

VDDIOP0 PC11 MCI2_DA0 LCDDAT19 – – LCDDAT19

VDDIOP0 PC12 MCI2_DA1 TIOA1 LCDDAT18 – LCDDAT18

VDDIOP0 PC13 MCI2_DA2 TIOB1 LCDDAT17 – LCDDAT17

VDDIOP0 PC14 MCI2_DA3 TCLK1 LCDDAT16 – LCDDAT16

VDDIOP0 PC15 MCI2_CK PCK2 LCDDAT21 – LCDDAT21/PCK2

VDDIOP0 PC16 TK0 – – – TK0 Audio

VDDIOP0 PC17 TF0 – – – TF0 Audio

VDDIOP0 PC18 TD0 – – – TD0 Audio

VDDIOP0 PC19 RK0 – – – RK0 Audio

VDDIOP0 PC20 RF0 – – – RF0 Audio

VDDIOP0 PC21 RD0 – – – RD0 Audio

VDDIOP0 PC22 SPI1_MISO – – – SPI1_MISO

VDDIOP0 PC23 SPI1_MOSI – – – SPI1_MOSI

VDDIOP0 PC24 SPI1_SPCK – – – SPI1_SPCK

VDDIOP0 PC25 SPI1_NPCS0 – – – SPI1_NPCS0

VDDIOP0 PC26 SPI1_NPCS1 TWD1 ISI_D11 – SPI1_NPCS1/TWD1

VDDIOP0 PC27 SPI1_NPCS2 TWCK1 ISI_D10 – SPI1_NPCS2/TWCK1

VDDIOP0 PC28 SPI1_NPCS3 PWMFI0 ISI_D9 – SPI1_NPCS3/ISI_D9

VDDIOP0 PC29 URXD0 PWMFI2 ISI_D8 – URXD0/ISI_D8

VDDIOP0 PC30 UTXD0 ISI_PCK – – UTXD0/ISI_PCK

VDDIOP0 PC31 FIQ PWMFI1 – IRQ_PMIC –

Table 4-25. PIO D Pin Assignment and Signal Description


Extended Function

VDDIOP1 PD0 MCI0_CDA – – MCI0_CDA –

VDDIOP1 PD1 MCI0_DA0 – – MCI0_DA0 –




VDDIOP1 PD5 MCI0_DA4 TIOA0 PWMH2 MCI0_DA4 –

VDDIOP1 PD6 MCI0_DA5 TIOB0 PWML2 MCI0_DA5 –

VDDIOP1 PD7 MCI0_DA6 TCLK0 PWMH3 MCI0_DA6 –

Table 4-24. PIO C Pin Assignment and Signal Description (Continued)




VDDIOP1 PD8 MCI0_DA7 PWML3 – MCI0_DA7 –

VDDIOP1 PD9 MCI0_CK – – MCI0_CK –

VDDIOP1 PD10 SPI0_MISO – – SPI0_MISO SPI0_MISO

VDDIOP1 PD11 SPI0_MOSI – – SPI0_MOSI SPI0_MOSI

VDDIOP1 PD12 SPI0_SPCK – – SPI0_SPCK SPI0_SPCK

VDDIOP1 PD13 SPI0_NPCS0 – – SPI0_NPCS0 –

VDDIOP1 PD14 SCK0 SPI0_NPCS1 CANRX0 – SCK0/SPI0_NPCS0/CANRX0

VDDIOP1 PD15 CTS0 SPI0_NPCS2 CANTX0 – CST0/SPI0_NPCS2/CANTX0

VDDIOP1 PD16 RTS0 SPI0_NPCS3 PWMFI3 – SPI0_NPCS3

VDDIOP1 PD17 RXD0 – – – RXD0

VDDIOP1 PD18 TXD0 – – – TXD0

VDDIOP1 PD19 ADTRG – – – ADTRG (HSYNC)

VDDANA PD20 AD0 – – – AD0/LCD TSC




VDDANA PD24 AD4 – – – AD4






VDDANA PD30 AD10 PCK0 – -- AD10/PCK0

VDDANA PD31 AD11 PCK1 – – AD11/PCK1

Table 4-26. PIO E Pin Assignment and Signal Description



VDDIOM PE0 A0/NBS0 – – MCI0_CD –

VDDIOM PE1 A1 – – MCI1_CD –

VDDIOM PE2 A2 – – PWR_MCI0 –

VDDIOM PE3 A3 – – EN5V_USBB –

VDDIOM PE4 A4 – – EN5V_USBC –

VDDIOM PE5 A5 – – OVCUR_USB –

VDDIOM PE6 A6 – – – RST_LCD

Table 4-25. PIO D Pin Assignment and Signal Description (Continued)


Extended Function


VDDIOM PE7 A7 – – – IRQ1 / ChgMXT

VDDIOM PE8 A8 – – – IRQ2/ChgQT

VDDIOM PE9 A9 – – VBUS_SENSE A9

VDDIOM PE10 A10 – – – A10





VDDIOM PE15 A15 SCK3 – – A15/SCK3

VDDIOM PE16 A16 CTS3 – – A16/CTS3

VDDIOM PE17 A17 RTS3 – – A17/RTS3

VDDIOM PE18 A18 RXD3 – – A18/RXD3

VDDIOM PE19 A19 TXD3 – – A19/TXD3

VDDIOM PE20 A20 SCK2 – – A20/SCK2

VDDIOM PE21 A21/NANDALE – – A21/NANDALE –

VDDIOM PE22 A22/NANDCLE – – A22/NANDCLE –

VDDIOM PE23 A23 CTS2 – 1-Wire / User LED A23/1-Wire/CTS2

VDDIOM PE24 A24 RTS2 – Power LED A24/RTS2

VDDIOM PE25 A25 RXD2 – – A25/RXD2

VDDIOM PE26 NCS0 TXD2 – – NCS0/TXD2

VDDIOM PE27 NCS1 TIOA2 LCDDAT22 – LCDDAT22

VDDIOM PE28 NCS2 TIOB2 LCDDAT23 LCDDAT23

VDDIOM PE29 NWR1/NBS1 TCLK2 – USER_PB NWR1/NBS1/TCLK2

VDDIOM PE30 NWAIT – – nPBSTA_PMIC –

VDDIOM PE31 IRQ PWML1 – – IRQ/PWML1

Table 4-26. PIO E Pin Assignment and Signal Description (Continued)




4.4 SAMA5D3 Xplained Board SchematicsThis section contains the following schematics: General information Block Diagram PIO Multiplexing Table Power Supplies SAMA5D3 Device and USB Interfaces DDR2 Memory NAND Flash and Optional Memories SD and Micro-SD Interfaces Gigabit Ethernet Ethernet 10/100 LCD, JTAG, DEBUG and Extended Connectors


Figure 4-38. General information

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

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R.

SC

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V.

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T

INIT

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Title

& R

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tory

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5D

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ine

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AT

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tory

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ine

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RE

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AT

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TE

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R.

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ALE

1/1

RE

V.

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INIT

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ITAA

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vA

1 11

A

XX

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X-X

XP

Pn

XX

X

Title

& R

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ion

His

tory

27

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p-1

3

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5D

3 X

pla

ine

d

Em

be

st

19

-Fe

b-1

4X

XX

XX

-XX

X-X

X

Schematic: SAMA5D3 Xplained

SHEET

SHEET NAME

01

02

03

04

05

06

07

08

09

Title & Revision History

Block Diagram

Power Supply

SAMA5D3x-I & USB

SAMA5D3x-II & NAND

HSMCI

Ethernet_ETH1_10/100

Connectors

SAMA5D3x-II & DDR2

10

11

Ethernet_ETH0_10/100/1000

PIO Assignment

NO

IT

PI

RC

SE

DE

TA

DREVISION

19 Feb 2014

SAMA5D3 Xplained RevA

Official Release


Figure 4-39. Block diagram

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

2 11

A

XX

-XX

X-X

XP

Pn

XX

X

Blo

ck D

iag

ram

27

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p-1

3

SA

MA

5D

3 X

pla

ine

d

19

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b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

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ITAA

Re

vA

2 11

A

XX

-XX

X-X

XP

Pn

XX

X

Blo

ck D

iag

ram

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

2 11

A

XX

-XX

X-X

XP

Pn

XX

X

Blo

ck D

iag

ram

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

PIO A,...E

PIO A,...E

ATMEL

SAMA5D36

CORTEX(R)-A5 PROCESSOR

Extention boards connectors

EBI

2/4Gb

DDR2

SDRAM

2Gb

NAND

FLASH

SERIAL

DATA

FLASH

Micro SD

CARD

10/100/1000

FAST ETHERNET

ETH0

Power rails

VBAT

ANALOG Reference

10/100

FAST ETHERNET

ETH1

USB

DEVICE

USB

Host

x2

Single

PMU

Solution

5V INPUT

USB A,B,C

SD

CARD

Reset

Force PwrOn

Push

Buttons

LCD

Connector

JTAG & DBGU

JTAG

DBGU

USER

LEDS

PIO

5V & 3V3


Figure 4-40. PIO Multiplexing Table

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

3 11

A

XX

-XX

X-X

XP

Pn

XX

X

PIO

Assig

nm

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t

27

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p-1

3

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MA

5D

3 X

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XX

XX

X-X

XX

-XX

RE

VD

AT

EM

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IF.

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S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

3 11

A

XX

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X-X

XP

Pn

XX

X

PIO

Assig

nm

en

t

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

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19

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mb

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XX

XX

X-X

XX

-XX

RE

VD

AT

EM

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S.

DA

TE

VE

R.

SC

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Re

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3 11

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XX

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Assig

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27

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5D

3 X

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ine

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XX

XX

X-X

XX

-XX

LC

DD

AT

0

LC

DD

AT

1

LC

DD

AT

2

LC

DD

AT

3

LC

DD

AT

4

LC

DD

AT

5

LC

DD

AT

6

LC

DD

AT

7

LC

DD

AT

8

LC

DD

AT

9

LC

DD

AT

10

LC

DD

AT

11

LC

DD

AT

12

LC

DD

AT

13

LC

DD

AT

14

LC

DD

AT

15

MC

I0_

CD

A

MC

I0_

DA

0

MC

I0_

DA

1

MC

I0_

DA

2

MC

I0_

DA

3

MC

I0_

DA

4

MC

I0_

DA

5

MC

I0_

DA

6

LC

DP

WM

LC

DD

ISP

LC

DV

SY

NC

LC

DH

SY

NC

LC

DP

CK

LC

DD

EN

MC

I0_

DA

7

GT

XC

K

GT

X0

GR

X0

GM

DC

GM

DIO

G1

25

CK

MC

I1_

CD

A

MC

I1_

DA

0

MC

I1_

DA

1

MC

I1_

DA

2

MC

I1_

DA

3

MC

I1_

CK

SC

K1

CT

S1

RT

S1

RX

D1

TX

D1

DR

XD

DT

XD

ET

X0

ET

X1

ER

X0

ER

X1

ET

XE

N

EC

RS

DV

LC

DD

AT

17

LC

DD

AT

16

LC

DD

AT

21

/PC

K2

EC

RS

DV

ER

EF

CK

EM

DC

EM

DIO

LC

DD

AT

20

LC

DD

AT

19

LC

DD

AT

18

TK

0

TF

0

TD

0

SP

I1_N

PC

S2/T

WC

K1/IS

I_D

10

SP

I1_N

PC

S3/IS

I_D

9

UR

XD

0/I

SI_

D8

UT

XD

0/I

SI_

PC

K

IRQ

_P

MIC

MC

I0_

CK

SP

I0_

MIS

O

SP

I0_

MO

SI

SP

I0_

SP

CK

SP

I0_

NP

CS

0

SC

K0

/CA

NR

X0

CT

S0

/CA

NT

X0

SP

I0_

NP

CS

3

RX

D0

TX

D0

AD

TR

G

AD

0

MC

I0_

CD

MC

I1_

CD

PW

R_

MC

I0

EN

5V

_U

SB

B

EN

5V

_U

SB

C

OV

CU

R_

US

B

RS

T_

LC

D

IRQ

1

IRQ

2

VB

US

_S

EN

SE

/A9

A1

6/C

TS

3

A2

2/N

AN

DC

LE

1-W

ire/U

ser

led1/A

23/C

TS

2

Po

we

r le

d/A

24

/RT

S2

NC

S0

/TX

D2

LC

DD

AT

22

LC

DD

AT

23

NW

R1

/NB

S1

/TC

LK

2

ST

A_P

MIC

AD

TR

G/P

WM

L1

LCD

VC

C

VC

C

GN

D

LC

DD

ISP

LC

DV

SY

NC

LC

DD

EN

SP

I0_

MIS

O/A

D2

_Y

P

SP

I0_

SP

CK

/AD

0_

XP

LC

DD

AT

0

Re

se

t

IRQ

1

TW

CK

1

LC

DP

WM

LC

DH

SY

NC

LC

DP

CK

SP

I0_M

OS

I/A

D1_X

M

SP

I0_

NP

CS

3/A

D3

_Y

M

GN

D

ISI_

D5

ISI_

D3

ISI_

D1

ISI_

D7

ISI_

HS

YN

C/U

TX

D1

ISI_

VS

YN

C/U

RX

D1

ISI_

D6

ISI_

D4

ISI_

D2

ISI_

D0

JUMPER DESCRIPTION

JP

2

PA

RT

FU

NC

TIO

ND

EF

AU

LT

JP

3

JP

4

JP

5

JP

6

JP

1S

HO

RT

CL

OS

E

I_IO

M M

easure

ment

CS

Se

ria

l fla

sh

me

mo

ry

CS

Na

nd

fla

sh

me

mo

ryC

LO

SE

I_IO

P M

ea

su

rem

en

t

I_C

OR

E M

easure

ment

I_IO

DD

R M

ea

su

rem

en

t

PD

31

PA

18

PA

17

PA

16

PIO

A

PA

19

PA

20

PA

21

PA

26

PA

27

PA

22

PA

23

PA

24

PA

28

PA

29

PA

30

PA

25

PA

31

PB

0

PIO

B

PB

4

PB

3

PB

2

PB

1

PB

7

PB

6

PB

5

PB

10

PB

11

PB

12

PB

8

PB

13

PB

14

PB

15

PB

9

PIO

B

PB

18

PB

17

PB

16

PC

1

PC

0

PIO

C

PC

5

PC

4

PC

3

PC

2

PC

9

PC

8

PC

7

PC

6

PC

13

PC

12

PC

11

PC

10

PC

15

PC

14

PC

17

PC

16

PIO

C

PC

21

PC

20

PC

19

PC

18

PC

25

PC

24

PC

23

PC

22

PC

29

PC

28

PC

27

PC

26

PC

31

PC

30

PD

17

PD

16

PIO

D

PD

21

PD

20

PD

19

PD

18

PIO

MU

XIN

G

US

AG

EU

SA

GE

US

AG

EU

SA

GE

US

AG

EU

SA

GE

US

AG

E

PE

0

PIO

E

PE

4

PE

3

PE

2

PE

1

PE

7

PE

6

PE

5

PE

11

PE

10

PE

9

PE

8

US

AG

E

PE

15

PE

14

PE

13

PE

12

PIO

EU

SA

GE

PD

22

PD

26

PD

25

PD

24

PD

23

PD

30

PD

29

PD

28

PD

27

PB

21

PB

19

PB

26

PB

24

PB

23

PB

22

PB

28

PB

29

PB

27

PB

25

PB

31

PB

20

PB

30

PE

17

PE

16

PE

21

PE

20

PE

19

PE

18

PE

25

PE

23

PE

24

PE

22

PE

28

PE

26

PE

27

PE

31

PE

29

PE

30

PA

12

PA

11

PA

10

PA

9

PA

8

PA

7

PA

6

PA

5

PA

4

PA

3

PA

2

PA

1

PA

0

PIO

A

PA

15

PA

14

PA

13

RK

0

RF

0

RD

0

SP

I1_

MIS

O

SP

I1_

MO

SI

SP

I1_

SP

CK

SP

I1_

NP

CS

0

SP

I1_

NP

CS

1/T

WD

1/I

SI_

D1

1

A2

5/R

XD

2

PD

0

PD

1

PD

2

PD

8

PD

3

PD

6

PD

5

PD

4

PIO

D

PD

13

PD

12

PD

7

PD

10

PD

9

PD

15

PD

11

PD

14

US

AG

E

GT

X1

GT

X2

GT

X3

GR

X1

GR

X2

GR

X3

GT

XE

N

INT

_G

ET

H

GR

XC

K

INT

_E

TH

GR

XE

R

CA

NR

X1

CA

NT

X1

AD

1

AD

2

AD

3

AD

4

AD

5

AD

6

AD

7

AD

8

AD

9

AD

10

/PC

K0

/PC

K1

A1

0

A1

1

A1

2

A1

3

A1

4

A1

5/S

CK

3

A1

7/R

TS

3

A1

8/R

XD

3

A1

9/T

XD

3

A2

0/S

CK

2

A2

1/N

AN

DA

LE

1 2 9 10

3 4 5 6 7 8 11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

ID_

SY

S

LC

DD

AT

1

LC

DD

AT

2

LC

DD

AT

3

LC

DD

AT

4

LC

DD

AT

5

LC

DD

AT

6

LC

DD

AT

7

GN

D

GN

D

LC

DD

AT

8

LC

DD

AT

9

LC

DD

AT

10

LC

DD

AT

11

GN

D

LC

DD

AT

12

LC

DD

AT

13

LC

DD

AT

14

LC

DD

AT

15

GN

D

LC

DD

AT

16

LC

DD

AT

17

LC

DD

AT

18

LC

DD

AT

19

GN

D

LC

DD

AT

20

LC

DD

AT

21

LC

DD

AT

22

LC

DD

AT

23

GN

D

IRQ

2

TW

D1

SH

OR

T

SH

OR

T

SH

OR

T


Figure 4-41. Power supplies

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

BP2

BP1

BP

1

BP

2

5V

_M

AIN

VD

DC

OR

E

VD

DIO

P1

VD

DIO

P0

VD

DA

NA

VD

DP

LL

A

VD

DO

SC

VD

DIO

DD

R

VD

DIO

M

AV

DD

L_

PL

L

DV

DD

L

AV

DD

L

FU

SE

_2

V5

5V

_M

AIN

3V

3

3V

3

VD

DU

TM

IC

3V

3

5V

_M

AIN

TW

CK

_P

MIC

[7]

TW

D_

PM

IC[7

]

NR

ST

[5,9

,10

,11

]

SH

DN

[5]

PC

31

[7]

WK

UP

[5]

Vb

us

[5]

5V

_E

xt

[11

]

PE

30

[7]

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

4 11

A

XX

-XX

X-X

XP

Pn

XX

X

Po

we

r S

up

ply

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

4 11

A

XX

-XX

X-X

XP

Pn

XX

X

Po

we

r S

up

ply

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

4 11

A

XX

-XX

X-X

XP

Pn

XX

X

Po

we

r S

up

ply

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

(1V2)

(1V8)

(3V3)

(3V3)

(2V5)

RES

ETW

AK

UP

orFo

rce

Pow

er O

N

Auto

PW

RO

N(o

ption)

Pla

ce

TP

6 T

P7

to

Bo

tto

m

PC27

PC26

R1

R2

R3

R1

75

R1

76

R1

77

0R

08

05

C1

01

00

nF

C1

01

00

nF

L9

2.2

uH

L9

2.2

uH

R1

4

49

.9K

R1

4

49

.9K

C2

12

.2u

FC

21

2.2

uF

BP

2B

P2

C4

1u

FC

41

uF

C1

31

0u

FC

13

10

uF

R1

60

RR

16

0R

C2

32

.2u

FC

23

2.2

uF

R1

72

R2

R1

72

R2

C2

01

00

nF

C2

01

00

nF

MN

1A

CT

88

65

MN

1A

CT

88

65

GNDP129

GNDA2

INL

45

5V

P1

31

INL

67

6

GNDP228

VP

22

6

GNDP314

EXPAD33

VP

31

6

NC

22

5

VD

DR

EF

23

nR

ST

01

1

nIR

Q1

2

nP

BS

TA

T1

3

VS

EL

20

NC

11

8

PW

RH

LD

10

PW

RE

N1

7

SC

L2

1

SD

A2

2

RE

FB

P3

2

nP

BIN

9

SW

13

0

OU

T1

1

OU

T2

24

SW

22

7

SW

31

5

OU

T3

19

OU

T4

3

OU

T5

4

OU

T6

7

OU

T7

8

R1

75

0R

R1

75

0R

C2

4.7

uF

C2

4.7

uF

JP

1D

NP

(JU

MP

ER

)JP

1D

NP

(JU

MP

ER

)

12

TP

7S

MD

TP

7S

MD

Q1

IRL

ML

25

02

Q1

IRL

ML

25

02

1

3 2

C5

1u

FC

51

uF

R1

9

10

0K

1%

R1

9

10

0K

1%

C1

4.7

uF

C1

4.7

uF

R1

5

0R

R1

5

0R

J2

DN

P(D

C J

AC

K)

J2

DN

P(D

C J

AC

K)3 12

L1

11

80

oh

m a

t 1

00

MH

zL

11

18

0o

hm

at

10

0M

Hz

12

L8

18

0o

hm

at

10

0M

Hz

L8

18

0o

hm

at

10

0M

Hz

12

C1

84

7n

FC

18

47

nF

C2

22

.2u

FC

22

2.2

uF

JP

3D

NP

(JU

MP

ER

)JP

3D

NP

(JU

MP

ER

)

12

R1

10

RR

11

0R

TP

2S

MD

TP

2S

MD

C2

64

.7u

FC

26

4.7

uF

C6

1u

FC

61

uF

R6

1.5

K 1

%R

61

.5K

1%

L5

2.2

uH

L5

2.2

uH

JP

4D

NP

(JU

MP

ER

)JP

4D

NP

(JU

MP

ER

)

12

C2

51

00

nF

C2

51

00

nF

L6 60

mA

10

uH

L6 60

mA

10

uH

C3

4.7

uF

C3

4.7

uF

JP

2D

NP

(JU

MP

ER

)JP

2D

NP

(JU

MP

ER

)

12

R7

1.5

K 1

%R

71

.5K

1%

C1

14

.7u

FC

11

4.7

uF

R5

2R

2R

52

R2

R8

10

KR

81

0K

R4

1R

R4

1R

C1

71

00

nF

C1

71

00

nF

C9

10

uF

C9

10

uF

L7

2.2

uH

L7

2.2

uH

C1

91

00

nF

C1

91

00

nF

R1

76

DN

P(0

R)

R1

76

DN

P(0

R)

TP

6S

MD

TP

6S

MD

L1

2

60

mA

10

uH

L1

2

60

mA

10

uH

C7

4.7

uF

C7

4.7

uF

D4

P4

SM

AJ5

.0A

D4

P4

SM

AJ5

.0A

12

R1

86

0R

R1

86

0R

L3

18

0o

hm

at

10

0M

Hz

L3

18

0o

hm

at

10

0M

Hz

12

L1

18

0o

hm

at

10

0M

Hz

L1

18

0o

hm

at

10

0M

Hz

12

R1

24

9.9

KR

12

49

.9K

L1

01

80

oh

m a

t 1

00

MH

zL

10

18

0o

hm

at

10

0M

Hz

12

C1

51

0u

FC

15

10

uF

TP

1S

MD

TP

1S

MD

C1

41

00

nF

C1

41

00

nF

R1

81

KR

18

1K

R3

DN

P(0

R)

R3

DN

P(0

R)

C1

30

10

nF

C1

30

10

nF

C1

61

0u

FC

16

10

uF

C8

10

uF

C8

10

uF

R9

DN

P(0

R)

R9

DN

P(0

R)

C2

42

.2u

FC

24

2.2

uF

R1

30

RR

13

0R

R1

02

R2

R1

02

R2

L4 60

mA

10

uH

L4 60

mA

10

uH

R1

0R

R1

0R

L2

18

0o

hm

at

10

0M

Hz

L2

18

0o

hm

at

10

0M

Hz

12

BP

1B

P1

C1

21

0u

FC

12

10

uF

R2

DN

P(0

R)

R2

DN

P(0

R)

R1

77

DN

P(0

R)

R1

77

DN

P(0

R)


Figure 4-42. SAMA5D3 Device and USB Interfaces

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

HH

SD

PC

HH

SD

MA

HH

SD

PA

HH

SD

MB

HH

SD

PB

HH

SD

MC

TD

IT

MS

TC

KT

DO

NT

RS

TN

RS

T

SH

DN

WK

UP

PE

23

PE

24

VD

DB

U

HH

SD

MC

HH

SD

PC

HH

SD

MB

HH

SD

PB

AD

VR

EF

5V

_U

SB

B5

V_

US

BC

5V

_U

SB

B

5V

_U

SB

C

VD

DIO

P1

VD

DIO

P0

VD

DIO

M

VD

DIO

P0

VD

DO

SC

FU

SE

_2

V5

3V

3

GN

DU

TM

IG

ND

UT

MI

GN

DU

TM

I

3V

3

3V

3

VD

DP

LL

A

VD

DIO

DD

R

VD

DC

OR

E

VD

DU

TM

IC

VD

DA

NA

EA

RT

H_

US

B

5V

_M

AIN

EA

RT

H_

US

B

EA

RT

H_

US

B_

A

3V

3

EA

RT

H_

US

B_

A

WK

UP

[4]

SH

DN

[4]

PE

[0..

31

][4

,7,8

,11

]

PE

5[7

]

TM

S[1

1]

TC

K[1

1]

TD

O[1

1]

TD

I[1

1]

NR

ST

[4,9

,10

,11

]

AR

EF

[11

]

NT

RS

T[1

1]

VB

at

[11

]

Vb

us

[4]

PE

9[7

,11

]

PE

29

[7,1

1]

PE

4[7

]

PE

3[7

]

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

5 11

A

XX

-XX

X-X

XP

Pn

XX

X

SA

MA

5D

3x-I

& U

SB

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

5 11

A

XX

-XX

X-X

XP

Pn

XX

X

SA

MA

5D

3x-I

& U

SB

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

5 11

A

XX

-XX

X-X

XP

Pn

XX

X

SA

MA

5D

3x-I

& U

SB

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

LED

OV

CU

R_U

SB

USB

HO

ST B

&C

INTE

RFA

CE

USB

DEV

ICE

A IN

TER

FAC

E Ma

x tra

ce

-le

ng

th m

ism

atc

hb

etw

ee

n U

SB

sig

na

ls p

airs

sh

ou

ld b

e n

o g

rea

ter

tha

n 3

.8m

m

90

oh

ms d

iffe

ren

tia

l tr

ace

imp

ed

an

ce

R&

Cas c

lose a

s p

ossib

le

(Super)

-Capacitor

energ

y s

tora

ge

Ro

utin

g to

p o

r b

ott

om

Ro

utin

g U

SB

A c

op

pe

r p

lan

for

GN

DU

TM

I co

ve

ra

ll U

SB

co

mp

om

en

ts

top/b

ot

top/b

ot

top/b

ot

top/b

ot

(VB

US

_S

EN

SE

)

USE

R B

UTT

ON

J7

_U

SB

_A

_U

pJ7

_U

SB

_B

_D

ow

nE

N5V

_U

SB

C

EN

5V

_U

SB

B

Pla

ce

TP

5 to

Bo

tto

m

Pla

ce

TP

4 to

Bo

tto

m

Popula

te R

185 if

no S

uper

Cap (

C41)

R1

85

1.5

K 1

%

R1

85

1.5

K 1

%

R2

51

0K

R2

51

0K

BP

3B

P3

C5

01

00

nF

C5

01

00

nF

C6

01

0p

FC

60

10

pF

C3

2

10

0n

F

C3

2

10

0n

F

R2

9D

NP

(0R

)R

29

DN

P(0

R)

Y2

32

.76

8K

Hz C

L=

12

.5p

F

Y2

32

.76

8K

Hz C

L=

12

.5p

F

1

23

4

D1

BA

T5

4C

D1

BA

T5

4C

12

3

TP

5

SM

D

TP

5

SM

D

C4

01

uF

C4

01

uF

C4

92

0p

FC

49

20

pF

C5

21

00

nF

C5

21

00

nF

C5

41

00

nF

C5

41

00

nF

C4

81

00

nF

C4

81

00

nF

C5

32

0p

FC

53

20

pF

R2

7

20

0K

R2

7

20

0K

VBUS DM DP ID

GND

J6

UB

AF

-10

15

P

VBUS DM DP ID

GND

J6

UB

AF

-10

15

P

1 2 3 4 5

7 6

8

R2

8

0R

R2

8

0R

MN

3

SP

25

26

A-2

E

MN

3

SP

25

26

A-2

E

EN

A1

FLG

A2

EN

B4

OU

TA

8

GN

G6

FLG

B3

IN7

OU

TB

5

TP

4

SM

D

TP

4

SM

D

C3

81

00

nF

C3

81

00

nF

C4

31

00

nF

C4

31

00

nF

D3

RE

D

D3

RE

D

C5

91

00

nF

C5

91

00

nF

C3

51

00

nF

C3

51

00

nF

C4

1

DN

P(0

.2F

/3V

3)

C4

1

DN

P(0

.2F

/3V

3)

C2

81

00

nF

C2

81

00

nF

R3

44

70

RR

34

47

0R

R2

41

00

K 1

%R

24

10

0K

1%

MN

2H

SA

MA

5D

3x_

BG

A3

24

MN

2H

SA

MA

5D

3x_

BG

A3

24

GNDCORE_1A16

VDDCORE_1C5

VDDCORE_2C7

GNDCORE_2C9

VD

DIO

DD

R_

1D

13

VDDCORE_3D14

GNDIODDR_1E14

GNDIODDR_2F10

GNDIODDR_3F13

VD

DIO

DD

R_

2F

14

GNDIODDR_4F15

VDDIOP0_1G7

VD

DIO

DD

R_

3G

10

VD

DIO

DD

R_

4G

13

VD

DIO

DD

R_

5H

11

GNDIODDR_5H14

GNDIOP_1J7

GNDIOM_1J11

GNDANAL4

AD

VR

EF

L5

VD

DA

NA

L6

VDDIOP1_1L11

VDDIOP1_2M4

TD

OM

11

TM

SN

10

GNDIOP_2N11

GNDCORE_3N13

GNDFUSEP4

TC

KP

9

GNDPLLP10

NT

RS

TP

11

GNDUTMI_1R12

VD

DF

US

ER

3

TD

IR

8

VD

DP

LL

AR

10

VB

GR

11

VD

DIO

M_

1P

12

VDDCORE_4T7

GNDCORE_4T8

JT

AG

SE

LT

9

WK

UP

T1

0

GNDOSCT11

SH

DN

T1

2

GNDBUT13

GNDCORE_5T14

VDDCORE_5T15

VD

DIO

M_

2T

16

GNDIOM_2T17

GNDIOP_3U7

XIN

U8

BM

SU

9

VD

DO

SC

U1

1

VD

DU

TM

IIU

13

TS

TU

15

XIN

32

U1

6

VDDCORE_6U17

VDDCORE_7V7

XO

UT

V8

NR

ST

V9

VDDIOP0_2V11

VD

DU

TM

ICV

13

VDDBUV15

XO

UT

32

V1

6

GNDCORE_6V17

GNDIOP_4E5

HH

SD

MA

V1

0

HH

SD

PA

U1

0

HH

SD

MC

V1

4

HH

SD

PC

U1

4

HH

SD

PB

U1

2H

HS

DM

BV

12

DIB

NU

6

DIB

PV

6

R2

31

.5K

1%

R2

31

.5K

1%

L2

11

80

oh

m a

t 1

00

MH

zL

21

18

0o

hm

at

10

0M

Hz

12

C6

11

00

nF

C6

11

00

nF

C2

9

10

0n

F

C2

9

10

0n

F

C2

7

10

nF

C2

7

10

nF

C5

62

0p

FC

56

20

pF

R3

31

00

K 1

%R

33

10

0K

1%

C4

41

00

nF

C4

41

00

nF

Y1

12

MH

z C

L=

15

pF

Y1

12

MH

z C

L=

15

pF

1

2 3

4

R2

11

00

K 1

%R

21

10

0K

1%

C3

0

10

0n

F

C3

0

10

0n

F

C3

71

00

nF

C3

71

00

nF

C4

71

00

nF

C4

71

00

nF

C4

21

00

nF

C4

21

00

nF

C3

41

00

nF

C3

41

00

nF

R2

2D

NP

(10

0K

)R

22

DN

P(1

00

K)

C6

41

00

nF

C6

41

00

nF

Q2

IRL

ML

25

02

Q2

IRL

ML

25

02

1

32

R3

05

.62

K 1

%R

30

5.6

2K

1%

R3

24

70

RR

32

47

0R

C5

71

00

nF

C5

71

00

nF

C3

61

00

nF

C3

61

00

nF

L1

31

80

oh

m a

t 1

00

MH

zL

13

18

0o

hm

at

10

0M

Hz

12

C4

61

00

nF

C4

61

00

nF

C3

91

00

nF

C3

91

00

nF

C6

21

0u

FC

62

10

uF

C6

31

00

nF

C6

31

00

nF

C3

31

00

nF

C3

31

00

nF

C5

51

00

nF

C5

51

00

nF

L1

51

80

oh

m a

t 1

00

MH

zL

15

18

0o

hm

at

10

0M

Hz

12

R2

01

00

RR

20

10

0R

C3

1

10

0n

F

C3

1

10

0n

F

D2

BL

UE

D2

BL

UE

C5

81

00

nF

C5

81

00

nF

A B

J7

US

B8

S-A

R2

HF

-NB

W-S

2

A B

J7

US

B8

S-A

R2

HF

-NB

W-S

2

5 86 7

91

0

1 2 3 4

111

2

C4

51

00

nF

C4

51

00

nF

R3

10

RR

31

0R

C5

12

0p

FC

51

20

pF

L1

41

80

oh

m a

t 1

00

MH

zL

14

18

0o

hm

at

10

0M

Hz

12

R2

61

00

K 1

%R

26

10

0K

1%

C6

51

0u

FC

65

10

uF


Figure 4-43. DDR2 Memory

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DD

R_

VR

EF

DD

R_

A8

DD

R_

D9

DD

R_

D1

0D

DR

_D

11

DD

R_

D1

2D

DR

_D

13

DD

R_

D1

5D

DR

_D

14

DD

R_

A1

DD

R_

A9

DD

R_

A2

DD

R_

D2

DD

R_

A1

0

DD

R_

A3

DD

R_

A1

1

DD

R_

A4

DD

R_

A1

2

DD

R_

A5

DD

R_

D1

DD

R_

VR

EF

DD

R_

D0

DD

R_

A6

DD

R_

D4

DD

R_

D3

DD

R_

A7

DD

R_

D6

DD

R_

D5

DD

R_

D7

DD

R_

D8

DD

R_

A0

DD

R_

A8

DD

R_

D2

7D

DR

_D

26

DD

R_

D2

5

DD

R_

D3

1

DD

R_

D2

9D

DR

_D

28

DD

R_

D3

0

DD

R_

A1

DD

R_

A9

DD

R_

A2

DD

R_

A1

0

DD

R_

D1

8D

DR

_A

3

DD

R_

A1

1

DD

R_

A4

DD

R_

A1

2

DD

R_

A5

DD

R_

VR

EF

DD

R_

D1

7D

DR

_D

16

DD

R_

A6

DD

R_

D1

9D

DR

_D

20

DD

R_

D2

2D

DR

_A

7D

DR

_D

23

DD

R_

D2

1

DD

R_

D2

4

DD

R_

A0

DD

R_

DQ

M0

DD

R_

DQ

S1

DD

R_

DQ

S0

DD

R_

CS

DD

R_

BA

0D

DR

_B

A1

DD

R_

BA

2

DD

R_

CK

E

DD

R_

WE

DD

R_

CL

K

DD

R_

RA

S

DD

R_

CL

KN

DD

R_

CA

S

DD

R_

DQ

M2

DD

R_

DQ

S2

DD

R_

DQ

S3

DD

R_

CS

DD

R_

BA

0D

DR

_B

A1

DD

R_

BA

2

DD

R_

WE

DD

R_

CK

E

DD

R_

RA

S

DD

R_

CL

K

DD

R_

CA

S

DD

R_

CL

KN

DD

R_

A1

3

DD

R_

DQ

M1

DD

R_

DQ

M3

DD

R_

A1

3

DD

R_

A1

3

DD

R_

DQ

M2

DD

R_

DQ

M3

DD

R_

DQ

S1

DD

R_

DQ

S0

DD

R_

D1

2D

DR

_D

13

DD

R_

D0

DD

R_

D1

DD

R_

D2

DD

R_

D3

DD

R_

D4

DD

R_

D5

DD

R_

D6

DD

R_

D7

DD

R_

D8

DD

R_

D9

DD

R_

D1

0D

DR

_D

11

DD

R_

A1

2

DD

R_

D2

6D

DR

_D

27

DD

R_

D1

4D

DR

_D

15

DD

R_

D1

6D

DR

_D

17

DD

R_

D1

8D

DR

_D

19

DD

R_

D2

0D

DR

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21

DD

R_

D2

2D

DR

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23

DD

R_

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4D

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25

DD

R_

DQ

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R_

DQ

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R_

D3

0D

DR

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31

DD

R_

D2

8D

DR

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29

DD

R_

BA

0D

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R_

BA

2

DD

R_

A1

DD

R_

CK

ED

DR

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LK

DD

R_

CL

KN

DD

R_

A0

DD

R_

A2

DD

R_

A3

DD

R_

RA

SD

DR

_C

AS

DD

R_

VR

EF

DD

R_

A4

DD

R_

A5

DD

R_

A6

DD

R_

CS

DD

R_

WE

DD

R_

A8

DD

R_

A9

DD

R_

A1

0D

DR

_A

11

DD

R_

DQ

M0

DD

R_

DQ

M1

DD

R_

A7

VD

DIO

DD

R

VD

DIO

DD

RV

DD

IOD

DR

VD

DIO

DD

R

VD

DIO

DD

R

VD

DIO

DD

R

DD

R_

A[0

..1

3]

DD

R_

D[0

..3

1]

DD

R_

A[0

..1

3]

DD

R_

D[0

..3

1]

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

6 11

A

XX

-XX

X-X

XP

Pn

XX

X

SA

MA

5D

3x-I

I &

DD

R2

27

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p-1

3

SA

MA

5D

3 X

pla

ine

d

19

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b-1

4E

mb

est

XX

XX

X-X

XX

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RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

6 11

A

XX

-XX

X-X

XP

Pn

XX

X

SA

MA

5D

3x-I

I &

DD

R2

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

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b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

6 11

A

XX

-XX

X-X

XP

Pn

XX

X

SA

MA

5D

3x-I

I &

DD

R2

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

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b-1

4E

mb

est

XX

XX

X-X

XX

-XX

DDR2 SDRAM

Addre

ss, contr

ol and d

ata

tra

ces m

ay n

ot exceed 1

.3 inches (

33.0

mm

).A

ddre

ss, contr

ol and d

ata

tra

ces m

ust be length

-matc

hed to w

ithin

0.1

inch (

2.5

4m

m).

Addre

ss, contr

ol and d

ata

tra

ces m

ust m

atc

h the d

ata

gro

up tra

ce length

s to w

ithin

0.2

5 inches (

6.3

5m

m).

Keep n

ets

as s

hort

as p

ossib

le, th

ere

fore

, D

DR

2 d

evic

es h

ave to b

e p

laced clo

se as p

ossib

le o

f S

AM

A5D

36

The layout E

BI D

DR

2 should

use c

ontr

olle

d im

pedance tra

ces o

f Z

O=

50ohm

chara

cte

ristic im

pedance.

Diffe

rencia

l 100 O

hm

sT

op/B

ottom

Diffe

rencia

l 100 O

hm

sT

op/B

ottom

Diffe

rencia

l 100 O

hm

sT

op/B

ottom

C9

81

00

nF

C9

81

00

nF

C9

91

00

nF

C9

91

00

nF

C7

31

00

nF

C7

31

00

nF

C1

00

10

0n

FC

10

01

00

nF

R4

61

.5K

1%

R4

61

.5K

1%

C6

81

00

nF

C6

81

00

nF

R4

51

RR

45

1R

R3

94

.7K

R3

94

.7K

R4

32

00

R 1

%R

43

20

0R

1%

C9

31

00

nF

C9

31

00

nF

C9

01

00

nF

C9

01

00

nF

C6

91

00

nF

C6

91

00

nF

R4

14

.7K

R4

14

.7K

C9

11

00

nF

C9

11

00

nF

C7

01

00

nF

C7

01

00

nF

C9

71

00

nF

C9

71

00

nF

MT47

H64M

16HR

DDR2

SDR

AM

MN

5

MT47

H64M

16HR

DDR2

SDR

AM

MN

5

A0

M8

A1

M3

A2

M7

A3

N2

A4

N8

A5

N3

A6

N7

A7

P2

A8

P8

A9

P3

A1

0M

2

BA

0L

2

OD

TK

9

DQ

0G

8

DQ

1G

2

DQ

2H

7

DQ

3H

3

DQ

4H

1

DQ

5H

9

DQ

6F

1

DQ

7F

9

UD

QS

B7

UD

QS

A8

LD

MF

3

VD

DJ9

VD

DM

9

VD

DL

J1

VR

EF

J2

VD

DQ

E9

VS

SA

3

VS

SE

3

VD

DQ

A9

VD

DE

1

RF

U1

A2

RF

U2

E2

CK

EK

2

CK

J8

CK

K8

CA

SL

7

RA

SK

7

WE

K3

CS

L8

VD

DQ

C3

VD

DQ

C7

VD

DQ

C9

VS

SQ

D8

VS

SQ

E7

VS

SQ

F2

VS

SQ

F8

VD

DA

1

VS

SJ3

A1

1P

7

BA

1L

3

A1

2R

2

BA

2L

1

VS

SN

1

VS

SD

LJ7

VS

SQ

B2

RF

U3

R3

DQ

8C

8

DQ

9C

2

DQ

10

D7

DQ

11

D3

DQ

12

D1

DQ

13

D9

DQ

14

B1

DQ

15

B9

VD

DR

1

VD

DQ

G1

VD

DQ

G7

VD

DQ

G9

VS

SP

9

VS

SQ

D2

VS

SQ

A7

VS

SQ

B8

VS

SQ

H2

VS

SQ

H8

VD

DQ

G3

VD

DQ

C1

UD

MB

3

LD

QS

E8

LD

QS

F7

RF

U4

R7

A1

3R

8

R4

04

.7K

R4

04

.7K

C7

91

00

nF

C7

91

00

nF

R3

6D

NP

(1K

)R

36

DN

P(1

K)

C7

11

00

nF

C7

11

00

nF

R4

71

.5K

1%

R4

71

.5K

1%

R4

24

.7K

R4

24

.7K

MT47

H64M

16HR

DDR2

SDR

AM

MN

4

MT47

H64M

16HR

DDR2

SDR

AM

MN

4

A0

M8

A1

M3

A2

M7

A3

N2

A4

N8

A5

N3

A6

N7

A7

P2

A8

P8

A9

P3

A1

0M

2

BA

0L

2

OD

TK

9

DQ

0G

8

DQ

1G

2

DQ

2H

7

DQ

3H

3

DQ

4H

1

DQ

5H

9

DQ

6F

1

DQ

7F

9

UD

QS

B7

UD

QS

A8

LD

MF

3

VD

DJ9

VD

DM

9

VD

DL

J1

VR

EF

J2

VD

DQ

E9

VS

SA

3

VS

SE

3

VD

DQ

A9

VD

DE

1

RF

U1

A2

RF

U2

E2

CK

EK

2

CK

J8

CK

K8

CA

SL

7

RA

SK

7

WE

K3

CS

L8

VD

DQ

C3

VD

DQ

C7

VD

DQ

C9

VS

SQ

D8

VS

SQ

E7

VS

SQ

F2

VS

SQ

F8

VD

DA

1

VS

SJ3

A1

1P

7

BA

1L

3

A1

2R

2

BA

2L

1

VS

SN

1

VS

SD

LJ7

VS

SQ

B2

RF

U3

R3

DQ

8C

8

DQ

9C

2

DQ

10

D7

DQ

11

D3

DQ

12

D1

DQ

13

D9

DQ

14

B1

DQ

15

B9

VD

DR

1

VD

DQ

G1

VD

DQ

G7

VD

DQ

G9

VS

SP

9

VS

SQ

D2

VS

SQ

A7

VS

SQ

B8

VS

SQ

H2

VS

SQ

H8

VD

DQ

G3

VD

DQ

C1

UD

MB

3

LD

QS

E8

LD

QS

F7

RF

U4

R7

A1

3R

8

C9

41

00

nF

C9

41

00

nF

C7

81

00

nF

C7

81

00

nF

C7

41

00

nF

C7

41

00

nF

C1

01

4.7

uF

C1

01

4.7

uF

R3

80

RR

38

0R

R4

4

20

0R

1%

R4

4

20

0R

1%

C9

51

00

nF

C9

51

00

nF

C7

51

00

nF

C7

51

00

nF

TP

3

SM

D

TP

3

SM

D

L1

6

10

uH

60

mA

L1

6

10

uH

60

mA

C9

61

00

nF

C9

61

00

nF

R3

70

RR

37

0R

C1

02

10

0n

FC

10

21

00

nF

MN

2F

SA

MA

5D

3x_

BG

A3

24

MN

2F

SA

MA

5D

3x_

BG

A3

24

DD

R_

CA

SA

5

DD

R_

A1

3A

6

DD

R_

A1

1A

7

DD

R_

A7

A8

DD

R_

A2

A9

DD

R_

D3

0A

10

DD

R_

D2

7A

11

DD

R_

CL

KN

A1

2

DD

R_

DQ

SN

3A

13

DD

R_

D2

5A

14

DD

R_

D2

4A

15

DD

R_

DQ

SN

2A

17

DD

R_

D1

9A

18

DD

R_

WE

B5

DD

R_

BA

1B

6

DD

R_

CK

EB

7

DD

R_

A9

B8

DD

R_

A4

B9

DD

R_

A0

B1

0

DD

R_

D2

8B

11

DD

R_

CL

KB

12

DD

R_

DQ

S3

B1

3

DD

R_

D2

3B

14

DD

R_

DQ

M2

B1

5

DD

R_

D1

6B

16

DD

R_

DQ

S2

B1

7

DD

R_

D1

7B

18

DD

R_

CS

C8

DD

R_

A8

C1

0

DD

R_

A1

C1

1

DD

R_

CA

LN

C1

2

DD

R_

VR

EF

C1

3

DD

R_

BA

0E

9

DD

R_

DQ

SN

0D

18

DD

R_

D1

2D

17

DD

R_

D1

4D

16

DD

R_

D2

2D

15

DD

R_

DQ

M3

D1

2

DD

R_

A3

D1

1

DD

R_

A6

D1

0

DD

R_

A1

2D

9

DD

R_

D1

3C

18

DD

R_

D1

5C

17

DD

R_

D2

0C

16

DD

R_

D1

8C

15

DD

R_

D2

1C

14

DD

R_

A5

E1

0

DD

R_

D3

1E

11

DD

R_

D2

6E

12

DD

R_

CA

LP

E1

3

DD

R_

BA

2F

9

DD

R_

A1

0F

11

DD

R_

D2

9F

12

DD

R_

D8

F1

6

DD

R_

D6

F1

7

DD

R_

DQ

SN

1F

18

DD

R_

RA

SG

11

DD

R_

DQ

M0

G1

2

DD

R_

D1

0G

14

DD

R_

D7

G1

5

DD

R_

D4

G1

6D

DR

_D

3G

17

DD

R_

DQ

S1

G1

8

DD

R_

D0

H1

2

DD

R_

D2

H1

3

DD

R_

D5

H1

5

DD

R_

D1

H1

7

DD

R_

DQ

M1

E1

5

DD

R_

D1

1E

16

DD

R_

D9

E1

7

DD

R_

DQ

S0

E1

8

C8

81

00

nF

C8

81

00

nF

C8

01

00

nF

C8

01

00

nF

C8

91

00

nF

C8

91

00

nF

C8

21

00

nF

C8

21

00

nF

R3

5D

NP

(1K

)R

35

DN

P(1

K)

C6

61

00

nF

C6

61

00

nF

C8

31

00

nF

C8

31

00

nF

C8

11

00

nF

C8

11

00

nF

C8

41

00

nF

C8

41

00

nF

C7

61

00

nF

C7

61

00

nF

C1

04

10

0n

FC

10

41

00

nF

C8

61

00

nF

C8

61

00

nF

C8

51

00

nF

C8

51

00

nF

C7

71

00

nF

C7

71

00

nF

C6

71

00

nF

C6

71

00

nF

C8

71

00

nF

C8

71

00

nF

C9

21

00

nF

C9

21

00

nF

C7

21

00

nF

C7

21

00

nF

C1

03

4.7

uF

C1

03

4.7

uF


Figure 4-44. NAND Flash and Optional Memories

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PE

30 M

_E

BI_

D2

PE

21 M

_E

BI_

D3

PE

31 M

_E

BI_

D4

NR

DN

WE

M_

EB

I_D

2

M_

EB

I_D

4M

_E

BI_

D3

M_

EB

I_D

6M

_E

BI_

D7

M_

EB

I_D

5

M_

EB

I_D

0M

_E

BI_

D1

M_

EB

I_D

5

PE

24 M

_E

BI_

D6

M_

EB

I_D

7

PE

25

NR

D

PE

22 M

_E

BI_

D0

PE

27

NW

E

PE

28

PE

29

NA

ND

RD

Y

M_

EB

I_D

1

PE

23

PE

26

PD

13

PD

12

PD

8P

D9

PD

4P

D5

PD

6P

D7

PD

28

PD

16

PD

17

PD

18

PD

10

PD

11

PD

15

PD

14

PD

26

PD

19

PD

23

PD

22

PD

21

PD

20

PD

25

PD

24

PD

29

PD

30

PD

31

PD

27

PD

3P

D2

PD

1P

D0

PB

3P

B2

PB

1P

B0

PB

13

PB

12

PB

8P

B9

PB

4P

B5

PB

6P

B7

PB

28

PB

16

PB

17

PB

18

PB

10

PB

11

PB

15

PB

14

PB

26

PB

19

PB

23

PB

22

PB

21

PB

20

PB

25

PB

24

PB

29

PB

30

PB

31

PB

27

PA

0P

A1

PA

2P

A3

PA

4P

A5

PA

6P

A7

PA

8P

A9

PA

10

PA

11

PA

15

PA

14

PA

13

PA

12

PA

16

PA

17

PA

18

PA

19

PA

23

PA

22

PA

21

PA

20

PA

25

PA

24

PA

28

PA

29

PA

30

PA

31

PA

27

PA

26

PC

3P

C2

PC

1P

C0

PC

13

PC

12

PC

8P

C9

PC

4P

C5

PC

6P

C7

PC

28

PC

16

PC

17

PC

18

PC

10

PC

11

PC

15

PC

14

PC

26

PC

19

PC

23

PC

22

PC

21

PC

20

PC

25

PC

24

PC

29

PC

30

PC

31

PC

27

PE

15

PE

14

PE

16

PE

17

PE

18

PE

19

PE

21

PE

22

PE

1P

E2

PE

3P

E4

PE

5P

E6

PE

7P

E8

PE

9

PE

0

PE

10

PE

11

PE

12

PE

13

PE

20

PC

0

PC

1

PC

2

PC

3

PC

5

PC

6

PC

8

PC

9

PE

23

PD

11

PD

12

PD

10

NC

S3

NC

S3

PD

13

PC

7

PC

4

PC

23

PC

22

PC

24

PA

30

PA

31

PC

26

PC

27

NA

ND

RD

Y

VD

DIO

M

VD

DIO

M

VD

DIO

P1

VD

DIO

P1

VD

DIO

M

3V

3

3V

3

PE

[0..

31

][4

,5,8

,11

]

PD

[0..

31

][8

,11

]

PB

[0..

31

][8

,9,1

0,1

1]

PA

[0..

31

][1

1]

PC

[0..

31

][4

,11

]

J1

5_

Pin

5[1

1]

ET

H1

_P

C1

[10

]

ET

H1

_P

C2

[10

]J1

5_

Pin

4[1

1]

J1

5_

PC

3[1

1]

ET

H1

_P

C3

[10

]

ET

H1

_P

C4

[10

]J1

5_

PC

4[1

1]

J1

8_

PC

5[1

1]

ET

H1

_P

C5

[10

]

ET

H1

_P

C6

[10

]J1

8_

PC

6[1

1]

J1

8_

PC

7[1

1]

ET

H1

_P

C7

[10

]

ET

H1

_P

C8

[10

]J1

8_

PC

8[1

1]

J1

8_

PC

9[1

1]

ET

H1

_P

C9

[10

]

ET

H1

_P

C0

[10

]J1

5_

Pin

6[1

1]

J1

5_

TW

D[1

1]

J1

5_

TW

CK

[11

]

TW

CK

_L

CD

[11

]T

WD

_L

CD

[11

]

TW

CK

_IS

I[1

1]

TW

D_

ISI

[11

]

TW

CK

_P

MIC

[4]

TW

D_

PM

IC[4

]

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

7 11

A

XX

-XX

X-X

XP

Pn

XX

X

SA

MA

5D

3x-I

I &

NA

ND

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

7 11

A

XX

-XX

X-X

XP

Pn

XX

X

SA

MA

5D

3x-I

I &

NA

ND

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

7 11

A

XX

-XX

X-X

XP

Pn

XX

X

SA

MA

5D

3x-I

I &

NA

ND

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

(NA

ND

CE)

(NAN

DCLE

)(N

ANDA

LE)

(NA

ND

CLE

)(N

AN

DA

LE)

(SP

I0_

MIS

0)

(SP

I0_

MO

SI)

OPT

ION

AL

(SP

I0_

SP

CK

)

(SP

I0_

CS

)

R1

50

22

RR

15

02

2R

R1

38

22

RR

13

82

2R

MN

2C

SA

MA

5D

3x_

BG

A3

24

MN

2C

SA

MA

5D

3x_

BG

A3

24

PC

0_

ET

X0

D8

PC

1_

ET

X1

A4

PC

2_

ER

X0

E8

PC

3_

ER

X1

A3

PC

4_

ET

XE

NA

2

PC

5_

EC

RS

DV

F8

PC

6_

ER

XE

RB

3

PC

7_

ER

EF

CK

G8

PC

8_

EM

DC

B4

PC

9_

EM

DIO

F7

PC

10

A1

PC

11

D7

PC

12

C6

PC

13

E7

PC

14

B2

PC

15

F6

PC

16

B1

PC

17

E6

PC

18

C3

PC

19

D6

PC

20

C4

PC

21

D5

PC

22

C2

PC

23

G9

PC

24

C1

PC

25

H1

0

PC

26

H9

PC

27

D4

PC

28

H8

PC

29

G5

PC

30

D3

PC

31

E4

C1

05

10

0n

FC

10

51

00

nF

C1

07

10

0n

FC

10

71

00

nF

R1

55

22

RR

15

52

2R

R5

1

1.5

K 1

%

R5

1

1.5

K 1

%

R1

43

22

RR

14

32

2R

R1

80

3.3

KR

18

03

.3K

MN

2E

SA

MA

5D

3x_

BG

A3

24

MN

2E

SA

MA

5D

3x_

BG

A3

24

PE

0_

A0

/NB

S0

P1

3

PE

1_

A1

R1

4

PE

2_

A2

R1

3

PE

3_

A3

V1

8

PE

4_

A4

P1

4

PE

5_

A5

U1

8

PE

6_

A6

T1

8

PE

7_

A7

R1

5

PE

8_

A8

P1

7

PE

9_

A9

P1

5

PE

10

_A

10

P1

8

PE

11

_A

11

R1

6

PE

12

_A

12

N1

6

PE

13

_A

13

R1

7

PE

14

_A

14

N1

7

PE

15

_A

15

_S

CK

3R

18

PE

16

_A

16

_C

TS

3N

18

PE

17

_A

17

_R

TS

3P

16

PE

18

_A

18

_R

XD

3M

18

PE

19

_A

19

_T

XD

3N

15

PE

20

_A

20

_S

CK

2M

15

PE

21

_A

21

/NA

ND

AL

EN

14

PE

22

_A

22

/NA

ND

CL

EM

17

PE

23

_A

23

_C

TS

2M

13

PE

24

_A

24

_R

TS

2M

16

PE

25

_A

25

_R

XD

2N

12

PE

26

_N

CS

0_

TX

D2

M1

4

PE

27

_N

CS

1_

TIO

A2

M1

2

PE

28

_N

CS

2_

TIO

B2

L1

3

PE

29

_N

WR

1/N

BS

1_

TC

LK

2L

15

PE

30

_N

WA

ITL

14

PE

31

_IR

Q_

PW

ML

1L

16

MN

7 DN

P(D

S2

43

1)

MN

7 DN

P(D

S2

43

1)

IO2

GND1

NC

13

NC

24

NC

35

NC

46

R1

54

22

RR

15

42

2R

R1

60

22

RR

16

02

2R

R1

44

22

RR

14

42

2R

R1

81

3.3

KR

18

13

.3K

MN

8

DN

P(N

25

Q0

32

A1

3E

SE

40

F)

MN

8

DN

P(N

25

Q0

32

A1

3E

SE

40

F)

HO

LD

/DQ

37

GN

D4

VC

C8

S1

C6

DQ

O5

DQ

12

W/V

pp

/DQ

23

MN

11

DN

P(D

S2

8E

05

)

MN

11

DN

P(D

S2

8E

05

)

NC

2

IO1

GN

D3

R1

53

22

RR

15

32

2R

JP

6JU

MP

ER

JP

6JU

MP

ER

12

R1

41

22

RR

14

12

2R

R1

61

22

RR

16

12

2R

MN

2A

SA

MA

5D

3x_

BG

A3

24

MN

2A

SA

MA

5D

3x_

BG

A3

24

PA

0_

LC

DD

AT

0E

3

PA

1_

LC

DD

AT

1F

5

PA

2_

LC

DD

AT

2D

2

PA

3_

LC

DD

AT

3F

4

PA

4_

LC

DD

AT

4D

1

PA

5_

LC

DD

AT

5J1

0

PA

6_

LC

DD

AT

6G

4

PA

7_

LC

DD

AT

7J9

PA

8_

LC

DD

AT

8F

3

PA

9_

LC

DD

AT

9J8

PA

10

_L

CD

DA

T1

0E

2

PA

11

_L

CD

DA

T1

1K

8

PA

12

_L

CD

DA

T1

2F

2

PA

13

_L

CD

DA

T1

3G

6

PA

14

_L

CD

DA

T1

4E

1

PA

15

_L

CD

DA

T1

5H

5

PA

16

_L

CD

DA

T1

6H

3

PA

17

_L

CD

DA

T1

7H

6

PA

18

_L

CD

DA

T1

8H

4

PA

19

_L

CD

DA

T1

9H

7

PA

20

_L

CD

DA

T2

0H

2

PA

21

_L

CD

DA

T2

1J6

PA

22

_L

CD

DA

T2

2G

2

PA

23

_L

CD

DA

T2

3J5

PA

24

_L

CD

PW

MF

1

PA

25

_L

CD

DIS

PJ4

PA

26

_L

CD

VS

YN

CG

3

PA

27

_L

CD

HS

YN

CJ3

PA

28

_L

CD

PC

KG

1

PA

29

_L

CD

DE

NK

4

PA

30

_T

WD

0H

1

PA

31

_T

WC

K0

K3

R1

67

22

RR

16

72

2R

R4

81

00

K 1

%R

48

10

0K

1%

R1

42

22

RR

14

22

2R

R1

66

22

RR

16

62

2R

R1

56

22

RR

15

62

2R

R1

47

22

RR

14

72

2R

R5

01

00

K 1

%R

50

10

0K

1%

R1

57

22

RR

15

72

2R

R1

65

22

RR

16

52

2R

R1

48

22

RR

14

82

2R

JP

5

JU

MP

ER

JP

5

JU

MP

ER

1 2R

16

42

2R

R1

64

22

R

R4

91

00

K 1

%R

49

10

0K

1%

R1

45

22

RR

14

52

2R

R1

79

3.3

KR

17

93

.3K

R1

33

DN

P(2

2R

)R

13

3D

NP

(22

R)

R1

34

22

RR

13

42

2R

MN

2B

SA

MA

5D

3x_

BG

A3

24

MN

2B

SA

MA

5D

3x_

BG

A3

24

PB

0_

GT

X0

T2

PB

1_

GT

X1

N7

PB

2_

GT

X2

T3

PB

3_

GT

X3

N6

PB

4_

GR

X0

P5

PB

5_

GR

X1

T4

PB

6_

GR

X2

R4

PB

7_

GR

X3

U1

PB

8_

GT

XC

KR

5

PB

9_

GT

XE

NP

3

PB

10

_G

TX

ER

R6

PB

11

_G

RX

CK

V3

PB

12

_G

RX

DV

P6

PB

13

_G

RX

ER

V1

PB

14

_G

CR

SR

7

PB

15

_G

CO

LU

3

PB

16

_G

MD

CP

7

PB

17

_G

MD

IOV

2

PB

18

_G

12

5C

KV

5

PB

19

_G

TX

4T

6

PB

20

_G

TX

5N

8

PB

21

_G

TX

6U

4

PB

22

_G

TX

7M

7

PB

23

_G

RX

4U

5

PB

24

_G

RX

5M

8

PB

25

_G

RX

6T

5

PB

26

_G

RX

7N

9

PB

27

V4

PB

28

M9

PB

29

P8

PB

30

M1

0

PB

31

R9

R1

78

3.3

KR

17

83

.3K

R1

46

22

RR

14

62

2R

R5

21

00

K 1

%R

52

10

0K

1%

R1

36

22

RR

13

62

2R

R1

62

DN

P(2

2R

)R

16

2D

NP

(22

R)

R1

51

22

RR

15

12

2R

R1

39

22

RR

13

92

2R

MN

2D

SA

MA

5D

3x_

BG

A3

24

MN

2D

SA

MA

5D

3x_

BG

A3

24

PD

0K

5

PD

1P

1

PD

2K

6

PD

3R

1

PD

4L

7

PD

5P

2

PD

6L

8

PD

7R

2

PD

8K

7

PD

9U

2

PD

10

K9

PD

11

M5

PD

12

K1

0

PD

13

N4

PD

14

L9

PD

15

N3

PD

16

L1

0

PD

17

N5

PD

18

M6

PD

19

T1

PD

20

N2

PD

21

M3

PD

22

M2

PD

23

L3

PD

24

M1

PD

25

N1

PD

26

L1

PD

27

L2

PD

28

K1

PD

29

K2

PD

30

J1

PD

31

J2

R1

63

DN

P(2

2R

)R

16

3D

NP

(22

R)

R1

52

22

RR

15

22

2R

R1

40

22

RR

14

02

2R

R1

58

DN

P(2

2R

)R

15

8D

NP

(22

R)

MN

2G

SA

MA

5D

3x_

BG

A3

24

MN

2G

SA

MA

5D

3x_

BG

A3

24

D1

4H

16

D1

6H

18

D6

J1

2

D8

J1

4

D9

J1

6

D1

1J1

7

D1

3J1

8

NW

E_

NW

R0

K1

1

D0

K1

2

D4

K1

3

D2

K1

4D

1K

15

D3

K1

6

D5

K1

7

D7

K1

8

NC

S3

L1

2

NR

DL

17

NA

ND

RD

YL

18

D1

0J1

3

D1

2J1

5

R1

49

22

RR

14

92

2R

MN

6M

T2

9F

2G

08

AB

AE

AW

PM

N6

MT

29

F2

G0

8A

BA

EA

WP

WE

18

N.C

66

VC

C3

7

CE

9

RE

8

N.C

11

20

WP

19

N.C

55

N.C

11

N.C

22

N.C

33

N.C

44

DN

U1

21

DN

U2

22

N.C

12

23

N.C

13

24

R/B

7

I/O

8_

N.C

26

I/O

9_

N.C

27

I/O

10

_N

.C2

8

I/O

02

9

VC

C_

N.C

34

N.C

14

35

VS

S3

6

DN

U3

38

VC

C_

N.C

39

VC

C1

2

VS

S1

3

AL

E1

7

N.C

81

1N

.C7

10

N.C

91

4

N.C

10

15

CL

E1

6

VS

S_

N.C

25

I/O

11

_N

.C3

3

I/O

13

0

I/O

33

2I/O

23

1

I/O

15

_N

.C4

7I/

O1

4_

N.C

46

I/O

13

_N

.C4

5

I/O

74

4I/O

64

3I/O

54

2I/O

44

1

I/O

12

_N

.C4

0

VS

S_

N.C

48

R1

37

DN

P(2

2R

)R

13

7D

NP

(22

R)

R1

35

DN

P(2

2R

)R

13

5D

NP

(22

R)

R1

59

DN

P(2

2R

)R

15

9D

NP

(22

R)

C1

06

10

0n

FC

10

61

00

nF


Figure 4-45. SD and Micro-SD Interfaces

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VD

DIO

P1

VD

D_

MC

I0

VD

DIO

P1

VD

DIO

M

VD

DIO

M

VD

DIO

P1

PD

1[7

]

PE

2[7

]

PD

9[7

]

PD

0[7

]P

D4

[7]

PD

3[7

]

PE

0[7

]

PD

6[7

]P

D7

[7]

PD

8[7

]

PD

5[7

]

PD

2[7

]

PB

20

[7]

PB

21

[7]

PB

22

[7]

PB

23

[7]

PB

19

[7]

PB

24

[7]

PE

1[7

]

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

8 11

A

XX

-XX

X-X

XP

Pn

XX

X

HS

MC

I

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

8 11

A

XX

-XX

X-X

XP

Pn

XX

X

HS

MC

I

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

8 11

A

XX

-XX

X-X

XP

Pn

XX

X

HS

MC

I

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

(MC

I0_

CD

)

(MC

I0_

WP

)

SD/M

MC

Plus

CA

RD

INTE

RFA

CE

- MC

I0

(MC

I0_

DA

1)

(MC

I0_

DA

0)

(MC

I0_

CK

)

(MC

I0_

CD

A)

(MC

I0_

DA

3)

(MC

I0_

DA

2)

(MC

I0_

DA

4)

(MC

I0_

DA

5)

(MC

I0_

DA

7)

(MC

I0_

DA

6)

(MC

I1_

DA

1)

(MC

I1_

CK

)(M

CI1

_C

DA

)

(MC

I1_

DA

3)

(MC

I1_

DA

2)

(MC

I1_

CD

)

(MC

I1_

DA

0)

Mic

ro S

D C

AR

D IN

TER

FAC

E - M

CI1

C1

08

10

uF

C1

08

10

uF

C1

10

10

uF

C1

10

10

uF

R5

5

DN

P(4

.7K

)

R5

5

DN

P(4

.7K

)

R122 68KR122 68K

R1

82

22

RR

18

22

2R

R127 68KR127 68K

R1

83

22

RR

18

32

2R

J1

0

7S

DM

M-B

0-2

21

1

J1

0

7S

DM

M-B

0-2

21

1

8 57 6 4 3 2 1 9

14

15

16

13

12

11

10

R54 10KR54 10K

R124 68KR124 68K

J1

1

DN

P(M

CT

F-0

40

3)

J1

1

DN

P(M

CT

F-0

40

3)

DA

T0

7

DA

T1

8

DA

T2

1

DA

T3

2

VD

D4

VS

S6

CD

9

PG

ND

10

PG

ND

11

PG

ND

12

PG

ND

13

NC

14

NC

15

CM

D3

CL

K5

R5

31

00

K 1

%R

53

10

0K

1%

R129 68KR129 68K

R5

9

10

K

R5

9

10

K

R58 10KR58 10K

R130 68KR130 68K

R112 DNP(68K)R112 DNP(68K)

R5

70

RR

57

0R

R126 68KR126 68K

R131 68KR131 68K

R132 68KR132 68K

R121 68KR121 68K

Q3

IRL

ML

64

02

Q3

IRL

ML

64

02

1

32

R123 68KR123 68K

R5

6

10

K

R5

6

10

K

R128 68KR128 68K

C1

11

10

0n

FC

11

11

00

nF

C1

09

10

0n

FC

10

91

00

nF

R125 68KR125 68K


Figure 4-46. Gigabit Ethernet

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PB

3P

B2

PB

1P

B0

PB

4P

B5

PB

6P

B7

ET

H0

_A

+E

TH

0_

A-

ET

H0

_B

-E

TH

0_

C+

ET

H0

_C

-

ET

H0

_D

+E

TH

0_

D-

PB

16

PB

11

PB

13

PB

9

PB

17

PB

10

ET

H0

_L

ED

2

XIXO

ET

H0

_L

ED

1

XI

XO

PB

18

PB

8

ET

H0

_B

+E

TH

0_

B-

ET

H0

_D

+E

TH

0_

D-

ET

H0

_A

+E

TH

0_

A-

ET

H0

_C

+E

TH

0_

C-

ET

H0

_L

ED

1

ET

H0

_L

ED

2

ET

H0

_B

+

VD

DIO

P1

DV

DD

L

AV

DD

L

AV

DD

H

AV

DD

L_

PL

L

VD

DIO

P1

VD

DIO

P1

VD

DIO

P1

VD

DIO

P1

EA

RT

H_

ET

H0

ET

H0

_G

ND

AV

DD

H

VD

DIO

P1

EA

RT

H_

ET

H0

ET

H0

_G

ND

PB

[0..

31

]

[7,8

,10

,11

]

NR

ST

[4,5

,10

,11

]

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

9 11

A

XX

-XX

X-X

XP

Pn

XX

X

Eth

ern

et_

ET

H0

_1

0/1

00

/10

00

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

9 11

A

XX

-XX

X-X

XP

Pn

XX

X

Eth

ern

et_

ET

H0

_1

0/1

00

/10

00

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

9 11

A

XX

-XX

X-X

XP

Pn

XX

X

Eth

ern

et_

ET

H0

_1

0/1

00

/10

00

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

G1

25

CK

GT

X0

GT

X1

GT

X2

GT

X3

GR

X0

GR

X1

GR

X2

GR

X3

GT

XC

K

GT

X_

CT

L

GR

XC

K

GR

X_

CT

L

GM

DC

GM

DIO

INT

_G

ET

HR

ETH

010

Bas

e-T/

100B

ase-

TX/1

000B

ASE

-T

top/b

ot

RG

MII

Routing C

onstr

ain

ts (

Reduced G

igabit M

edia

Independent In

terf

ace):

The R

GM

II s

ignals

must be length

-matc

hed b

y T

X a

nd R

X g

roups.

That is

, th

e T

X g

roup s

hould

be m

atc

hed w

ithin

0.2

5 inch (

6.3

5 m

m),

and the R

X g

roup s

hould

be m

atc

hed w

ithin

0.2

5 inch (

6.3

5 m

m).

Tota

l le

ngth

should

not exceed 1

.75 inch (

44.5

mm

).T

here

is n

o r

equirem

ent to

matc

h the T

X a

nd R

X g

roups

because their c

locks a

re n

ot re

late

d.

top/b

ot

top/b

ot

top/b

ot

top/b

ot

top/b

ot

top/b

ot

top/b

ot

top/b

ot

top/b

ot

top/b

ot

LINK

ACT

Left

Gre

en L

ED

Righ

t Ye

llow

LED

R6

4

4.7

K

R6

4

4.7

K

R6

82

2R

R6

82

2R

+C

12

71

0u

F

+C

12

71

0u

F

C1

12

20

pF

C1

12

20

pF

R7

30

RR

73

0R

R6

11

KR

61

1K

C1

20

10

nF

C1

20

10

nF

R6

7

4.7

K

R6

7

4.7

K

C1

36

10

nF

C1

36

10

nF

+C

11

31

0u

F

+C

11

31

0u

F

Y3

25

MH

zY

32

5M

Hz

1

2 3

4

C1

21

10

nF

C1

21

10

nF

C1

35

10

nF

C1

35

10

nF

C1

29

10

nF

C1

29

10

nF

C1

24

10

0n

F

C1

24

10

0n

F

+C

12

61

0u

F

+C

12

61

0u

F

C1

16

20

pF

C1

16

20

pF

R6

9

4.7

K

R6

9

4.7

K

C1

19

10

nF

C1

19

10

nF

L1

71

80

oh

m a

t 1

00

MH

zL

17

18

0o

hm

at

10

0M

Hz

12

C1

22

10

nF

C1

22

10

nF

C1

15

10

nF

C1

15

10

nF

R6

5

4.7

K

R6

5

4.7

K

C1

34

10

nF

C1

34

10

nF

R71 470RR71 470R

C1

28

10

nF

C1

28

10

nF

J1

2

48

F-0

1G

Y2

DP

L2

NL

J1

2

48

F-0

1G

Y2

DP

L2

NL

TD

2+

3

TD

1+

1

TD

1-

2

TD

3+

7

TD

3-

8

RC

T6

TD

2-

4

GR

LA

11

GR

LC

12

TD

4+

9

TD

4-

10

TC

T5

YE

LC

13

YE

LA

14

GN

D1

5

GN

D1

6

GN

D1

7

GN

D1

8

C1

18

10

nF

C1

18

10

nF

C1

14

10

nF

C1

14

10

nF

C1

33

10

nF

C1

33

10

nF

L1

81

80

oh

m a

t 1

00

MH

zL

18

18

0o

hm

at

10

0M

Hz

12

R72 470RR72 470R

C1

23

10

nF

C1

23

10

nF

KS

Z9

03

1R

NI

48

-pin

QF

N

MN

10

KS

Z9

03

1R

N

KS

Z9

03

1R

NI

48

-pin

QF

N

MN

10

KS

Z9

03

1R

N

VSS_PS13

LED215

DVDDH16

LED117

DVDDL14

TXD019

TXD120

TXD221

TXD322

DVDDL18

DVDDL23

GTX_CLK24

TX

_E

N2

5D

VD

DL

26

RX

D3

27

VS

S2

9D

VD

DL

30

RX

D1

31

RX

D0

32

RX

_D

V3

3D

VD

DH

34

RX

_C

LK

35

MD

C3

6

MDIO37

INT_N38

DVDDL39

DVDDH40

CLK125_NDO41

RESET_N42

LDO_O43

XO45

XI46

AVDDH47

ISET48

AV

DD

H1

TX

RX

P_

A2

TX

RX

M_

A3

TX

RX

P_

B5

TX

RX

M_

B6

TX

RX

P_

C7

TX

RX

M_

C8

TX

RX

P_

D1

0

TX

RX

M_

D1

1

AV

DD

H1

2

RX

D2

28

AVDDL_PLL44

P_GND49

AV

DD

L4

AV

DD

L9

R6

6

4.7

K

R6

6

4.7

K

R6

31

2.1

K 1

%R

63

12

.1K

1%

R1

11

DN

P(0

R)

R1

11

DN

P(0

R)

C1

38

10

nF

C1

38

10

nF

C1

25

DN

P(1

0u

F 0

80

5)

C1

25

DN

P(1

0u

F 0

80

5)

R6

04

.7K

R6

04

.7K

+C

11

71

0u

F

+C

11

71

0u

F

C1

37

10

nF

C1

37

10

nF

R7

02

2R

R7

02

2R

+C

13

21

0u

F

+C

13

21

0u

F

R6

22

2R

R6

22

2R


Figure 4-47. Ethernet 10/100

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

ET

H1

_X

O

ET

H1

_X

I

ET

H1

_X

O

ET

H1

_X

I

ET

H1

_L

ED

0

ET

H1

_L

ED

0

TX

+T

X+

TX

-

RX

+

RX

-R

X-

RX

+

TX

-

ET

H1

_L

ED

1E

TH

1_

LE

D1

VD

DIO

P1

VD

DIO

P0

VD

DIO

P0

E1

_A

VD

DT

VD

DIO

P0

EA

RT

H_

ET

H1

EA

RT

H_

ET

H1

GN

D_

ET

H1

VD

DIO

P0

EA

RT

H_

ET

H1

GN

D_

ET

H1

VD

DIO

P0

NR

ST

[4,5

,9,1

1]

ET

H1

_P

C2

[7]

ET

H1

_P

C3

[7]

ET

H1

_P

C0

[7]

ET

H1

_P

C5

[7]

ET

H1

_P

C6

[7]

ET

H1

_P

C7

[7]

ET

H1

_P

C4

[7]

ET

H1

_P

C8

[7]

ET

H1

_P

C9

[7]

PB

12

[7]

ET

H1

_P

C1

[7]

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

10 11

A

XX

-XX

X-X

XP

Pn

XX

X

Eth

ern

et_

ET

H1

_1

0/1

00

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

10 11

A

XX

-XX

X-X

XP

Pn

XX

X

Eth

ern

et_

ET

H1

_1

0/1

00

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

10 11

A

XX

-XX

X-X

XP

Pn

XX

X

Eth

ern

et_

ET

H1

_1

0/1

00

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

10B

ase-

T/10

0Bas

e-TX

ETH

1

top/b

ot

top/b

ot

top/b

ot

top/b

ot

ACT

LINK

+C

14

81

0u

F

+C

14

81

0u

F

L1

91

80

oh

m a

t 1

00

MH

zL

19

18

0o

hm

at

10

0M

Hz

12

MN

9

KS

Z8

08

1R

NB

MN

9

KS

Z8

08

1R

NBR

XC

/B-C

AS

T_

OF

F1

9

CR

S/C

ON

FIG

12

9

CO

L/C

ON

FIG

02

8

TX

D1

25

TX

D0

24

TX

EN

23

RX

D3

/PH

YA

D0

13

RX

D2

/PH

YA

D1

14

RX

D1

/PH

YA

D2

15

RX

D0

/DU

PL

EX

16

RX

DV

/CO

NF

IG2

18

RX

ER

/IS

O2

0

MD

C1

2

MD

IO1

1

INT

RP

/NA

ND

21

VD

DA

_3

V3

3

VD

DIO

17

RE

SE

T3

2

TX

P7

TX

M6

RX

P5

RX

M4

VD

D_

1V

22

GN

D1

PA

DD

LE

33

TX

C2

2

TX

D2

26

TX

D3

27

RE

XT

10

XO

8

XI

9

LE

D0

/NW

AY

EN

30

LE

D1

/SP

EE

D3

1

R116 10KR116 10K

+C

14

61

0u

F

+C

14

61

0u

F

R120 10KR120 10K

+C

14

41

0u

F

+C

14

41

0u

F

C1

39

10

0n

FC

13

91

00

nF

R114 10KR114 10K

R115 10KR115 10K

C1

47

20

pF

C1

47

20

pF

C1

40

10

0n

FC

14

01

00

nF

C1

41

2.2

uF

C1

41

2.2

uF

R7

94

70

RR

79

47

0R

Y4

25

MH

zY

42

5M

Hz

1

2 3

4

C1

42

10

0n

FC

14

21

00

nF

R8

04

70

RR

80

47

0R

C1

49 20

pF

C1

49 20

pF

R7

66

.49

K 1

%R

76

6.4

9K

1%

C1

43

10

0n

FC

14

31

00

nF

R7

5

1KR7

5

1K

C1

45

10

0n

FC

14

51

00

nF

R7

4

1KR7

4

1K

R113 10KR113 10K

R8

10

RR

81

0R

R7

8

10

K

R7

8

10

K

L2

0

18

0o

hm

at

10

0M

Hz

L2

0

18

0o

hm

at

10

0M

Hz

12

R117 10KR117 10K

R7

7

10

K

R7

7

10

K

R118 10KR118 10K

R119 10KR119 10K

1 2 3 6 4 5 7 8

75 75

7575

1nF

TD+

TD-CT NCRD-CT

TX+

TX-

RX+

RX-

RD+

Left

Gre

en L

ED

Righ

t ye

llow

LED

J1

31

3F

-64

GY

D2

PL

2N

L

1 2 3 6 4 5 7 8

75 75

7575

1nF

TD+

TD-CT NCRD-CT

TX+

TX-

RX+

RX-

RD+

Left

Gre

en L

ED

Righ

t ye

llow

LED

J1

31

3F

-64

GY

D2

PL

2N

L

1 2 7 83 654

9

10

11

12

13

14

15

16


Figure 4-48. LCD, JTAG, DEBUG and Extended Connectors

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

AR

EF

PC

25

PC

28

PC

30

PC

29

PE

19

PE

18

PB

29

PB

28

PD

18

PD

17

PC

18

PD

20

PD

21

PD

22

PD

23

PD

24

PD

25

PD

26

PD

27

PC

20

PD

28

PC

21

PD

29

PD

30

PC

19

PB

3P

B2

PB

1P

B0

PB

13

PB

12

PB

8P

B9

PB

4P

B5

PB

6P

B7

PB

28

PB

16

PB

17

PB

18

PB

10

PB

11

PB

15

PB

14

PB

26

PB

19

PB

23

PB

22

PB

21

PB

20

PB

25

PB

24

PB

29

PB

30

PB

31

PB

27

PA

0P

A1

PA

2P

A3

PA

4P

A5

PA

6P

A7

PA

8P

A9

PA

10

PA

11

PA

15

PA

14

PA

13

PA

12

PA

16

PA

17

PA

18

PA

19

PA

23

PA

22

PA

21

PA

20

PA

25

PA

24

PA

28

PA

29

PA

30

PA

31

PA

27

PA

26

PC

3P

C2

PC

1P

C0

PC

13

PC

12

PC

8P

C9

PC

4P

C5

PC

6P

C7

PC

28

PC

16

PC

17

PC

18

PC

10

PC

11

PC

15

PC

14

PC

26

PC

19

PC

23

PC

22

PC

21

PC

20

PC

25

PC

24

PC

29

PC

30

PC

31

PC

27

PD

13

PD

12

PD

8P

D9

PD

4P

D5

PD

6P

D7

PD

28

PD

16

PD

17

PD

18

PD

10

PD

11

PD

15

PD

14

PD

26

PD

19

PD

23

PD

22

PD

21

PD

20

PD

25

PD

24

PD

29

PD

30

PD

31

PD

27

PD

3P

D2

PD

1P

D0

PD

31

PB

14

PD

14

PD

15

PD30PC17PB26

PC16

PB27PB25

PE9PA17PA19PA21PA23

PE11PE17PE15

PE23

PE13PE29

PE25

PE10

PA20PA18PA16

PE16PE20PE12

PA22

PB15PE31PE14

PE24PE26

PE

30

PE

21

PE

31

PE

24

PE

25

PE

22

PE

27

PE

28

PE

29

PE

15

PE

23

PE

26

PE

1P

E2

PE

3P

E4

PE

5P

E6

PE

14

PE

7P

E8

PE

9

PE

0

PE

10

PE

11

PE

12

PE

13

PE

20

PE

16

PE

17

PE

18

PE

19

5V

_E

xt

5V

_E

xt

PA

0P

A1

PA

2P

A3

PA

4P

A5

PA

6P

A7

PA

8P

A9

PA

10

PA

11

PA

15

PA

14

PA

13

PA

12

PA

25

PA

24

PC

13

PC

12

PC

11

PC

14

PC

10

PC

15

PE

27

PE

28

PA

29

PA

27

PA

26

PE

8P

E7

TW

D_

LC

DT

WC

K_

LC

D

PE

23

PD

10

PD

11

PD

12

PD

16

PD

20

PD

21

PD

22

PD

23

PE

6N

RS

T

TC

KT

MS

RT

CK

TD

I

TD

O

PC15

PC26

TW

CK

_L

CD

TW

D_

LC

D

PC22PC24 PC23

5V

_E

xt

PE

13

PE

14

PA

28

NR

ST

PD

19

PB

15

3V

3

3V

3

5V

_M

AIN

3V

3

VD

DIO

P0

5V

_M

AIN

3V

3

3V

33

V3

PB

[0..

31

][7

,8,9

,10

]

PA

[0..

31

][7

]

PC

[0..

31

][4

,7]

PD

[0..

31

][7

,8]

PE

[0..

31

][4

,5,7

,8]

NR

ST

[4,5

,9,1

0]

J1

5_

Pin

6[7

]J1

5_

Pin

5[7

]J1

5_

Pin

4[7

]

J1

5_

PC

3[7

]J1

5_

PC

4[7

]

J1

8_

PC

5[7

]J1

8_

PC

6[7

]J1

8_

PC

7[7

]

J1

8_

PC

8[7

]J1

8_

PC

9[7

]

AR

EF

[5]

PB

31

[7]

PB

30

[7]

VB

at

[5]

5V

_E

xt

[4]

NR

ST

[4,5

,9,1

0]

TD

O[5

]

TD

I[5

]

TC

K[5

]T

MS

[5]

NT

RS

T[5

]

J1

5_

TW

CK

[7]

J1

5_

TW

D[7

]

TW

D_

ISI

[7]

TW

CK

_IS

I[7

]

TW

CK

_L

CD

[7]

TW

D_

LC

D[7

]

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

11 11

A

XX

-XX

X-X

XP

Pn

XX

X

Co

nn

ecto

rs

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

11 11

A

XX

-XX

X-X

XP

Pn

XX

X

Co

nn

ecto

rs

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

RE

VD

AT

EM

OD

IF.

DE

S.

DA

TE

VE

R.

SC

ALE

1/1

RE

V.

SH

EE

T

INIT

ED

ITAA

Re

vA

11 11

A

XX

-XX

X-X

XP

Pn

XX

X

Co

nn

ecto

rs

27

-Se

p-1

3

SA

MA

5D

3 X

pla

ine

d

19

-Fe

b-1

4E

mb

est

XX

XX

X-X

XX

-XX

LCD

Con

nect

or

DEB

UG

JTA

G

(ID

_S

YS

)

(SP

I0_

SP

CK

)

(SP

I0_

MO

SI)

(SP

I0_

MIS

O)

(SP

I0_

NP

CS

3)

(AD

0)

(AD

1)

(AD

2)

(AD

3)

(TX

D)

(RS

T_

LC

D)

(LC

DD

AT

0)

(LC

DD

AT

1)

(LC

DD

AT

2)

(LC

DD

AT

3)

(LC

DD

AT

4)

(LC

DD

AT

5)

(LC

DD

AT

6)

(LC

DD

AT

7)

(LC

DD

AT

8)

(LC

DD

AT

9)

(LC

DD

AT

10

)(L

CD

DA

T1

1)

(LC

DD

AT

12

)(L

CD

DA

T1

3)

(LC

DD

AT

14

)(L

CD

DA

T1

5)

(LC

DD

AT

16

)(L

CD

DA

T1

7)

(LC

DD

AT

18

)(L

CD

DA

T1

9)

(LC

DD

AT

20

)(L

CD

DA

T2

1)

(LC

DD

AT

22

)(L

CD

DA

T2

3)

(LC

DP

CK

)

(LC

DV

SY

NC

)(L

CD

HS

YN

C)

(LC

DD

EN

)

(LC

DD

ISP

)

(LC

DP

WM

)(I

RQ

2)

IRQ

1)

Exte

ntio

nbo

ards

conn

ecto

rs

(RX

D)

TXD3

RXD3

RXD1

TWCK

1

TXD1

RXD0

TXD0

TWD1

AD8

CANR

X0

AD9

AD10

CANR

X1

CANT

X0

URXD

0UT

XD0

AD0

AD1

AD4

AD2

AD3

AD6

AD5

AD7

SPI1

_MOS

I

SPI1

_MIS

OSP

I1_S

PCK

PA31

PA30

PC26

PC27

TWCK

0TW

D0

ETX0

ETX1

ERX0

SPI1

_NPC

S0ER

X1ET

XEN

SPI1

_NPC

S3

R1

01

22

RR

10

12

2R

J1

4

FH

25

43

-08

GT

10

J1

4

FH

25

43

-08

GT

10

1 2 3 4 5 6 7 8

R190 68KR190 68K

R1

03

22

RR

10

32

2R

R1

68

DN

P(0

R)

R1

68

DN

P(0

R)

R9

30

RR

93

0R

R1

06

10

0K

1%

R1

06

10

0K

1%


J2

3

P1

01

-1*0

6S

GF

-11

6A

-NX

J2

3

P1

01

-1*0

6S

GF

-11

6A

-NX

1 2 3 4 5 6


R8

9D

NP

(0R

)R

89

DN

P(0

R)

J2

4

P1

01

-2*1

0S

GF

-11

6A

-NX

J2

4

P1

01

-2*1

0S

GF

-11

6A

-NX

12

34

56

78

91

01

11

21

31

51

71

9

14

16

18

20

J1

8

FH

25

43

-08

GT

10

J1

8

FH

25

43

-08

GT

10

1 2 3 4 5 6 7 8

J1

9

JT

25

4-D

S1

80

-85

0-2

18

-00

1

J1

9

JT

25

4-D

S1

80

-85

0-2

18

-00

1

1 23 45 67 89 1011 1213151719

14161820

21 2223 2425 2627 2829 3031 3233 3435 36

R1

73

0R

R1

73

0R

R1

05

10

0K

1%

R1

05

10

0K

1%

R1

02

DN

P(0

R)

R1

02

DN

P(0

R)

R8

5D

NP

(0R

)R

85

DN

P(0

R)


R1

00

DN

P(0

R)

R1

00

DN

P(0

R)

R1

84

22

RR

18

42

2R

R9

9D

NP

(0R

)R

99

DN

P(0

R)

J2

1

FH

25

43

-08

GT

10

J2

1

FH

25

43

-08

GT

10

1 2 3 4 5 6 7 8

R9

10

RR

91

0R

R1

87

0R

R1

87

0R

R1

74

0R

R1

74

0R

J1

5

FH

25

43

-10

GT

10

J1

5

FH

25

43

-10

GT

10

12345678910

J1

6

P1

01

-2*0

3S

GF

-11

6A

-NX

J1

6

P1

01

-2*0

3S

GF

-11

6A

-NX

1 23 45 6

R1

08

0R

R1

08

0R

R189 68KR189 68K

R8

4

DN

P(0

R)

R8

4

DN

P(0

R)

J2

2

FP

52

0T

1-5

0S

R0

4

J2

2

FP

52

0T

1-5

0S

R0

4

12345678910

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

52

51

R1

04

10

0K

1%

R1

04

10

0K

1%

R8

80

RR

88

0R

J2

0

FH

25

43

-08

GT

10

J2

0

FH

25

43

-08

GT

10

1 2 3 4 5 6 7 8

R9

2D

NP

(0R

)R

92

DN

P(0

R)

R9

0D

NP

(0R

)R

90

DN

P(0

R)

R1

09

0R

R1

09

0R

R9

40

RR

94

0R

R8

60

RR

86

0R

R8

7D

NP

(0R

)R

87

DN

P(0

R)

J1

7

FH

25

43

-08

GT

10

J1

7

FH

25

43

-08

GT

10

1 2 3 4 5 6 7 8

R9

62

2R

R9

62

2R


R8

3

0R

R8

3

0R

R1

07

10

0K

1%

R1

07

10

0K

1%

R9

8D

NP

(0R

)R

98

DN

P(0

R)

R9

72

2R

R9

72

2R

R1

10

0R

R1

10

0R

R8

20

RR

82

0R

R9

5D

NP

(0R

)R

95

DN

P(0

R)

R1

88

DN

P(0

R)

R1

88

DN

P(0

R)



5. Revision History

Table 5-1. SAMA5D3 Xplained User Guide Rev. 11269A Revision History

Doc. Rev. Changes

11269A First issue

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