Atmel Board

8/8/2019 Atmel Board

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Evaluation Board TSC695..............................................................................................

User Guide


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Evaulation Board TSC695 User Guide 14139GAERO11/05

Table of Contents

Section 1Introduction ........................................................................................... 1-1

1.1 Description ................................................................................................1-11.2 Features....................................................................................................1-1

Section 2 Processor.............................................................................................. 2-5

2.1 Processor Package ...................................................................................2-52.3 Data Buffers Control..................................................................................2-72.4 Processor Socket Part Number.................................................................2-82.5 Emulation Capability .................................................................................2-82.6 Debug Jumper ..........................................................................................2-82.7 PROM8 Jumper ........................................................................................2-8

Section 3 ROM (or Flash) ................................................................................... 3-11

3.1 Flash 8-bit ...............................................................................................3-113.2 Flash 40-bit .............................................................................................3-113.4 Flash - Expansion SIMM.........................................................................3-133.5 Example of Flash - Expansion SIMM......................................................3-14

Section 4 RAM.................................................................................................... 4-15

4.1 RAM - Bank 0..........................................................................................4-154.2 RAM - Bank 1..........................................................................................4-154.4 RAM - Expansion SIMM B ......................................................................4-16

4.5 Example of RAM - Expansion SIMM.......................................................4-17

Section 5 FPGA .................................................................................................. 5-19

5.1 FPGA Part Number .................................................................................5-195.2 FPGA Socket Part Number .....................................................................5-195.3 FPGA Pin-out ..........................................................................................5-205.4 FPGA Clocks...........................................................................................5-225.5 FPGA Downloading.................................................................................5-23

Section 6 DMA.................................................................................................... 6-25

Section 7 TSC695 Power & Clock ...................................................................... 7-27

7.1 TSC695 Power........................................................................................7-277.2 TSC695 Clocks .......................................................................................7-27


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Table of Contents

Evaulation Board TSC695 User Guide 24139GAERO11/05

Section 8 Reset, HALT, EWDINT and Status LEDs .......................................... 8-29

8.1 RESET ....................................................................................................8-298.2 HALT.......................................................................................................8-308.3 EWDINT..................................................................................................8-318.4 Status LEDs ...........................................................................................8-31

Section 9 Test Points.......................................................................................... 9-33

Section 10 Logic Analizer PODs........................................................................ 10-35

10.1 POD 1 ...................................................................................................10-3510.2 POD 2 ...................................................................................................10-36

Section 11

Serial Links ....................................................................................... 11-3911.1 Serial A .................................................................................................11-3911.2 Serial B .................................................................................................11-3911.3 SUN Connection ...................................................................................11-4011.4 PC Connection......................................................................................11-41

Section 12 Tap Connector .................................................................................. 12-43

Section 13 Expansion Connectors...................................................................... 13-45

13.1 3 x 32 points connector - P1 .................................................................13-4513.2 3 x 32 points connector - P2 .................................................................13-4613.3 3 x 32 points connector - P3 .................................................................13-47

Section 14 Board Implementation....................................................................... 14-49

Section 15 Deviations ......................................................................................... 15-51

15.1 CB[6:0] and DPAR on FPGA ................................................................15-51

15.2 Reset and HALT Driven by JTAG Connector........................................15-5115.3 TSC695 Signals on FPGA ....................................................................15-51

Section 16 Schematics ....................................................................................... 16-53

Section 17 Document History ............................................................................. 17-73


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Evaluation Board TSC695 User Guide 1-1Rev. 4139GAERO11/05

Section 1Introduction

1.1 Description The eVAB-695 is a board used to evaluate and demonstrate the TSC695 32-bit RISCembedded processor implementing the SPARC architecture V7 specification.

The TSC695 includes on chip an Integer Unit (IU), a Floating Point Unit (FPU), a Mem-ory Controller and a DMA Arbiter. For Real Time applications, the TSC695 offers a highsecurity Watch Dog, two Timers, an Interrupt Controller, Parallel and Serial interfaces.Fault tolerance is supported using specific parity on internal/external buses and anEDAC on the external data bus. The design is highly testable with the support of an On-Chip Debugger (OCD), an internal and boundary scan through JTAG interface.

This board is based on the TSC695, a ROM space, a SRAM space and DPRAM space.Several extension connectors and a large range of memory mapping produces an highflexibility to the evaluation or the demonstration. Free user interfaces are also proposedto customize the application.

1.2 Features The eVAB-695 board is designed in standard VME. It is a board in B / 2U format (23.3 x16 cm or 9.2 x 6.3 inches). The rear and front 96-pin connectors only respect the powerlines of the VME bus.

1.2.1 Processor The TSC695 includes all the major features (except co-processor implementation andmaster/checker mode) of the ERC32 chip-set. The component can be divided in sixblocks: IU based on SPARC V7.0 architecture FPU compliant to ANSI/IEEE 754 standard specific memory controller slave DMA arbiter seven peripherals:

1 watchdog (or NMI) 2 timers 1 interrupt controller 1 GPI 2 UARTs

JTAG controller with OCD

1.2.2 ROM The eVAB-695 can have either a 8-bit boot-Flash for 512 Kbytes of code either a 40-bitboot-Flash for 2 Mbytes of code.

Up to 4M bytes of code using one SIMM module can be mounted as ROM expansion.

The eVAB-695 is equipped with RDBmon a remote debugger.


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Introduction

1-2 Evaluation Board TSC695 User Guide4139GAERO11/05

1.2.3 RAM The eVAB-695 have 2 banks of 40-bit SRAM for 2 Mbytes of data/code each.

Up to 8M bytes of data/code using 2 SIMM modules can be mounted as RAMexpansion.

1.2.4 FPGA The board is provided without FPGA. A capability is given to mount an ALTERA 10K50FPGA on board.Note: The FPGA interface has been used by Atmel for internal prototyping needs. It

has only been partially validated.

The FPGA area receives all signals of the TSC695 except for the address and databuses. The FPGA receives the address and data buffered buses. Some other FPGAI/Os are connected to the expansion connectors.

The FPGA is downloaded via either a serial PROM (not provided), either via the Bit-Blaster connector.

1.2.5 ExpansionConnectors

3 expansion connectors are provided. P1 and P2 are reserved for system expansion(processor emulation, DMA, exchange RAM, ...) and P3 is dedicated for I/O expansion.

1.2.6 Debugging 1 connector TAP-JTAG for hardware debugging

4 x 34-bit pods for logic analysis 32 couples of signal/Gnd for test points system halt input NMI input (cf EWDINT)

1.2.7 Power The eVAB-695 can be powered (Vcc board) in 5 or 3.3 volts with a proper choice ofcomponents.

Each of the TSC695 Vcc core (VccI) and the TSC695 Vcc buffers (VccO) can be pow-ered separately from the Vcc board.


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Introduction

Evaluation Board TSC695 User Guide 1-34139GAERO11/05

1.3 Board BlockDiagram

Figure 1-1. Board Block Diagram

The processor TSC695 is placed in the centre of the board to be compatible with theSEU test equipment.

The serial A and B connectors, the RESET and HALT switches and the LEDs for boardstatus are placed on the left of P3 on the front side. P1 and P2 are placed on rear side.

A L E

S Y S C L K

DMA

DMA

InternalPeripherals

695E

F P U

IU

R A [ 3 1 : 0 ] Boot ROM 1

Boot ROM 2 SIMM

RAM

RAM Bank[1,0]

SIMM A

SIMM B

Bank[m,n]Bank[r, s]

RAM CtrlMEM & I/O Ctrl

FPGA Area

LSa LSb TAP I/O Connector P3

4 x 34-bitpods

CLK

B D [ 3 9 : 0 ]

B R A [ 3 1 : 0 ]

D [ 3 9 : 0 ]

&

Reset

Expansion Connector P1 Expansion Connector P2MDMAREQ/MDMAGNT

M e m o r y

I n t e r f a c e

R A S I . .

.FPGA

(*)

(*)

BitBlaster

Serial

PROM


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Section 2Processor

2.1 ProcessorPackage

The processor is the TSC695. The package used is the package provided to customers,the 256-pin MQFP-F package. This component is mounted on a special support, with achip-carrier. The component is placed bottom to top in its support. An hole is made on

the board, under the component, to access the die when the lid is removed (SEU tests).Figure 2-1. TSC695 Top View

1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4

256255254253252251250249248247246245244243242241240239238237236235234233232231230229228227226225224223222221220219218217216215214213212211210209208207206205204203202201200199198197196195194193

6566676869707172737475767778798081828384858687888990919293949596979899

100101102103104105106107108109110111112113114115116117118119120121122123124125126127128

1 9 2

1 9 1

1 9 0

1 8 9

1 8 8

1 8 7

1 8 6

1 8 5

1 8 4

1 8 3

1 8 2

1 8 1

1 8 0

1 7 9

1 7 8

1 7 7

1 7 6

1 7 5

1 7 4

1 7 3

1 7 2

1 7 1

1 7 0

1 6 9

1 6 8

1 6 7

1 6 6

1 6 5

1 6 4

1 6 3

1 6 2

1 6 1

1 6 0

1 5 9

1 5 8

1 5 7

1 5 6

1 5 5

1 5 4

1 5 3

1 5 2

1 5 1

1 5 0

1 4 9

1 4 8

1 4 7

1 4 6

1 4 5

1 4 4

1 4 3

1 4 2

1 4 1

1 4 0

1 3 9

1 3 8

1 3 7

1 3 6

1 3 5

1 3 4

1 3 3

1 3 2

1 3 1

1 3 0

1 2 9

G P I N T

G P I [ 7 ]

V C C O

V S S O

G P I [ 6 ]

G P I [ 5 ]

G P I [ 4 ]

G P I [ 3 ]

V C C O

V S S O

G P I [ 2 ]

G P I [ 1 ]

G P I [ 0 ]

D [ 3 1 ]

D [ 3 0 ]

V C C O

V S S O

D [ 2 9 ]

D [ 2 8 ]

V C C I

V S S I

D [ 2 7 ]

D [ 2 6 ]

V C C O

V S S O

D [ 2 5 ]

D [ 2 4 ]

D [ 2 3 ]

D [ 2 2 ]

V C C O

V S S O

D [ 2 1 ]

D [ 2 0 ]

D [ 1 9 ]

D [ 1 8 ]

V C C O

V S S O

D [ 1 7 ]

D [ 1 6 ]

V C C I

V S S I

D [ 1 5 ]

D [ 1 4 ]

V C C O

V S S O

D [ 1 3 ]

D [ 1 2 ]

D [ 1 1 ]

D [ 1 0 ]

V C C O

V S S O

D [ 9 ]

D [ 8 ]

D [ 7 ]

D [ 6 ]

V C C O

V S S O

D [ 5 ]

D [ 4 ]

D [ 3 ]

D [ 2 ]

V C C O

V S S O

D [ 1 ]

RSIZE[1]RSIZE[0]RASI[3]VCCOVSSORASI[2]RASI[1]RASI[0]RA[31]RA[30]VCCOVSSORA[29]RA[28]RA[27]VCCOVSSORA[26]RA[25]RA[24]VCCIVSSIVCCOVSSORA[23]RA[22]RA[21]VCCOVSSORA[20]RA[19]RA[18]VCCOVSSORA[17]RA[16]RA[15]VCCOVSSORA[14]VCCIVSSIRA[13]RA[12]VCCOVSSORA[11]RA[10]RA[9]VCCOVSSORA[8]RA[7]RA[6]VCCOVSSORA[5]RA[4]RA[3]VCCOVSSORA[2]RA[1]

L O C K

R L D S T O R

D

V S S O

V C C O

W E

W R T

I O S E L [ 0 ]

I O S E L [ 1 ]

I O S E L [ 2 ]

V S S O

V C C O

I O S E L [ 3 ]

I O W R

T x B

R x B

R x A T x

A

C P A R

V S S O

V C C O

I U E R R

E X T I N T A C K

V S S I

V C C I

E X T I N T [ 0 ]

E X T I N T [ 1 ]

E X T I N T [ 2 ]

E X T I N T [ 3 ]

E X T I N T [ 4 ]

S Y S A V

S Y S E R R

V S S O

V C C O

C P U H A L T

S Y S H A L T

N O P A R

R O M W R T

B U S R D Y

B U S E R R

D M A R E Q

V S S I

V C C I

E X M C S

D M A G N T

V S S O

V C C O

D M A A S

D R D Y

C L K 2

T C K

T D I

T M S

T R S T

T D O

S Y S C L K

V S S O

V C C O

D P A R

R A S P A R

R A P A R

V S S O

V C C O

R A [ 0 ]

RTCINST

FLUSHVSSOVCCO

DIAINULL

DEBUGTMODE[0]TMODE[1]

EWDINTIWDE

WDCLKMDS

MHOLDDDIR

VSSOVCCODDIR

BUFFENMEMWR

VSSOVCCO

OEVSSIVCCI

MEMCS[0]MEMCS[1]MEMCS[2]

VSSOVCCO

MEMCS[3]MEMCS[4]MEMCS[5]MEMCS[6]MEMCS[7]MEMCS[8]

VSSOVCCO

MEMCS[9]ROMCSPROM8

VSSIVCCIALE

CB[0]VSSOVCCOCB[1]CB[2]CB[3]CB[4]

VSSOVCCOCB[5]CB[6]BA[0]BA[1]

SYSRESETRESET

VSSOVCCOMEXC

DXFER

TSC695(top view)


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Processor


2.2 Processor Pin-Out Table 2-1. TSC695 Pin-out

Pin Signal Pin Signal Pin Signal Pin Signal1 GPIINT 65 D[0] 129 RA[0] 193 DXFER2 GPI[7] 66 RSIZE[1] 130 VCCO 194 MEXC ]3 VCCO 67 RSIZE[0] 131 VSSO 195 VCCO4 VSSO 68 RASI[3] 132 RAPAR 196 VSSO

5 GPI[6] 69 VCCO 133 RASPAR 197 RESET ]6 GPI[5] 70 VSSO 134 DPAR 198 SYSRESET ]7 GPI[4] 71 RASI[2] 135 VCCO 199 BA[1]8 GPI[3] 72 RASI[1] 136 VSSO 200 BA[0]9 VCCO 73 RASI[0] 137 SYSCLK 201 CB[6]

10 VSSO 74 RA[31] 138 TDO 202 CB[5]11 GPI[2] 75 RA[30] 139 TRST ] 203 VCCO12 GPI[1] 76 VCCO 140 TMS 204 VSSO13 GPI[0] 77 VSSO 141 TDI 205 CB[4]14 D[31] 78 RA[29] 142 TCK 206 CB[3]15 D[30] 79 RA[28] 143 CLK2 207 CB[2]16 VCCO 80 RA[27] 144 DRDY ] 208 CB[1]17 VSSO 81 VCCO 145 DMAAS 209 VCCO18 D[29] 82 VSSO 146 VCCO 210 VSSO19 D[28] 83 RA[26] 147 VSSO 211 CB[0]

20 VCCI 84 RA[25] 148 DMAGNT ] 212 ALE ]21 VSSI 85 RA[24] 149 EXMCS ] 213 VCCI22 D[27] 86 VCCI 150 VCCI 214 VSSI23 D[26] 87 VSSI 151 VSSI 215 PROM8 ]24 VCCO 88 VCCO 152 DMAREQ ] 216 ROMCS ]25 VSSO 89 VSSO 153 BUSERR ] 217 MEMCS[9] ]26 D[25] 90 RA[23] 154 BUSRDY ] 218 VCCO27 D[24] 91 RA[22] 155 ROMWRT ] 219 VSSO28 D[23] 92 RA[21] 156 NOPAR ] 220 MEMCS[8] ]29 D[22] 93 VCCO 157 SYSHALT ] 221 MEMCS[7] ]30 VCCO 94 VSSO 158 CPUHALT ] 222 MEMCS[6] ]31 VSSO 95 RA[20] 159 VCCO 223 MEMCS[5] ]32 D[21] 96 RA[19] 160 VSSO 224 MEMCS[4] ]33 D[20] 97 RA[18] 161 SYSERR ] 225 MEMCS[3] ]34 D[19] 98 VCCO 162 SYSAV 226 VCCO

35 D[18] 99 VSSO 163 EXTINT[4] 227 VSSO36 VCCO 100 RA[17] 164 EXTINT[3] 228 MEMCS[2] ]37 VSSO 101 RA[16] 165 EXTINT[2] 229 MEMCS[1] ]38 D[17] 102 RA[15] 166 EXTINT[1] 230 MEMCS[0] ]39 D[16] 103 VCCO 167 EXTINT[0] 231 VCCI40 VCCI 104 VSSO 168 VCCI 232 VSSI41 VSSI 105 RA[14] 169 VSSI 233 OE ]42 D[15] 106 VCCI 170 EXTINTACK 234 VCCO43 D[14] 107 VSSI 171 IUERR ] 235 VSSO44 VCCO 108 RA[13] 172 VCCO 236 MEMWR ]45 VSSO 109 RA[12] 173 VSSO 237 BUFFEN ]46 D[13] 110 VCCO 174 CPAR 238 DDIR47 D[12] 111 VSSO 175 TXA 239 VCCO48 D[11] 112 RA[11] 176 RXA 240 VSSO49 D[10] 113 RA[10] 177 RXB 241 DDIR ]

50 VCCO 114 RA[9] 178 TXB 242 MHOLD ]51 VSSO 115 VCCO 179 IOWR ] 243 MDS ]52 D[9] 116 VSSO 180 IOSEL[3] ] 244 WDCLK53 D[8] 117 RA[8] 181 VCCO 245 IWDE54 D[7] 118 RA[7] 182 VSSO 246 EWDINT55 D[6] 119 RA[6] 183 IOSEL[2] ] 247 TMODE[1]56 VCCO 120 VCCO 184 IOSEL[1] ] 248 TMODE[0]57 VSSO 121 VSSO 185 IOSEL[0] ] 249 DEBUG58 D[5] 122 RA[5] 186 WRT 250 INULL59 D[4] 123 RA[4] 187 WE ] 251 DIA60 D[3] 124 RA[3] 188 VCCO 252 VCCO61 D[2] 125 VCCO 189 VSSO 253 VSSO


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Processor


2.3 Data BuffersControl

Figure 2-2. Data Buffers Control Schematic

Figure 2-3. Data Buffers Control Configuration

62 VCCO 126 VSSO 190 RD 254 FLUSH63 VSSO 127 RA[2] 191 RLDSTO 255 INST64 D[1] 128 RA[1] 192 LOCK 256 RTC

Table 2-1. TSC695 Pin-out (Continued)Pin Signal Pin Signal Pin Signal Pin Signal

J32

12

34

56

EXT_D_BUFFENP2 - C24

EXT_C_BUFFENP2 - C23

FPGA - C6

FPGA - C7

BUFFENP2 - B30FPGA - AD4

BUFFENTSC695 - 237

xx245 xx245 xx245 xx245 xx245U26U22 U23 U24 U25

G3 G3 G3 G3 G3

BCB [6:0] | BDPAR

CB [6:0] | DPAR

BD [31:0]

D [31:0]

POD3 - pin26

J32

CB_BUFFENEXT_C_BUFFEN

BUFFEN

135

J32 / 3-1

J32 / 3-5

Controled by P2

Controled by mP

246

DATA_BUFFENEXT_D_BUFFEN

BUFFEN

J32 / 4-2

J32 / 4-6

J6

U1

U7

U8

U9

J28

J5 J4

J19

J20

or FPGA

J32

J18

Data Check


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Processor


2.4 ProcessorSocket PartNumber

The socket used for the TSC695 device is made by ENPLAS (www.enplas.com).The socket reference is: FPQ-256-0.508-01.The chip carrier reference is: CA-256-0.508-01.

2.5 EmulationCapability

Excepted for TMODE[1,0], DEBUG, ROMWRT ], NOPAR ] and JTAG port, all TSC695signals are available on P1 & P2 connectors. In this way, an emulation of the processor(support empty) can be done through P1 & P2 (ex: MCM or ERC32 chip-set).

2.6 Debug Jumper The debug jumper drives directly the TSC695 input pin "DEBUG" to Vcc or Gnd.

Figure 2-4. Processor - Debug Jumper

2.7 PROM8 Jumper The PROM8 jumper drives directly the TSC695 input pin "PROM8" to Vcc or Gnd.

Figure 2-5. Processor - PROM8 jumper

J6

U1

U7

U8

U9

J28

J5 J4

J19

J18

J19

DEBUGON

OFF

123 J19 / 2-3

J19 / 1-2

Debug Off

Debug On

J20

J8

PROM8

ON OFF

123

J8 / 1-2

J8 / 2-3

PROM40

PROM8

U12

J7

U1U28

J8

J29

J30

J14

U15U14U13

J20

J4


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Processor


2.8 Parity Jumper The PARity jumper drives directly the TSC695 input pin "NOPAR" to Vcc or Gnd.

Figure 2-6. Processor - Parity jumper

J9

PARityON

OFF

123 J9 / 2-3

J9 / 1-2

Parity Off

Parity OnU12

U1

U27

U28

J8

J9

J29

J30

J14

U15U14U13J4


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Section 3ROM (or Flash)

128K x 8 or 512K x 8 components can be used. PROMs, EPROMs or Flash devicesare available. The capacity must be correctly programmed in the Memory ConfigurationRegister (field psiz ) of the TSC695. The capacity will be the total of the on board capac-ity included the expansion SIMM module.

The on-board ROMs are placed in sockets.

3.1 Flash 8-bit It is possible to use the 8-bit mode. The device to be use is a 32-pin PLCC and islocated in U12.

Table 3-1. Flash 8-bit Configuration

3.2 Flash 40-bit It is possible to use the 40-bit mode. The devices to be used are 32-pin PLCC and arelocated in U14 for byte 3 D[24:31], in U15 for byte 2 D[16:23], in U16 for byte 2 D[8:15], in U17for D[0:7]byte 20, Parity on D7 of U13 (MSB), CB [0:6] of U13.

Table 3-2. Flash 40-bit Configuration

Capacity (8-bit Mode)128K x 8

Ex: using Flash 29F010128K bytes of code

512K x 8


Capacity (40-bit Mode)128K x 8


512K x 8Ex: using Flash 29F040 2M bytes of code


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ROM (or Flash)


3.3 Flash 8-bit/Flash 40-bitSelection

If no FPGA is implemented, the Flash 8-bit and the Flash 40-bit cannot be present at thesame time. Only the decoding made in FPGA can allow the presence of both the Flash8-bit and the Flash 40-bit.

3.3.1 Schematic

Figure 3-1. Flash 8-bit / Flash 40-bit Selection Schematic

3.3.2 FlashCS Jumper

Figure 3-2. FlashCS Jumper Configuration

ROMCS

PROM8

TSC695

J8

PROM8FPGA

BOOTROM1_40_CS

BOOTROM1_8_CSFlash_8_CS

Flash_40_CSJ16

FlashCS

12

34

56

Other conditions

216

215

C4

C5 H26

J2

123on

off

J16

Flash_40_CSBOOTROM1_40_CS

ROMCS

135

J16 / 3-5

J16 / 1-3

No FPGA

FPGA configured

U12

J3

U27

U28

J9

J30

J14 J16

U17

U16U15U14

J29

246

Flash_8_CSBOOTROM1_8_CS

ROMCS

J16 / 4-6

J16 / 2-4

J31


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ROM (or Flash)


3.3.3 Flash 8-bit Write In ROM8-bit mode, the input write signal of the Flash (U12) can be powered either byMEMWR either by WR.

Figure 3-3. Flash 8-bit Write Jumper Configuration

3.4 Flash -Expansion SIMM

Up to 4M bytes of code using a 72-pin SIMM proprietary module on connector can bemounted as Flash (ROM) expansion on the J3 connector.

3.4.1 Flash - ExpansionSIMM selection

The operating mode is the mode selected in boot ROM space (ROM_8 or ROM_40).

If no FPGA is implemented, the Flash 8-bit and the Flash 40-bit cannot be present inthe same time in the SIMM expansion. The on-SIMM Flashs selection can be madeby ROMCS signal using J31 connector.

If FPGA is implemented, the on-SIMM Flash can be selected either by theBOOTROM2_8_CS (FPGA pin J4) or BOOTROM2_40_CS (FPGA pin J3) signalscoming from the FPGA. J31 connector is used for the selection. Only a decodingmade in FPGA can allow the presence on SIMM of both a Flash 8-bit and a Flash 40-bit.

3.4.2 Schematic

Figure 3-4. Flash - Expansion SIMM Selection Schematic

J30 / 2-3

J30 / 1-2

WR_U12 = WR

WR_U12 = MEMWR

U12

J7

U1U28

J8

J29

J30

J14

U15U14U13

J20

J4

J30

WR_U12MEMWR

WR

123

ROMCS

PROM8

TSC695

J8

PROM8

FPGA

BOOTROM2_40_CS

BOOTROM2_8_CS

SIMM_8_CS

SIMM_40_CS

J31

On-SIMM

12

34

56

Other conditions

216

215

C4

C5 J3

J4

12

3on

off

FlashCS


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ROM (or Flash)


Figure 3-5. Flash - Expansion SIMM Selection

3.4.3 Flash - ExpansionSIMM pin-out

This pin-out is compatible to the SIMM module of SRAM expansion.

Bottom view:

Top view:

3.5 Example of Flash- ExpansionSIMM

This module can expand the Flash capacity from 512K to 1M bytes of code in 8-bitmode and 2M to 4M bytes of code in 40-bit mode.

Figure 3-6. Example of Flash - Expansion SIMM module

J31

SIMM_40_CSBOOTROM2_40_CS

ROMCS

135

J31 / 3-5J31 / 1-3

No FPGA

FPGA configured

U12

J3

U27

U28

J9

J30

J14 J16

U17

U16U15U14

J29

246

SIMM_8_CSBOOTROM2_8_CS

ROMCS

J31 / 4-6J31 / 2-4

J31

12

3

G N D

5 7

B D 0 8

9

B D 0 9

11

B D 1 0

13

B D 1 1

154 6

B D 0 0

8

B D 0 1

10

B D 0 2

12

B D 0 3

14

+ V C C

16

B A 0 0

18

B A 0 1

20 22

B C B 0 4

24

B C B 0 5

26

B C B 0 6

28

B C B 0 7

30

M E M W R

32

B R A 1 9

34 36

B R A 0 2

17

B R A 0 3

19

B R A 0 4

21

B D 1 2

23

B D 1 3

25

B D 1 4

27

B D 1 5

29

G N D

31 33 35 3738

B R A 1 0

39

O E

41

B D 2 0

43

B D 2 1

45

B D 2 2

47

B D 2 3

49

B R A 0 7

5140

G N D

42

B D 1 6

44

B D 1 7

46

B D 1 8

48

B D 1 9

50

B R A 1 3

52

B R A 1 4

54

B R A 1 5

56

B R A 1 6

58

B D 2 4

60

B D 2 5

62

B D 2 6

64

B D 2 7

66

G N D

68

B R A 2 0

70 72

B R A 0 8

53

B R A 0 9

55

+ V C C

57 59

B D 2 8

61

B D 2 9

63

B D 3 0

65

B D 3 1

67

B R A 1 1

69 71

B R A 1 2

B R A 1 7

B R A 1 8

B R A 2 1

B C B 0 0

B C B 0 1

B C B 0 2

B C B 0 3

B D 0 4

B D 0 5

B D 0 6

B D 0 7

B R A 0 5

B R A 0 6

S I M M

_ 8

_ C S

S I M M

_ 4 0

_ C S

1

2

3 5 7 9 11 13 15

4 6 8 10 1 2 14 1 6 18 2 0 22 2 4 26 2 8 30 3 2 34 3 6

17 19 21 23 25 27 29 31 33 35 37

38

3 9 4 1 4 3 4 5 4 7 4 9 5 1

4 0 4 2 4 4 4 6 4 8 5 0 5 2 5 4 5 6 5 8 6 0 6 2 6 4 6 6 6 8 7 0 7 2

53 55 57 59 61 63 65 67 69 71

BRA[20:2]

BD[7:0] BD[15:8] BD[23:16] BD[31:24] BCB[7:0]

BA[1:0]BRA[18:2]

MEMWR

OE

0

123

AB

SIMM_8_CS

BRA[19]BRA[20]

GSIMM_40_CS

BRA[21]

F L A S H

( 5 1 2 K x

8 )

F L A S H

( 5 1 2 K x

8 )

F L A S H

( 5 1 2 K x

8 )

F L A S H

( 5 1 2 K x

8 )

F L A S H

( 5 1 2 K x

8 )

F L A S H

( 5 1 2 K x

8 )

1 3 9

1 / 2

0

123

AB

G

1 3 9

1 / 2


16/69


Section 4RAM

The RAM space (in 40-bit mode) is built in banks of 2M bytes of code/data.The two first banks are implemented on board, the other ones (up to 4) can imple-mented on two 72-pin SIMM modules as RAM expansion.

The on-board RAMs are soldered.

4.1 RAM - Bank 0 The first bank (Bank 0) is composed of five 512K x 8 SRAMs selected by MEMCS[0] ofthe TSC695. The total capacity is 2M bytes of code/data.The devices used are located in U2 for check byte + parity, U3 for byte 3 (D[0..7]), U4 forbyte 2 (D[8..15], U5 for byte 1 (D[16..23]) and U6 for byte 0 (D[24..31]).

First word address : 0x02000000

Last word address : 0x021FFFFC

4.2 RAM - Bank 1 The second bank (Bank 1) is composed of five 512K x 8 SRAMs selected by MEMCS[1]of the TSC695. The total capacity is 2M bytes of code/data.The devices used are located in U7 for check byte + parity, U8 for byte 3 (D[0..7]), U9 forbyte 2 (D[8..15], U10 for byte 1 (D[16..23]) and U11 for byte 0 (D[24..31]).

First word address : 0x02200000

Last word address : 0x023FFFFC


17/69

RAM


4.3 RAM - ExpansionSIMM A

Up to 2 banks of RAM using a 72-pin SIMM module on connector can be mounted asRAM expansion A on the J1 connector.This space is selected by the J1 jumper (from MEMCS[2] to MEMCS[9]).

4.3.1 RAM - ExpansionSIMM A selection

Figure 4-1. RAM - Expansion SIMM A Selection

4.3.2 RAM - ExpansionSIMM A pin-out This pin-out is compatible with the SIMM module of Flash expansion.Bottom view:

Top view:

4.4 RAM - ExpansionSIMM B

Up to 2 banks of RAM using a 72-pin SIMM module on connector can be mounted asRAM expansion B on the J2 connector.This space is selected by jumpers on board (from MEMCS[2] to MEMCS[9]).

4.4.1 RAM - Expansion

SIMM B selection

Figure 4-2. RAM - Expansion SIMM B selection

CS2A

CS1A

MEMCS[2]

MEMCS[6]J7J6

U7U14U13

J28

J5 J4J18



J20

G N D

+ V C C

12

3

G N D

5 7

D 0 8

9

D 0 9

11

D 1 0

13

D 1 1

154 6

D 0 0

8

D 0 1

10

D 0 2

12

D 0 3

14

+ V C C

16 18 20 22

C B 0 4

24

C B 0 5

26

C B 0 6

28

C B 0 7

30

M E M W R

32

R A 1 9

34

C S 1 A

36

R A 0 2

17

R A 0 3

19

R A 0 4

21

D 1 2

23

D 1 3

25

D 1 4

27

D 1 5

29

G N D

31 33 35 3738

R A 1 0

39

O E

41

D 2 0

43

D 2 1

45

D 2 2

47

D 2 3

49

R A 0 7

5140

G N D

42

D 1 6

44

D 1 7

46

D 1 8

48

D 1 9

50

R A 1 3

52

R A 1 4

54

R A 1 5

56

R A 1 6

58

D 2 4

60

D 2 5

62

D 2 6

64

D 2 7

66

G N D

68

R A 2 0

70 72

R A 0 8

53

R A 0 9

55

+ V C C

57 59

D 2 8

61

D 2 9

63

D 3 0

65

D 3 1

67

R A 1 1

69 71

R A 1 2

R A 1 7

R A 1 8

R A 2 1

C B 0 0

C B 0 1

C B 0 2

C B 0 3

D 0 4

D 0 5

D 0 6

D 0 7

C S 2 A

R A 0 5

R A 0 6

1

2

3 5 7 9 11 13 15

4 6 8 10 1 2 14 1 6 18 2 0 22 2 4 26 2 8 30 3 2 34 3 6

17 19 21 23 25 27 29 31 33 35 37

38

3 9 4 1 4 3 4 5 4 7 4 9 5 1

4 0 4 2 4 4 4 6 4 8 5 0 5 2 5 4 5 6 5 8 6 0 6 2 6 4 6 6 6 8 7 0 7 2

53 55 57 59 61 63 65 67 69 71

CS2B

CS1B

MEMCS[2]

MEMCS[6]



J7J6

U7U14U13J5 J4

J18

J28 J20


18/69

RAM


4.4.2 RAM - ExpansionSIMM B pin-out

This pin-out is compatible to the SIMM module of Flash expansion.

Bottom view:

Top view:

4.5 Example of RAM- ExpansionSIMM

One module can expand the RAM capacity from 1 bank or 2 banks.

Figure 4-3. Example of RAM - Expansion SIMM module

G N D

+ V C C

1

2

3

G N D

5 7

D 0 8

9

D 0 9

11

D 1 0

13

D 1 1

15

4 6

D 0 0

8

D 0 1

10

D 0 2

12

D 0 3

14

+ V C C

16 18 20 22

C B 0 4

24

C B 0 5

26

C B 0 6

28

C B 0 7

30

M E M W R

32

R A 1 9

34

C S 1 B

36

R A 0 2

17

R A 0 3

19

R A 0 4

21

D 1 2

23

D 1 3

25

D 1 4

27

D 1 5

29

G N D

31 33 35 37

38

R A 1 0

39

O E

41

D 2 0

43

D 2 1

45

D 2 2

47

D 2 3

49

R A 0 7

51

40

G N D

42

D 1 6

44

D 1 7

46

D 1 8

48

D 1 9

50

R A 1 3

52

R A 1 4

54

R A 1 5

56

R A 1 6

58

D 2 4

60

D 2 5

62

D 2 6

64

D 2 7

66

G N D

68

R A 2 0

70 72

R A 0 8

53

R A 0 9

55

+ V C C57 59

D 2 8

61

D 2 9

63

D 3 0

65

D 3 1

67

R A 1 1

69 71

R A 1 2

R A 1 7

R A 1 8

R A 2 1

C B 0 0

C B 0 1

C B 0 2

C B 0 3

D 0 4

D 0 5

D 0 6

D 0 7

C S 2 B

R A 0 5

R A 0 6

1

2

3 5 7 9 11 13 15

4 6 8 10 1 2 14 1 6 18 2 0 22 2 4 26 2 8 30 3 2 34 3 6

17 19 21 23 25 27 29 31 33 35 37

38

3 9 4 1 4 3 4 5 4 7 4 9 5 1

4 0 4 2 4 4 4 6 4 8 5 0 5 2 5 4 5 6 5 8 6 0 6 2 6 4 6 6 6 8 7 0 7 2

53 55 57 59 61 63 65 67 69 71

RA[20:2]

D[7:0] D[15:8] D[23:16] D[31:24] CB[7:0]

MEMWROE

CS1 S R A M

( 5 1 2 K x

8 )

S R A M

( 5 1 2 K x

8 )

S R A M

( 5 1 2 K x

8 )

S R A M

( 5 1 2 K x

8 )

S R A M

( 5 1 2 K x

8 )

CS2


19/69


Section 5FPGA

For internal prototyping needs, Atmel has developed an FPGA area on the TSC695board. This interface has only been partially validated (not all of the signals have beenexecrised). The following section gives the key points for the integration of an additionalFPGA on the board.

Atmel does not intend to fully validate the FPGA interface. No support will be providedby Atmel in case of integration of such an FPGA on-board at the reserved location.

The FPGA can be useful to add some functions to the board. A dedicated area has beenreserved on-board to fit this expansion mode requirement.

5.1 FPGA PartNumber

The eVAB-695 board is designed to ease integration of an ALTERA EPF-10K50 to theboard. The FPGA (BGA-356 package) should be placed in a socket.

Depending on the board powering , 3.3V or 5V FPGA shall be used.

5.0 Volts:ALTERA EPF-10K50BC356-3

3.3 volts:ALTERA EPF-10K50VBC356-3

5.2 FPGA SocketPart Number

The socket used for the FPGA device is made by E-Tec (www.e-tec.ch).The socket reference is: BPW356-1270-26AA01.


20/69

FPGA


5.3 FPGA Pin-out

Figure 5-1. FPGA Pin-out

1234567891011121314151617181920212223242526

ABCDEFGHJKLMNPRTUVWYAAABACADAEAF

EPF-10K50BC356-3EPF-10K50VBC356-3

BGA-356

Bottom View

EPF-10K50BC356-3EPF-10K50VBC356-3

BGA-356

Top View

Indicates location of pin A1


21/69

FPGA


Table 5-1. FPGA Pin-out with Inter-connectionsPin Signal Pin Signal Pin Signal Pin Signal Pin SignalA1 Vcc (power) D1 P3-A29 L1 P3-B10 U1 P3-C19 AD1 GPI[5]A2 Gnd (power) D2 nCONFIG L2 P3-B11 U2 P3-C20 AD2 Gnd (power)A3 BRA[0} D3 Gnd (MSEL1) L3 P3-B14 U3 P3-C21 AD3 Data0A4 BRA[1] D4 Gnd (MSEL0) L4 P3-B15 U4 P3-C22 AD4 BUFFEN ]A5 BRA[2] D5 Vcc (power) L5 P3-B16 U5 Vcc (power) AD5 (Data2 - "open")

A6 BRA[3] D22 Vcc (TMS) L22 P3-B17 U22 (RDYnBSY - AD6 (Data4 - "open")A7 Vcc (power) D23 Gnd (TRST) L23 P3-B18 U23 P3-C23 AD7 GPI[6]A8 BRA[4] D24 nSTATUS L24 P3-B19 U24 P3-C24 AD8 (Data6 - "open")A9 BRA[5] D25 Vcc (power) L25 P3-B20 U25 P3-C25 AD9 GPI[7]

A10 Gnd (power) D26 P3-A30 L26 P3-B21 U26 Gnd (power) AD10 TXAA11 BRA[6] AD11 TXBA12 BRA[7] E1 P3-A31 M1 Gnd (power) V1 P3-C26 AD12 CB[0]A13 Vcc (input) E2 P3-A32 M2 P3-A17 V2 Vcc (power) AD13 Vcc (DEV_CLRn)A14 SYSCLK E3 BD[0] M3 P3-A18 V3 P3-C27 AD14 Gnd (power)A15 BRA[8] E4 BD[1] M4 P3-A19 V4 P3-C28 AD15 CB[1]A16 BRA[9] E5 BD[2] M5 P3-A20 V5 P3-C29 AD16 CB[2]A17 BRA[10] E22 BD[3] M22 P3-A21 V22 P3-C30 AD17 CB[3]A18 BRA[11] E23 BD[4] M23 Vcc (power) V23 P3-C31 AD18 Vcc (power)A19 BRA[12] E24 BD[5] M24 P3-A22 V24 P3-C32 AD19 CB[4]A20 Gnd (power) E25 BD[6] M25 P3-A23 V25 IOSEL[0] ] AD20 Gnd (power)

A21 BRA[13] E26 BD[7] M26 Vcc (power) V26 IOSEL[1] ] AD21 CB[5]A22 BRA[14] AD22 CB[6]A23 Vcc (power) F1 Vcc (power) N1 Vcc (power) W1 Gnd (power) AD23 Gnd (CS)A24 BRA[15] F2 BD[8] N2 P3-A24 W2 IOSEL[2] ] AD24 Vcc (nCS)A25 BRA[16] F3 BD[9] N3 P3-A25 W3 IOSEL[3] ] AD25 Gnd (TCK)A26 Vcc (power) F4 Vcc (power) N4 P3-A26 W4 IOWR ] AD26 Vcc (power)

F5 BD[10] N5 P3-A27 W5 FLUSHB1 Gnd (power) F22 BD[11] N22 P3-A28 W22 Vcc (power) AE1 Gnd (power)B2 BRA[17] F23 BD[12] N23 P3-B23 W23 INST AE2 Gnd (power)B3 BRA[18] F24 BD[13] N24 P3-B24 W24 INULL AE3 DPARB4 Vcc (power) F25 BD[14] N25 P3-B25 W25 DIA AE4 CPARB5 BRA[19] F26 BD[15] N26 Gnd (power) W26 IUERR ] AE5 (Data5 - "open")B6 BRA[20] AE6 RAPARB7 BRA[21] G1 BD[16] Y1 SYSERR ] AE7 Gnd (power)B8 BRA[22] G2 BD[17] Y2 CPUHALT ] AE8 RASPAR

B9 BRA[23] G3 BD[18] Y3 SYSAV AE9 TCK (of 695E)B10 BRA[24] G4 BD[19] Y4 RTC AE10 TMS (of 695E)B11 BRA[25] G5 BD[20] Y5 GPIINT AE11 TRST ](of 695E)B12 BRA[26] G22 BD[21] Y22 EXTINTACK AE12 TDI (of 695E)B13 Gnd (power) G23 BD[22] Y23 RESET ] AE13 Gnd (input)B14 Vcc (input) G24 BD[23] Y24 EWDINT AE14 Vcc (DEV_OE)B15 BRA[27] G25 BD[24] Y25 IWDE AE15 TDO (of 695E)B16 BRA[28] G26 BD[25] Y26 WDCLK AE16 RESET_HALT[0]B17 BRA[29] AE17 RESET_HALT[1]B18 BRA[30] H1 BD[26] P1 P3-B26 AA1 Vcc (power) AE18 MEMCS[0] ]B19 BRA[31] H2 BD[27] P2 Vcc (power) AA2 LOCK AE19 MEMCS[1] ]B20 RSIZE[0] H3 BD[28] P3 P3-B27 AA3 DXFER AE20 MEMCS[2] ]B21 RSIZE[1] H4 BD[29] P4 P3-B28 AA4 RD AE21 MEMCS[3] ]B22 Gnd (power) H5 BD[30] P5 P3-B29 AA5 RLDSTO AE22 MEMCS[4] ]B23 RASI[0] H22 Vcc (power) P22 P3-B30 AA22 WRT AE23 Vcc (nRS)

B24 RASI[1] H23 Gnd (power) P23 P3-C1 AA23 WE ] AE24 Vcc (nWS)B25 Gnd (power) H24 Vcc (power) P24 P3-C2 AA24 Gnd (CLKUSR) AE25 Gnd (power)B26 Gnd (power) H25 BD[31] P25 P3-C3 AA25 RXA AE26 Gnd (power)

H26 BOOTROM1_40_CS] P26 P3-C4 AA26 RXBC1 RASI[2] AF1 Vcc (power)C2 Gnd (power) J1 Vcc (power) R1 Gnd (power) AB1 Vcc (power) AF2 (Data3 - "open")C3 RASI[3] J2 BOOTROM1_8_ R2 P3-C5 AB2 SYSHALT ] AF3 Vcc (power)C4 ROMCS ] J3 BOOTROM2_40 R3 P3-C6 AB3 EXTINT[0] AF4 (Data7 - "open")C5 PROM8 ] J4 BOOTROM2_8_ R4 P3-C7 AB4 FPGA-RA26 AF5 MEMCS[5] ]C6 P2-C24 J5 DMAAS R5 P3-C8 AB5 EXTINT[1] AF6 MEMCS[6] ]C7 P2-C23 J22 DMAREQ ] R22 P3-C9 AB22 EXTINT[2] AF7 Vcc (power)C8 P2-C22 J23 BUSERR ] R23 P3-C10 AB23 EXTINT[3] AF8 MEMCS[7] ]


22/69

FPGA


5.4 FPGA Clocks Two separate clocks must be provided to the FPGA.

5.4.1 FPGA ClocksSchematic

Figure 5-2. FPGA Clocks Schematic

5.4.2 FPGA Clocks

Jumper

Figure 5-3. FPGA Clocks Selection

C9 Gnd (power) J24 BUSRDY ] R24 P3-C11 AB24 EXTINT[4] AF9 MEMCS[8] ]C10 P2-C21 J25 DMAGNT ] R25 P3-C12 AB25 GPI[0] AF10 MEMCS[9] ]C11 P2-C20 J26 Gnd (power) R26 Gnd (power) AB26 GPI[1] AF11 Gnd (power)C12 P2-C19 AF12 MEXC ]C13 Gnd (power) K1 Gnd (power) T1 Gnd (power) AC1 GPI[2] AF13 GCLK_1C14 Vcc (power) K2 DRDY ] T2 P3-C13 AC2 Gnd (nCE) AF14 Gnd (input)C15 Vcc (power) K3 P3-B3 T3 P3-C14 AC3 Vcc (TDI) AF15 MHOLD ]C16 P2-C18 K4 P3-B4 T4 P3-C15 AC4 GPI[3] AF16 Vcc (power)C17 P2-C17 K5 Vcc (power) T5 P3-C16 AC5 DCLK AF17 ALE ]C18 P2-C16 K22 P3-B5 T22 P3-C17 AC22 (nCEO - "open") AF18 DDIRC19 master_DMARE K23 P3-B6 T23 P3-C18 AC23 (TDO - "open") AF19 Gnd (power)C20 master_DMAGN K24 P3-B7 T24 INIT_DONE AC24 CONF_DONE AF20 OE ]C21 master_DMAAS K25 P3-B8 T25 Vcc (power) AC25 Vcc (power) AF21 EXMCS ]C22 master_DRDY ] K26 P3-B9 T26 Vcc (power) AC26 GPI[4] AF22 MEMWR ]C23 P3-A15 AF23 BA[0]C24 P3-A16 AF24 BA[1]C25 Gnd (power) AF25 Gnd (power)C26 Vcc (power) AF26 Vcc (power)

Table 5-1. FPGA Pin-out with Inter-connections (Continued)Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal

FPGAECLK

SMB connector

CLK2SYSCLKTSC695

TSC695 GCLK_0GCLK_1

GCLK1

1

2

3pin AF13

pin A14

J14 connector

J14

GCLK_1CLK2

ECLK

123 J14 / 2-3

J14 / 1-2

GCLK_1 / ECLK

GCLK_1 / CLK2U12

U1

U27

U28

J8

J9

J29

J30

J14

U15U14U13J4


23/69

FPGA


5.4.3 FPGA ExternalClock

Figure 5-4. FPGA External Clock Location

5.5 FPGADownloading

Two ways are available for downloading the FPGA.

5.5.1 Serial PROM No serial PROM is provided with the board. The serial PROM (EPC1) method is possi-ble if no bit-blaster is mounted. The serial PROM shall be mounted on an 8-pin socket(not provided with the board) and can be powered in 5 or 3 Volts.

Figure 5-5. FPGA Serial PROM location

5.5.2 Bit-Blaster The bit-blaster method is available if no serial PROM is mounted.

Figure 5-6. Bit-Blaster Connector

The bit-blaster must always be powered in 5 Volts (J12-4). A DC/DC converter(MAX682) is used. This converter provides 5 Volts, named Vbb, from a source 2.7 Volts

J26

J24J23

J11 J17

J13

J25 J15

J143

X1X2 ECLKJ15 connector

U12

J3

U27

J9

J30

J14 J16

U17

U16U15U14

J29

J31

U28

J26

J3J21

J24

J17

U1U27

J12J13

J25 J15

J27

X1

J29

135246

79810

J12 top view

G n d n . c n . c V c

c G n

d

D a t a 0 n S

T A T U

S

n C O N

F I G

C O N

F_ D O

N E

D C L K


24/69

FPGA


up to 5.5 Volts. Vbb powers the pull-up resistors on INIT_DONE, nCONFIG,CONF_DONE and nSTATUS signals.

Figure 5-7. Bit-Blaster DC/DC Converter

IN

SKIP

SHDN

Gnd PGnd

OUT

Cxn CxpVcc (2.7 to 5.5V)

R = 390K

3

1

2

C = 1uF

C = 2.2uF

Vbb (5V)

C = 47uF

6 7

8

4 5

Gnd

J12-7

tantale

4 . 7 K

4 . 7 K

4 . 7 K

4 . 7 K

I N I T_

D O N E

C O N F

_ D O N

E

n C O N

F I G

n S T A

T U S

R 1 1

R 1 2

R 1 3

R 1 4

C144

C145

U33R33

C146

MAX682


25/69


Section 6DMA

A special feature is proposed to build a DMA master with the FPGA. Then anothereVAB-695, seen as target, can be accessed in DMA slave. To be able to communicatebetween the two eVAB-695s via P1 & P2, the address line RA26 of P1 is driven by theFPGA (pin AB4). Only with an inversion of this line during the DMA master session, the

extended RAM space of the master (address 0x04000000 to 0x0FFFFFFF) can bemapped to the boot-PROM, extended PROM, exchange Memory areas of the slave. Inthe same way a part of the extended I/O space of the master (address 0x14000000 to0x17FFFFFF) can be mapped to the I/O areas 0 to 3 of the slave.

Figure 6-1. DMA - Address 26 Configuration

J6

U1

U7

U8

U9

J28

J5 J4

J18

J19

J18

P1-RA26FPGA-RA26

695E-RA26

123 J18 / 2-3

J18 / 1-2

DMA Off

DMA On

J20


26/69


Section 7TSC695 Power & Clock

The board can be powered (Vcc board) by the connector P1, P2 or/and P3. It can alsobe powered by J20 and J28, allowing to separate the core Vcc and the I/O Vcc on theTSC695.

7.1 TSC695 Power

Figure 7-1. TSC695 Power Configuration

7.2 TSC695 Clocks CLK2 clock can be provided either by an oscillator (X1 - format 1 or 1/2 format) or byJ25 connector.

Vcc(board)

J28 J20c b a c b a

from P1P2P3

VccO(TSC695 I/O)

VccI(TSC695 core)

Gnd

J7J6

U7U14U13J5 J4

J18

J28 J20

J28 J20c b a c b a(PCB) from P1P2P3 (PCB)

Default Connections


27/69


28/69


Section 8Reset, HALT, EWDINT and Status

LEDs

Two dedicated push buttons and four status LEDs are available on front side.SMB connectors can be used to input HALT and EWDINT.

RESET and HALT can be provided by the TAP connector.The other sources for RESET and HALT are managed into the FPGA.

8.1 RESET

8.1.1 Schematic

Figure 8-1. RESET Schematic

4 . 7 K W

BP RESET

"On-Mom"

Other RESET sources

FPGA

SYSRESET

4 . 7 K W

TSC695

4.7mF

4 . 7 K W

pin AE17

65

4

32

1

U30R17

R15

89

10

1112

13

U30

R16

S1

R E S E T

_ H A L T [ 1 ]


29/69

Reset, HALT, EWDINT and Status LEDs


8.1.2 Push ButtonLocation

Figure 8-2. Reset Push Button Location

8.2 HALT

8.2.1 Schematic Figure 8-3. HALT schematic

8.2.2 Push ButtonLocation

Figure 8-4. HALT Push Button Location

J2

J1J23

J10 J11S2S1

D3D1

D2

U29

4 . 7 K W

BP HALT

"On-On"

Other HALT sources

FPGA

SYSHALT

4 . 7 K W

TSC695

4 . 7 K W

SYSHALTSMB connector

pin AE16

65

4

32

1

U31R20

R18

89

10

1112

13

U31

J27

S2

R19

R E S E T

_ H A L T [ 0 ]

J2 J1J23

J10 J11S2S1

D3D1

D2

U29


30/69



8.2.3 SMB ConnectorLocation

Figure 8-5. HALT - SMB Connector Location

8.3 EWDINT EWDINT can be used as NMI. A SMB connector is provided to input this external signal.

Figure 8-6. EWDINT - SMB Connector Location

8.4 Status LEDs

8.4.1 Schematic

Figure 8-7. LED Schematic

J26

J3J21

J24

J17

U1U27

J12

J13

J25 J15

J27

X1

J29

J26J3

J21J24

J17

U1

U27

J12

J13

J25 J15

J27J29

X1

CPUHALT "HALT"4.7KWred

"SYSTEM AVAILABLE"4.7KWgreen

TSC695

"RUN"4.7KWgreen

SYSAVTSC695

ALETSC695

D1

D2

D3


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8.4.2 LEDs Location Figure 8-8. LEDs Location

J2 J1J23

J10 J11S2S1

D3D1

D2

U29


32/69


Section 9Test Points

Table 9-1. Test Points Table

J29

Signal Pin nbr Signal

Gnd - 1 RTC

Gnd - 2 GPI [0]

Gnd - 3 GPI [1]

Gnd - 4 GPI [2]

Gnd - 5 GPI [3]

Gnd - 6 GPI [4]

Gnd - 7 GPI [5]

Gnd - 8 GPI [6]

Gnd - 9 GPI [7]

Gnd - 10 EWDINT

Gnd - 11 SYSCLK

Gnd - 12 RESET

Gnd - 13 SYSRESET ]

Gnd - 14 SYSERR ]

Gnd - 15 CPUHALT ]

Gnd - 16 ROMCS ]

Gnd - 17 MEMCS 0 ]

Gnd - 18 IOSEL 0 ]

Gnd - 19 OE ]

Gnd - 20 MEMWR ]

Gnd - 21 IOWR ]

Gnd - 22 WE ]

Gnd - 23 BUFFEN ]

Gnd - 24 DDIR

Gnd - 25 MHOLD ]

Gnd - 26 INST

Gnd - 27 RA [2]

Gnd - 28 D [0]


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Test Points


Figure 9-1. Test Points Location

Gnd - 29 TxA

Gnd - 30 TxB

Gnd - 31 RxA

Gnd - 32 RxB

J26

U12

J3

J21

J24

J17

U1

U27

U28

J12

J13

J27

J8

J9

J30

J14 J16

U17

U16U15U14U13

J29

pin 1

pin 32

J31


34/69


Section 10Logic Analyzer PODs

Four pods for logic analyzer and are available on board. They can provide inputs for adis-assembler.

10.1 POD 1Table 10-1. Pod 1 Table

Logic Analyzer

J21

Logic Analyses

E2 - Even(red)

A2/A3(brown)

Signal Pin nbr SignalA0/A1

(orange)E1 - Odd(brown)

- 1 39 38 -

- 2

G n d

37 -

K clock CK0 DMAGNT ] 3 36 SYSCLK CK1 J clock

E2:15 A3:7 BRA [31] 4 35 BRA [15] A1:7 E1:15

E2:14 A3:6 BRA [30] 5 40 34 BRA [14] A1:6 E1:14

E2:13 A3:5 BRA [29] 6

G n d

33 BRA [13] A1:5 E1:13

E2:12 A3:4 BRA [28] 7 32 BRA [12] A1:4 E1:12

E2:11 A3:3 BRA [27] 8 31 BRA [11] A1:3 E1:11

E2:10 A3:2 BRA [26] 9 41 30 BRA [10] A1:2 E1:10

E2:9 A3:1 BRA [25] 10 G n d 29 BRA [9] A1:1 E1:9

E2:8 A3:0 BRA [24] 11 28 BRA [8] A1:0 E1:8

E2:7 A2:7 BRA [23] 12 42 27 BRA [7] A0:7 E1:7

E2:6 A2:6 BRA [22] 13

G n d

26 BRA [6] A0:6 E1:6

E2:5 A2:5 BRA [21] 14 25 BRA [5] A0:5 E1:5

E2:4 A2:4 BRA [20] 15 24 BRA [4] A0:4 E1:4

E2:3 A2:3 BRA [19] 16 43 23 BRA [3] A0:3 E1:3

E2:2 A2:2 BRA [18] 17

G n d

22 BRA [2] A0:2 E1:2

E2:1 A2:1 BRA [17] 18 21 BRA [1] A0:1 E1:1

E2:0 A2:0 BRA [16] 19 20 BRA [0] A0:0 E1:0


35/69

Logic Analyzer PODs



Logic Analyzer

J22

Logic Analyzer

E4 - Even(yellow)

D2/D3(blue)

Signal Pin nbr Signal D0/D1(yellow)

E3 - Odd(orange)

- 1 39 38 -

- 2

G n d

37 -

M clock Q0 EXMCS ] 3 36 ALE ] CK2 L clock

E4:15 D3:7 D [31] 4 35 D [15] D1:7 E3:15

E4:14 D3:6 D [30] 5 40 34 D [14] D1:6 E3:14

E4:13 D3:5 D [29] 6

G n d

33 D [13] D1:5 E3:13

E4:12 D3:4 D [28] 7 32 D [12] D1:4 E3:12

E4:11 D3:3 D [27] 8 31 D [11] D1:3 E3:11

E4:10 D3:2 D [26] 9 41 30 D [10] D1:2 E3:10

E4:9 D3:1 D [25] 10 G n d

29 D [9] D1:1 E3:9

E4:8 D3:0 D [24] 11 28 D [8] D1:0 E3:8

E4:7 D2:7 D [23] 12 42 27 D [7] D0:7 E3:7

E4:6 D2:6 D [22] 13

G n d

26 D [6] D0:6 E3:6

E4:5 D2:5 D [21] 14 25 D [5] D0:5 E3:5

E4:4 D2:4 D [20] 15 24 D [4] D0:4 E3:4

E4:3 D2:3 D [19] 16 43 23 D [3] D0:3 E3:3

E4:2 D2:2 D [18] 17

G n d

22 D [2] D0:2 E3:2

E4:1 D2:1 D [17] 18 21 D [1] D0:1 E3:1

E4:0 D2:0 D [16] 19 20 D [0] D0:0 E3:0


36/69

Logic Analyzer PODs



Logic Analyzer

J23

Logic Analyzer

E6 - Even(blue)

C2/C3(white)

Signal Pin nbr Signal C0/C1(grey)

E5 - Odd(green)

- 1 39 38 -

- 2

G n d

37 -

P clock CK3 RESET ] 3 36 IOSEL [0] ] Q1 N clock

E6:15 C3:7 LOCK 4 35 CPUHALT ] C1:7 E5:15

E6:14 C3:6 RLDSTO 5 40 34 SYSERR ] C1:6 E5:14

E6:13 C3:5 MEMCS [0] ] 6

G n d

33 DDIR C1:5 E5:13

E6:12 C3:4 DXFER 7 32 RASI [3] C1:4 E5:12

E6:11 C3:3 RD 8 31 DMAREQ ] C1:3 E5:11

E6:10 C3:2 FLUSH 9 41 30 DMAAS C1:2 E5:10

E6:9 C3:1 INULL 10 G n d

29 DRDY ] C1:1 E5:9

E6:8 C3:0 INST 11 28 RASI [2] C1:0 E5:8

E6:7 C2:7 ROMCS ] 12 42 27 OE ] C0:7 E5:7

E6:6 C2:6 DIA 13

G n d

26 BUFFEN ] C0:6 E5:6

E6:5 C2:5 MEXC ] 14 25 RIZE [1] C0:5 E5:5

E6:4 C2:4 BA [1] 15 24 RASI [1] C0:4 E5:4

E6:3 C2:3 WE ] 16 43 23 MEMWR ] C0:3 E5:3

E6:2 C2:2 MDS ] 17

G n d

22 IOWR ] C0:2 E5:2

E6:1 C2:1 MHOLD ] 18 21 RIZE [0] C0:1 E5:1

E6:0 C2:0 BA [0] 19 20 RASI [0] C0:0 E5:0


37/69


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Section 11Serial Links

11.1 Serial A

Figure 11-1. Serial link A Configuration

11.2 Serial B

Figure 11-2. Serial Link B Configuration

1

J10 front view

J10 / 5

J10 / 3

Gnd

TxA TSC695

J2

J1J23

J10 J11S1

U29

D3D1

D2

S2

J10 / 2RxA TSC695569

23478

J23

J10

D3D1

D2

U29

J11J25

S2

1

J11 front view

J11 / 5

J11 / 3

Gnd

TxB TSC695

J11 / 2RxB TSC695569

23478


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Serial Links


11.3 SUN Connection

Figure 11-3. SUN Connection Lay-out

. . . . . .

. . . . . .. . . . . .

. . . . . .

. . . . . .. . .. . .. . .. . .

. . . . . . . . .. . .

. . . . . . . . .. . .. . . . . .5 Gnd TSC695

eVAB-695E / DB 9 serial port

Pin Nb

(A or B)

Function

SUN / DB 25 serial port

Pin Nb

(both A and B)

Function

2TxA SUN 2 Rx. TSC6953RxA SUN 3 Tx. TSC695

. . . . . .. . . . . . . . .. . . . . .. . .

. . . . . . . . .. . .

. . . . . . . . .. . .. . . . . .5 Gnd TSC695


Pin Nb(A or B)

Function

SUN / DB 25 serial port

Pin Nb(A or B)

Function

2Tx. SUN 2 Rx. TSC6953Rx. SUN 3 Tx. TSC695

7Gnd SUN

. . .. . .

. . . . . .. . . . . .


Pin Nb

( B or A)

Function14TxB SUN

2 Rx. TSC69516RxB SUN 3 Tx. TSC695

. . . . . .. . . . . .

. . . . . .. . . . . .

. . . . . .. . . . . .

7Gnd SUN

. . .. . .

. . .. . .

. . .. . .5 Gnd TSC695


40/69

Serial Links


11.4 PC Connection

Figure 11-4. PC Connection Lay-out

. . . . . .. . . . . . . . .. . . . . .. . .

. . . . . . . . .. . .

. . .. . .. . . . . .5 Gnd TSC695


Pin Nb(A or B)

Function

PC / DB 9 serial port

Pin Nb(COM1 or COM2)

Function

2Rx. PC 2 Rx. TSC6953Tx. PC 3 Tx. TSC695

5Gnd PC


41/69


Section 12Tap Connector

The J13 connector is the TAP connector used for JTAG. It is a male M50 type connector14 leads.

Figure 12-1. Tap Connector Lay-out

TCK can be received a pull-up and/or a pull-down resistor. The default configuration hasno resistor.

TMS, TDI, TRST pads of the TSC695 has an internal pull-up resistor.

J26

J3J21

J24

J17

U1U27

J13J12

J25 J15

J27

X1

J29

101112543

131421

J13 top view

n . c n . c

C P U H

A L T

R E S E

T G n

d

n . c S Y C L

K

T M S T C

K T R

S T

8976

T D O (

T D I 6 9

5 E )

T D I ( T

D O 6 9

5 E )

S Y S H

A L T

S Y S R

E S E T

TCKJ13-11

R 3 4

R 3 5

Vcc

TCKTSC695-pin 142

J17

R7

C129

U33 C145

C146C144

R35 R34

Bottom View


42/69


Section 13Expansion Connectors

13.1 3 x 32 pointsconnector - P1 Table 13-1. P1 Connector Pin Definition

P1

Pin nbr Signal row A Signal row B Signal row C Pin nbr32 Vcc Vcc Vcc 32

31 - - - - - - - - - 3130 D [13] RAPAR RA [25] 30

29 D [12] RA [31] RA [24] 29

28 D [11] RA [30] RA [23] 28

27 D [10] RA [29] RA [22] 27

26 D [09] RA [28] RA [21] 26

25 D [08] RA [27] RA [20] 25

24 D [07] RA [26] RA [19] 24

23 D [06] Gnd RA [18] 23

22 D [05] *8RSIZE [1] RA [17] 22

21 D [04] RSIZE [0] RA [16] 21

20 D [03] Gnd RA [15] 20

19 Gnd RASPAR RA [14] 19

18 SYSCLK D [31] RA [13] 18

17 Gnd D [30] RA [12] 17

16 ALE D [29] RA [11] 16

15 Gnd D [28] RA [10] 15

14 D [02] D [27] RA [09] 14

13 D [01] D [26] RA [08] 13

12 D [00] D [25] RA [07] 12

11 Gnd D [24] RA [06] 11

10 CLK2 D [23] RA [05] 10

9 Gnd D [22] Gnd 9

8 DPAR D [21] RA [04] 87 CB [06] D [20] RA [03] 7

6 CB [05] D [19] RA [02] 6

5 CB [04 D [18] RA [01] 5

4 CB [03] D [17] RA [00] 4

3 CB [02] D [16] BA [01] 3

2 CB [01] D [15] BA [00] 2

1 CB [00] D [14] CPAR 1


43/69

Expansion Connectors



P2

Pin nbr Signal row A Signal row B Signal row C Pin nbr

32 EXTINTACK Vcc slave_DMAREQ ] or DMAREQ ] 32

31 EXTINT[4] Gnd slave_DMAGNT ] or DMAGNT ] 31

30 EXTINT[3] BUFFEN ] slave_DMAAS or DMAAS 30

29 EXTINT[2] DDIR slave_DRDY ] or DRDY ] 29

28 EXTINT[1] DDIR* master _DMAREQ ] or FPGA [pin C19] 28

27 EXTINT[0] WE master_DMAGNT ] or FPGA [pin C20] 27

26 MEXC ] RD master_DMAAS or FPGA [pin C21] 26

25 EWDINT EXMCS ] master_DRDY ] or FPGA [pin C22] 25

24 IWDE MEMCS [9] ] EXT_D_BUFFEN ] or FPGA [pin C6] 24

23 WDCLK MEMCS [8] ] EXT_C_BUFFEN ] or FPGA [pin C7] 23

22 RTC Gnd FPGA [pin C8] 22

21 Tx A MEMCS [7] ] FPGA [pin C10] 21

20 Rx A MEMCS [6] ] FPGA [pin C11] 20

19 Tx B MEMCS [5] ] FPGA [pin C12] 19

18 Rx B MEMCS [4] ] FPGA [pin C16] 18

17 MHOLD ] MEMCS [3] ] FPGA [pin C17] 17

16 MDS ] MEMCS [2] ] FPGA [pin C18] 16

15 INULL MEMCS [1] ] RESET ] 1514 DIA MEMCS [0] ] SYSRESET ] 14

13 FLUSH Vcc CPUHALT ] 13

12 INST Gnd SYSHALT ] 12

11 DXFER ROMCS ] BUSRDY ] 11

10 WRT IOSEL [3] ] SYSAV 10

9 GPI [7] IOSEL [2] ] BUSERR ] 9

8 GPI [6] IOSEL [1] ] SYSERR ] 8

7 GPI [5] IOSEL [0] ] IUERR ] 7

6 GPI [4] IOWR ] LOCK 6

5 GPI [3] MEMWR ] RLDSTO 5

4 GPI [2] OE ] RASI [3] 4

3 GPI [1] - - - RASI [2] 3

2 GPI [0] Gnd RASI [1] 2

1 GPIINT Vcc RASI [0] 1


44/69




P3

Pin nbr Signal row A Signal row B Signal row C Pin nbr

32 FPGA [pin E2] Vcc FPGA [pin V24] 32

31 FPGA [pin E1] Gnd FPGA [pin V23] 31

30 FPGA [pin D26] FPGA [pin P22] FPGA [pin V22] 30

29 FPGA [pin D1] FPGA [pin P5] FPGA [pin V5] 29

28 FPGA [pin N22] FPGA [pin P4] FPGA [pin V4] 28



25 FPGA [pin N3] FPGA [pin N25] FPGA [pin U25] 25

24 FPGA [pin N2] FPGA [pin N24] FPGA [pin U24] 24

23 FPGA [pin M25] FPGA [pin N23] FPGA [pin U23] 23

22 FPGA [pin M24] Gnd FPGA [pin U4] 22

21 FPGA [pin M22] FPGA [pin L26] FPGA [pin U3] 21



18 FPGA [pin M3] FPGA [pin L23] FPGA [pin T23 18

17 FPGA [pin M2] FPGA [pin L22] FPGA [pin T22] 17

16 FPGA [pin C24] FPGA [pin L5] FPGA [pin T5] 16

15 FPGA [pin C23] FPGA [pin L4] FPGA [pin T4] 1514 IWDE FPGA [pin L3] FPGA [pin T3] 14

13 EWDINT Vcc FPGA [pin T2] 13

12 SYSCLK Gnd FPGA [pin R25] 12

11 RESET ] FPGA [pin L2] FPGA [pin R24] 11

10 GPIINT FPGA [pin L1] FPGA [pin R23] 10

9 RTC FPGA [pin K26] FPGA [pin R22] 9

8 GPI [7] FPGA [pin K25] FPGA [pin R5] 8




4 GPI [3] FPGA [pin K4] FPGA [pin P26] 4

3 GPI [2] FPGA [pin K3] FPGA [pin P25] 3

2 GPI [1] Gnd FPGA [pin P24] 2

1 GPI [0] Vcc FPGA [pin P23] 1


45/69



slave_DMAREQ* is DMAREQ* from TSC695 slave_DMAGNT* is DMAGNT* from TSC695 slave_DMAAS is DMAAS from TSC695 slave_DRDY* is DRDY* from TSC695


46/69


Section 14Board Implementation

Figure 14-1. Board Implementation - Lay-out

PROM 40

EWDINT

PROM8

S i m m

S R A M

B

S i m m

S R A M

A

S i m m

P R O M

POD 1

POD 2

POD 4POD 3

LS A LS B P3

P2P1

TSC 695FPGA

E P C 1

B itB lasterTAP

H a l

t R e s e t

Power

H L T R U N

S A V C L K 2

E C L K

10K50

Syshalt

OscillatorsMAX

S R A M

B a n k 0

pin 1

pin A 1

PROM8/40

P a r /

N o

P a r

T e s

t P o i n

t s

W R R O M

G C L K 1 FlashCS

D e b u g

R A 2 6

C S R A M

C S R A M

S I M M B

S I M M A

S R A M

B a n k 1

WDCLK CLK2

SIMMCS

B U F F E N


47/69

Board Implementation


Figure 14-2. Board Implementation - References

J26

U12

J2 J1 J3

J21

J22

J24J23

J10 J11 J17

J7J6

U1

U27

U28

J12J13

S2S1

D3D1

D2

J25 J15

J27

X1U29

J8

J9

J29

J30

J14 J16

U2

U3

U4

U5

U6

U7

U8

U9

U10

U11

U17

U16U15U14U13

J28

J5 J4

J19

J18

J20

X2

eVAB-695E-Rev.D

J31

J32


48/69


Section 15Deviations

15.1 CB[6:0] andDPAR on FPGA

The signals CB[7:0] and DPAR connected on FPGA are those of the TSC695 and notthose buffered for the other space than SRAM. Note that data connected to FPGA are,effectively, those coming from data buffers.

==> Disable the enable buffer for CB[7:0] and DPAR (U26 - xx245) usingEXT_C_BUFFEN on FPGA (pin C7) and drive directly CB[7:0] and DPAR.

15.2 Reset and HALTDriven by JTAGConnector

The "Reset in" and "HALT in" (from JTAG con to FPGA or CPU) are not possible.

==> If these functions are needed, use the 2x n.c pins of the JTAG connector and con-nect them to FPGA, pins AD5 and AD6 ("open").

15.3 TSC695 Signalson FPGA

Note that the following signals are missing:

TMODE[1,0] (not useful)DDIR* (but DDIR exits)

ROMWRT* (on board pulldown)

DEBUG

MDS*

NOPAR*Note: This shall be taken into account in the FPGA implementation.


49/69


Section 16Schematics

The following section illustrates the schematic diagrams for the TSC695 EvaluationBoard.


50/69

Schematics



51/69

Schematics



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Schematics



53/69

Schematics



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Schematics



55/69

Schematics



56/69

Schematics



57/69

Schematics


A

B

A

B


58/69

Schematics


B

A


59/69

Schematics



60/69

Schematics


A

B


61/69

Schematics



62/69

Schematics



63/69

Schematics



64/69

Schematics



65/69

Schematics



66/69

Schematics



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Schematics



68/69


Section 17Revision History

17.1 Changes fromRevision B 08/99to Revision C01/00

1. Changed logic analizer pods signals.

2. Added WDCLK on board.3. New Flash SIMM selection.4. Placed DC/DC convertor for FPGA.5. Buffering of clock signals.

17.2 Changes fromRevision C 01/00to Revision D04/00

1. Updating P3 Connector.2. Schematic for R34/R35 (TAP).

17.3 Changes fromRevision D 04/00to Revision E03/01

1. Permutation of J20 and J28 names.2. Permutation VccO and VccI.3. Addition of board schematics.

17.4 Changes fromRevision E 03/01to Revision F08/03

1. Changing TSC695E to TSC695.2. Changing eVAB-695E to eVAB-695.3. Addition of BUFFEN* controls for on-board data buffers.

17.5 Changes fromRevision F 08/03to Revision G11/05

1. Changing +5V to +VCC (board documentation is applicable for 3V and 5Vboards)

2. Precision on memory mount process (socket versus soldering)3. Precision given on FPGA area


69/69

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to anyintellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMELS TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMELS WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORYWARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULARPURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

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