authors

Shen-Fu Hsiao, Ming-Yu Tsai and Chia-Sheng Wen

by

Deepika Dendi

Introduction

Synthesis flow

Basic PTL Physical cells

One-level PTL Logic cells

Multilevel PTL cells

Improvements

Hybrid PTL/CMOS Synthesis Results

Conclusion

PTL outperforms CMOS for XOR rich applications.

CMOS have edge over PTL in circuits which are not XOR based.

Modified synthesis flow having both CMOS and PTL cells can give better results.

One-level PTL Logic cells

1. If input of mux is connected to Vdd ,replace NMOS by PMOS and remove inverter in MUX. This reduces area, power and improves speed performance. This Mux is called NPMUX.

2. Another improvement is to use the inverted signal available in MUX for signal inversion instead of using inverter

Layout models are created for basic PTL logic cells.

These layout models are used in placement and routing step after synthesis.

Cells are characterized to create synopsis models.

The models have area cost, parasitic capacitance, dynamic leakage power, delay etc.

This information Is used by synthesis and P&R tools to generate physical layout according to the design constraints.

Table V compares area and delay of different pure PTL synthesis methods

Table Vl compares area,delay and power of both area optimized(AO) and delay optimized(DO) results based on different types of cell libraries

1.Pure CMOS 2.Pure PTL

3. Hybrid CMOS/PTL

The paper presented a hybrid methodology that can easily be embedded in cell based design flow.

From the results using 90nm technology, it is found that PTL outperforms over CMOS in power and area. Whereas Hybrid CMOS/PTL gives better results in AO and DO