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Avionics Architecture December 2008

Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

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Page 1: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

Avionics Architecture

December 2008

Page 2: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 2

Avionics

• Hardware & Software• Processor, Buses, Equipments• Command & Control• Telecommand & Telemetry

between 30 and 70 % of the Plateform development cost (typically 50 % for EO satellite)

Page 3: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 3

Avionics: Overview

GroundSegment

PlatformEquipments

PayloadInstruments

PCDU

•AOCS Sensors•PWR System•THERM System•RF System•…

•Optical•Scientific•Telecom•Radionavigation•…

OBC

OBSW

Page 4: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 4

Avionics: Overview

GroundSegment

PlatformEquipments

PayloadInstruments

Command(CMD)

Control

(CTRL)

PCDU

Telecommand(TC)

Telemetry(TM)

Downlink(DL)

Uplink(UL)

Spacelink

Reception(Rx)

Transmission(Tx)

Command(CMD) Control

(CTRL)Data(DAT)

•AOCS Sensors•PWR System•THERM System•RF System•…

•Optical•Scientific•Telecom•Radionavigation•…

OBC

OBSW

Page 5: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 5

Avionics: Overview (cont.)

CDMU

Ground Segment

Platform Equipments

PayloadInstruments

PCDU

MM

Low Throughput(e.g. S Band)

High Throughput(e.g. X Band)

PDHURemoteTerminal

Unit

Page 6: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 6

Avionics: RedundancySensors Test I/F HPC1 out

Local Bus

TC in TM outActuatorsunreg. Power

LB-I/F

MAIN

Module

Processor

LB-I/F

MAIN

Module

Reconfi.

LB-I/F

MAIN

Module

Telecmd

MAIN

Module

Converter

LB-I/F

MAIN

Module

Telemty

CIA

CIA

MAIN

Module

MassMemory

CIA

CIA

RED.

Module

MassMemory

CIA

CIA

LB-I/F

RED.

Module

Telemty

CIA

CIA

LB-I/F

RED.

Module

Telecmd

LB-I/F

RED.

Module

Reconfi.

LB-I/F

RED.

Module

Processor

LB-I/F

RED.

Module

Interface

LB-I/F

MAIN

Module

Interface

RED.

Module

Converter

Sensors Test I/F HPC1 out TC in TM outActuatorsunreg. Power

MIL1553Bus

MIL1553Bus

Page 7: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 7

Avionics: Hostile Environment

• Temperature: extreme conditions• Temperature range solar cells -150 +100 °C• Packaging, isolation and heaters: reduction to -20 +50 °C• Commercial electronics don’t fit the bill : 0 70 °C

(mil range -55 +125 °C)

• Ion radiation : electron, proton, heavy ion (solar flare, van Allen belts)• Cumulated Effect:

• Modification of the component characteristics

• Single Event Effects: • SET: Single Event Transient (glitches) non

destructive• SEU: Single Event Upset (swap) non destructive• SEL: Single Event Latchup (CMOS)• SEB: Single Event Burnout (MOSFET) destructive• SEGR: Single Event Gate Rupture destructive

Page 8: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 8

• Radiation Protections• Shielding• Box design• Positioning in the S/C• Technology choices • Build in electronic protection

• Fault Tolerance• Ability to support temporary or definitive modification or

suppression of functionality• Redondancy

• Processing: Spatial or Temporal Redundancy and Majority Voting• Duplicate the system: when a system is faulty, switch on the other

one• Permit to eliminate the faulty system from the decision path (TMR

technology)• Data Redundancy through coding, (RS, CRC, etc)

• Error Detection and Correction (EDAC) on memory• Memory scrubbing to “clean” changed memory

Avionics: Protection Means

Page 9: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 9

OB Processor: EvolutionMip

s

200

100

50

14

4

2

16 bits2 MIPS

CPU OnlyMil Std

32 bits14 MIPSSparc V7

32 bits84 MIPSSparc V8

Cache

32 bitsPipe Line

Multi Core

Page 10: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 10

OB Memory• Memory types

• PROM (Programmable Read Only Memory)16 – 256 KBBoard boot and init SW

• EPROM (Electrically Programmable Read Only Memory such as Flash) 2 – 8 MBthe mission SW boot container

• SRAM (Static Random Access Memory)4 – 16 MB; the workplace that contains executing SW and variables

• SDRAM (Synchronous Dynamic Random Access Memory) 16 to 512 MBslower RAM typically used for mass storage

SRAM: data bit is stored in the state of a flip-flop (No power for Data Retention)

DRAM: data bit is stored in the electric charge of a nano capacitor (Frequent Refresh Cycles, Volatile)

ROM: uses a metal mask to permanently enable/disable selected transistors instead of storing a charge in them

FLASH: a kind of EEPROM erased and written in large blocks, read in a random access fashion (Non Volatile)

Page 11: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 11

Atmel AT697 Leon Main Features

• Synthesisable Open Source VHDL model of a 32-bit SPARC V8

• Caches: 16 KB Data, 32 KB instructions

• Self standing computer: need only external clock and memory

• 2 timers + watchdog

• 2 UART, 32 parallel I/O

• Fault tolerant (parity, EDAC, TMR)

• Separate DSU (Debug Serial Unit) with normal serial line interface and transaction/instruction trace buffer with 512 entries

• Integrated PCI interface (50 % of chip)

• Virtual latchup free (70 MeV.cm2/mg)

• Radiation up to 300 Krads (Si)

SPARC = Scalable Processor ARChitecture = RISC (Reduced Instruction Set Computer) – 32 bitRISC = Simple instruction set, simple CPU, target = 1 instruction per cycle (without memory R/W)

simple compiler, but needs 40 % bigger code size, better code optimisationSUN SPARC strong points: One of the best performance & power figures per gate

SPARC architecture is no longer evolving but still holds up against other CPU designs

Page 12: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 12

The LEON processor board (unfolded)

ADPMS under test

1,5 Watt300 gram

Proba 2 ADPMS some picturesProba 2 ADPMS some pictures

Page 13: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 13

OB Storage

• Playing Tapes Storage (Till 2000) mass memory was using back and forward playing tapes.

• Solid State Mass Memory (Nowadays)

• Processor board can have 512 MB SDRAM Mass memory

• extra board could hold a GB (with battery back-up)• Very big Mass Memory units with almost unlimited

size can be made in a very compact way (SDRAM or flash EPROM)

• Interface through fast serial links (E.g. SpaceWire)• Mostly used for high resolution image satellites

(e.g. 12 TB at EOL for Sentinel 2)SDRAM, DDR SDRAM, FeRAM, MRAM, CRAM, PRAM

Storage Capacity, Transfer Data Rate, Power for Data Retention, Power for Data Access,

Write Endurance, Sensitivity to Single Event EffectsHigh Speed Error Detection, High Speed Error Correction,

File Management System, Hardware Software Partitioning, Simultaneous Accesses

Page 14: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 14

OB Coms: BudgetFlow (Proba 2) From -> To Mbps

TC segments Ground Spacecraft 2

TM/TC CLCW protocol feedback

TC/TM channels 0,01

TM Packets TM ground 2 x 66

AOCS control OBSW Eqts 0,1

AOCS telemetry Eqts OBSW 0,1

Payload control OBSW Payload 0,1

Payload Telemetry Payload OBSW 0,01

Spacecraft SW housekeeping Eqts OBSW 0,01

REM context writing OBSW REM 0,01

REM Watchdog kicking REM OBSW 0,01

PCM/PDM control OBSW PCM/PDM 0,01

PCM/PDM Telemetry PCM/PDM OBSW 0,01

Spacecraft HW housekeeping Eqts OBSW 0,01

REM housekeeping REM (TM) ground 0,01

Payload Data TM packets Payload TM 20

Page 15: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 15

OB Comms: TaxonomyOn Board Communications

Digital Analog

Multi Drop Buses Point-to-Point Links Point-to-point

Spacewire*Mil-Bus*

Serial Line Digital Converter Switchable Outputs Statuses

I2C CanBus*

On going studies investigate on board wireless communications

Total harness weight (cables and connectors) may reach 6 to 10% of total satellite mass

Single Master Multi Master

OBDH RS-422 RS- 485

*may be redundant

PacketWire

Trade offs to be made:•Power consumption•Silicon surface, board surface•Connectors and wiring harness (6 to 10 % of weight of a satellite)•Performance (throughput, response time)•Isolation and fault propagation•Intelligence required at slave end•Required processing overhead

Page 16: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 16

MilBus Basics

BusController

RemoteTerminal

RemoteTerminal

Equipment

Equipment EquipmentEquipment

Nominal

Redundant• From aircraft industry• Mil-Std-1553-B Standard• Multi Drop Bus• Master/Slave• Single cable• Half Duplex• Asynchronous• Redundant (cross strapping)• 1 Mbps (650 Kbps effective)• Manchester Bi Phase Coding

Rx Cmd Data Word Data Word……………Data Word Status WordBC RTAnswer Time

12 µsInter Msg

4 µs

Answer Time12 µsTx Cmd Data Word……………Data WordRT BC

Inter Msg4 µsData WordStatus Word

Answer Time12 µsTx Cmd ……………Data WordRT RT

Inter Msg4 µsData WordRx Cmd Status Word Status WordAnswer Time

12 µs

1 Msg = 1 to 32 Words

1 Word = 16 Bits

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

P

PData

RT @ T/R RT Address # Words

RT @ Err Inst Svc Reserved Bsy P

CMD

DAT

STS

Page 17: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 17

Reconfiguration Module

• Manages:• The watchdog and associated computer reset and switch-

over logic• The active and cold standby computer• The OBSW version to be loaded at start-up

• It can as well contain:• Context memory:

• Serves as memory for time stamped logs of reconfiguration module, boot and application SW

• Is not reset by a computer boot and regularly transferred to the ground.

• Emergency TC hardware decoder and pulse generator• Central date and time system

Page 18: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 18

Spacewire Basics

• High Speed Serial Link• Fairly Simple• High data rate (up to 400 Mbps) • Low power consumption

• Promoted by ESA, based on IEEE 1533, DS Link, Transputer Technology

• Physical interface requires LVDS-tranceivers

• Packet based <Destination Address><Cargo><End_of_Packet>

• SpaceWire Router connects a number of SpaceWire link interfaces (receiver to transmitter ports)

• Group Adaptive Routing: group of links may be configure to increase throughput (bandwidth sharing) or fault tolerance

• Allow for different topologies following use needs

Page 19: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 19

Avionics: Space Link

• Radio Frequency• L-Band, S-Band, X-Band (Science Data)• Delay and Disruption Tolerant• Tracking and Ranging• Telecommand Uplink• Telemetry Downlink

Page 20: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 20

TC Telecommands

• Receives TC bitstream from antenna/receiver• Hardware decoding of TC data

streams:• Decoding bitstreams, error detection

and correction, de-randomisation, overrun detection

• Isolation of CLTU Command link Transmission Unit (which can contain several TC’s)

• Generate FAR Frame Analysis Report for CLCW, send to TM module (COP-1 protocol)

• Sends emergency TC’s directly to associated pulse generators

• Sending of TC’s to SW decoder• Pulse generation (Pulse Distribution

Unit) • Generates and distributes pulses

without software intervention (reliability, precision)

Page 21: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 21

TM Telemetry - Sources

• Sources of Telemetry allocated to separate VC Virtual Channels• Hardware generated TM’s:

• Emergency telemetry: reporting of essential Telemetry: SW independent – low bandwidth <0,2 Kbps

• Context memory (REM) dumps - < 6Kbps• Processor generated TM

• Event driven TM’s, housekeeping, off-line and Mass Memory data… See SW design

• TM from other sources (payloads, instruments) that inject directly TM without OBSW intervention

• Idle packet generation: to keep the space link operational and synchronised if no real TM is available

• VCM (Virtual Channels Multiplexer):• Time multiplexes VC’s according to BAT (Bandwidth

Allocation Table) on a per frame basis

Page 22: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 22

Telemetry Encoder

• Handles the serialised TM frames:• Addition of Reed-Solomon Error Detection and

Correction symbols• Pseudo-randomisation (to ensure bit transition

density and avoid Tx DC components)• Optional Non-Return-to-Zero Mark encoding• Convolutional Encoding, such as Viterbi (doubles

the bit rate)• Optional Split-Phase Level modulator (doubles bit

rate)• Feed bitstream to radio amplifier/transmitter

Page 23: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 23

OBC: System on Chip• Saab Space, available in 2008 in Atmel

ATC18RHA radiation hard 180 nm standard cell ASIC technology

• LEON2-FT Fault Tolerant SPARC V8 processor, 86 MIPS@100 MHz + FPU

• SPARC V8 Reference Memory Management Unit (MMU)

• Caches: 32 KB instruction, 16 KB data cache

• Extended Debug Support Unit (E-DSU) with 4096 trace lines

• EDAC and automatic scrubbing on large SDRAM, Memory Copy Controller

• 3 High-Speed UART’s

• Three MIL-STD-1553B bus interfaces

• OBDH bus Central Terminal

• 3 PacketWire Receivers & Transmitters

• 8 ECSS-E-50-12A SpaceWire Interfaces capable up to 200 MHz/160 Mbps, Hardware support for Remote Memory Access Protocol.

• 2 Controller Area Network (CAN) interfaces supporting up to 1 Mbps

Page 24: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 24

PROBA 1

DHS

AOCS I/F

Reaction Wheels (4)

Magnetometers (2)

Magnetotorquers (4)

PCS

GPS Receiver

Star Tracker (2)

Head

Head

Receivers (2)Transmitters

(2)

SREM

DEBIE

PPU

CHRIS

Imagers

Other Payloads

BatterySolar Array

Power line

Digital Control line

Proba 1 •Centralized (star) architecture+ Simple design, direct connection with the OBC+ Well adapted to off the shelf equipment integration- Modularity- Harness

• Mass:

•Structure

•Instruments

•Power

•AOCS

•Avionic & dataprocessing

8.5kg8.5kg

• Harness

• RF6kg6kg

8kg8kg

29kg29kg

24kg24kg

9.5kg9.5kg

12kg12kg

Page 25: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 25

Bus architecture:+ std protocol and communication schemes for all nodes+ modularity/ testablity+ Bus traffic solved with central arbitration (CAN, 1553) or protocal arbitration (CAN, Ethernet)-I/F component must be developped- Bus redundancy

Page 26: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 26

PROBA 2 Architecture

Nominal PCI BUS

DATAACQUISITION

MODULE

TELEMETRY &TELECOMMAND

MODULE

SPACECRAFTINTERFACE

MODULE

MAINPROCESSOR

MODULE

CAMERA &MASS MEMORY

MODULE

PCIARBITER

Redundant PCI BUS

DATAACQUISITION

MODULE

TELEMETRY &TELECOMMAND

MODULE

SPACECRAFTINTERFACE

MODULE

MAINPROCESSOR

MODULE

CAMERA &MASS MEMORY

MODULE

PCIARBITER

I/O BUS

EMERGENCYTELECOMMAND

MODULE

•Proba 2• Internal busses (industrial standards)• Main Boards/ generic communication (analog/ digital I/Os, serial lines)

Page 27: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 27

Backplane data throughput

up to 1 GBps

Multi processor support

Processor board- 100MIPS- 64 Mbyte SDRAM- 4 Mbyte SRAM- 4 Mbyte Flash- 256 kByte Prom Telecommand

- 2 Mbps uplink capability- 4 virtual channels or more- configurable N° of MAP-ID- 56 CPDU channels

Telemetry - 100 Mbps downlink- 5 virtual channels- 2 packetwire inputs - full encoding

Mass memory - 4 Gbit- with EDAC

Context memory - 128 kbyte- with EDAC

Communication Interfaces - Up to 25 UART channels - Up to 6 TTC-B-01 channels - a camera interface with frame grabber- 2 packetwires

Analogue Interfaces - Up to 80 analogue inputs- Up to 32 temperature inputs

Time interfaces - 8 programmable clock outputs - 3 clock datation inputs

Power conditioning - Up to 300W satellite peak power - Up to 6 solar sections

Power distribution - 24 outputs of 28V / 50W- current protected with auto restart- switchable or non-switchable- battery undervoltage protected with auto switch off

H/W generated emergency telemetry

Centralised time

synchronisation

H/W recovery

TC decoder

Budgets:Mass 13 kgVolume 455x160x267mmPower 17 W

1 failure tolerant system

Proba2: Main Facts & Figures

Page 28: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 28

Avionics : Proba 3PROPULSION

Nominal

AOCS & FF ADPMS

DWI+FLS

ULLIS

Comms

Payload

Coronagraphelectronics

Primary Tx

Primary Rx

RF

DU

Redundant Tx

Redundant Rx

S-b

and

ante

nnas

Power

Li-ion Battery

Solar arrays

Umbilical to launcher

Umbilical to Occulter

Power & Data Test I/F

Mechanisms

Solar array release mechanism (primary)

SO 28V

SO 28V

TC I/F RS422 UART

NSO 28V

TC I/F RS422 UART

Clock RS422 UART

TM I/F RS422 UART

SO 28V

NSO 28V

Clock

TM I/F RS422 UART

ImageWire

RS422 UART (TBC)Coronagraph

optics & telescope

DMS

PMS

PrimaryDMS

MPM

MCPM

TTM

SIM

DAM0

DAM1

REM

PSM

PDM0

PCM

RedundantDMS

MPM

MCPM

TTM

SIM

DAM0

DAM1Temp sensors 1 to 12 (TBC) on optical bench

Heaters 1 to 6 (TBC) on optical bench

RS422 UART

MIL-STD-1553

SO 28V

SO 28V

ASC

CHU1

CHU2

CHU3

DPU

CPU1Cro

ss c

ou

plin

g

CPU1SO 28V

RS422 UART

Clock

SO 28V

RS422 UART

Clock

SO 28V

RS422 UART

SO 28V

RS422 UART

RS422 UART

RS422 UART

SO 28V

Coronagraph spacecraft

initial date

C:\Documents and Settings\bja\Mina dokument\PROBA-3_Avionics_block_diagram.VSD

page 1 of 2

CSC Diagram

Avionics Concept for PROBA3

print date

last change07-11-08 09:25

07-11-08 09:25

07-11-08 09:25

dd.mm.yyAllA

datechangesissue EN PM PA

Alex Palacioscreator

Dump resistor

SO 28V

SO 28V

SO 28V

RS422 UART

Thermal I/F box

SO 28V

RS422 UART

1N 3DOF - Monoprop (HPGP)

Valve 8

Valve 1

...

10mN 6DOF - Marotta

Valve 16

Valve 1

...

SO 28V

RS422 UART

SO 28V

RS422 UART

SO 28V

RS422 UART

Solar array release mechanism (redundant)Safe & Arm

Safe & Arm

Propulsion DAM

DAM2 DAM2

RS422 UART

PDM1

PDM2

PDM3

PDM4

PDM5

Body panel x 6X 6

RF Metrology

Primary RF metrology

BB

Tx

Rx

Rf sw

itch

Redundant RF metrology

...

BB

Tx

Rx

Rf sw

itch

7 S-band antennas

RS422 UART

SO 28V

RS422 UART

RS422 UART

SO 28V

RS422 UART

X 3

X 3

X 4

X 4

X 3

X 3

PowerLow speed data linkHigh speed data linkAnalog signalDigital signalClock

Mission-Critical Item

X 2

X 2

500µN EP 2DOF - MiDGITS

RF Supply

PCCS XFCU

RF Supply

neutraliser

RS422 UART

X 4

X 6

Thermal control

Heater branches x 2 (for redundancy)

ASSG-RTU

Acc I/F electronics

SAS I/F electronics

SPS I/F electronics

Redundant

Acc I/F electronics

SAS I/F electronics

SPS I/F electronics

Accelerometers

Acc1

Acc5

...

Sun sensor 1*4

SPS

Sensors 1 to 4

Amplifier

GRW-RTU

Nominal

Redundant

Gyros

Gyro1

Gyro5

...

Gyro I/F electronics

Gyro I/F electronics

RW1

RW4

...

RW I/F electronics

RW I/F electronics

RS422 UART

Nom GPS receiver

LNA

Red GPS receiverLNA

PROP-RTU

Nominal

Redundant

I/F electronics

I/F electronics

PROP-RTU

Nominal

Redundant

I/F electronics

I/F electronics

EP-RTU

Nominal

Redundant

I/F electronics

I/F electronics

SO 28V

RS422 UART

PTC-RTU

Redundant

Quick-nut Pyro

22 Thermistor I/F electronics

4 LED drivers

18 HeatersI/F electronics

Nominal

Quick-nut Pyro

22 Thermistor I/F electronics

4 LED drivers

18 HeatersI/F electronics

SO 28V

RS422 UART

SO 28V

RS422 UART

Nom GPS PPS

RS422 UART

RS422 UART

Red GPS PPS

2 x 4 LEDs for RDW

Courtesy Verhaert Space

Comm

ercial In Confdence

Page 29: Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control

30 November 2009 ULG - Avionics Overview 29

PROBA 3:PROPULSION

AOCS & FF ADPMS

Comms

Payload

DARA

Primary Tx

Primary Rx

RF

DU

Redundant Tx

Redundant Rx

S-b

and

ante

nnas

Umbilical to Coronagraph

Power & Data Test I/F

SO 28V

SO 28V

TC I/F RS422 UART

NSO 28V

TC I/F RS422 UART

Clock RS422 UART

TM I/F RS422 UART

SO 28V

NSO 28V

Clock

TM I/F RS422 UART

RS422 UART (TBC)

DMS

PMS

PrimaryDMS

MPM

MCPM

TTM

SIM

DAM0

DAM1

REM

PSM

PDM0

PCM

RedundantDMS

MPM

MCPM

TTM

SIM

DAM0

DAM1

Occulter spacecraft

initial date

C:\Documents and Settings\bja\Mina dokument\PROBA-3_Avionics_block_diagram.VSD

page 2 of 2

OSC Diagram

Avionics Concept for PROBA3

print date

last change07-11-08 09:25

07-11-08 09:25

07-11-08 09:26

dd.mm.yyAllA

datechangesissue EN PM PA

Alex Palacioscreator

10mN 6DOF - Marotta

Valve 8

Valve 1

...

Propulsion DAM

PDM1

PDM2

PDM3

PDM4

PDM5

RF Metrology

Primary RF metrology

BB

Tx

Rx

Rf sw

itch

Redundant RF metrology

...

BB

Tx

Rx

Rf sw

itch

7 S-band antennas

RS422 UART

SO 28V

RS422 UART

RS422 UART

SO 28V

RS422 UART

X 4

X 4

X 3

X 3

X 2

X 2

NSO 28V (thermal)

2 x 4 LEDs for OPS

10-1000µN 6DOF - Nanospace Coldgas

Pod 1

Pod 4

...

DAM2 DAM2

RS422 UART RS422 UART

Power

Li-ion Battery

Solar arrays

Dump resistor

X 3

X 3

X 6

Body panel x 6X 6 PowerLow speed data linkHigh speed data linkAnalog signalDigital signalClock

Mission-Critical Item

SO 28V

RS422 UART

SO 28V

RS422 UART

SO 28V

RS422 UART

SO 28V

RS422 UART

PROP-RTU

Nominal

Redundant

I/F electronics

I/F electronics

PROP-RTU

Nominal

Redundant

I/F electronics

I/F electronics

Thermal control

Heater branches x 2 (for redundancy)

PTC-RTU

Redundant

Quick-nut Pyro

22 Thermistor I/F electronics

4 LED drivers

18 HeatersI/F electronics

Nominal

Quick-nut Pyro

22 Thermistor I/F electronics

4 LED drivers

18 HeatersI/F electronics

ASC

CHU1

CHU2

CHU3

DPU

CPU1Cro

ss c

ou

plin

g

CPU1SO 28V

RS422 UART

Clock

SO 28V

RS422 UART

Clock

RS422 UART

SO 28V

SO 28V

SO 28V

RS422 UART

ASSG-RTU

Nominal

Acc I/F electronics

SAS I/F electronics

SPS I/F electronics

Redundant

Acc I/F electronics

SAS I/F electronics

SPS I/F electronics

Accelerometers

Acc1

Acc5

...

Sun sensor 1*4

GRW-RTU

Nominal

Redundant

Gyros

Gyro1

Gyro5

...

Gyro I/F electronics

Gyro I/F electronics

RW1

RW4

...

RW I/F electronics

RW I/F electronics

RS422 UART

Nom GPS receiver

LNA

Red GPS receiverLNA

RS422 UART

SO 28V

Nom GPS PPS

RS422 UART

RS422 UART

Red GPS PPS

SO 28V

RS422 UART

SO 28V

RS422 UART

Courtesy Verhaert Space

Comm

ercial In Confdence