AVR Microcontroller

Embedded System Designing

Introduced by:Eng. Abd-Elsalam

[email protected]

Introduction. AVR microcontroller Architecture. C Review. Memories in AVR. I/O Ports. Interrupts, “External Interrupts”. Timers/Counters

Timer/counter 0 … 8 bit timer/counter. Timer/counter 1 … 16 bit timer/counter. Timer/counter 2 … 8 bit timer/counter.

Analog comparator “AC”. Analog to digital converter “A/D”. Serial peripheral interface “SPI”. USART. Two wire serial interface “I2C”. Applications “According to the course flow”.

Microprocessor vs. Microcontroller

Micro- Processor

Serial & Parallel Ports

Interrupt

ROMRAM

I/O Port

Timer

Microprocessor:Faster.General purpose.ExpensiveCPU is stand-alone, RAM, ROM, I/O, timer

are separate. Designer can control the amount of ROM,

RAM and I/O ports.It is cheaper compared to the

microcontroller with the same features.

Microcontroller:Slower.Stand alone operation.Cheaper.CPU, RAM, ROM, I/O and timer are all

on a single chip(but fixed amount).for applications in which cost, power and

space are critical.Single Operation.

Memory types:There are several types of memory which is

divided into RAM (Volatile ) and ROM and Flash memory (Non-Volatile) and each type is divided into sub types as follows:

RAM(Random Access Memory):○ SRAM(Static RAM):

Very expensiveVery high performanceConstructed of Flip-Flops

RAM(Random Access Memory):○ DRAM(Dynamic RAM):

Cheap Constructed from Capacitors so it

needs to be refreshed periodically. It is divided into: SDRAM(Synchronous DRAM)- SDR-SDRAM(Single Data Rate)- DDR-SDRAM(Double Data Rate)

○ DDR-SDRAM has better performance and faster than the SDR-SDRAM and it is commonly used now in our computer

RAM(Random Access Memory):○ DRAM(Dynamic RAM):

Cheap Constructed from Capacitors so it

needs to be refreshed periodically. It is divided into: SDRAM(Synchronous DRAM)- SDR-SDRAM(Single Data Rate)- DDR-SDRAM(Double Data Rate)

○ DDR-SDRAM has better performance and faster than the SDR-SDRAM and it is commonly used now in our computer

ROM(Read Only Memory):

○ ROM(ROM)○ PROM(Programmable ROM).○ EPROM (Erasable PROM).○ EEPROM(Electrically Erasable PROM).

Flash Memory:○ It is non-volatile computer memory that

can be electrically erased and reprogrammed. It is a technology that is primarily used in memory cards and USB flash drives for general storage and transfer of data between computers and other digital products. It is a specific type of EEPROM (Electrically Erasable Programmable Read-Only Memory) that is erased and programmed in large blocks

LEDS and Switches:LED(Light Emitting Diode):

○ A light-emitting diode (LED) is a semiconductor diode that emits light when an electrical current is applied in the forward direction of the device, as in the simple LED circuit.

Switches.○ Switches type:

Toggle switch.Pushbutton switch.DIP switch.

Switches○ The shown circuit is a sample

switch active low circuit, when we press on the pushbutton the ATMEL pin will be connected to the ground, otherwise it will be connected to the VCC

Opto-isolators and Opto-couplersThe Opto-coupler consists of the control part

which is the photo-diode and the load part which is the photo-transistor.

When the voltage is applied on the photo-diode, it emits light which turns the photo-transistor on (be in the saturation mode “short circuit”).

It is very fast The Switch ON/OFF speed is up to120 MHz with high Performance Opto-Coupler.

Relays○ All Relays Operate Using

the same principle.○ Consisted of a control circuit ○ has a coil “in the green

color” and a load circuit that has a switch “ in the red color”.

Buffers:○ Buffers are used to protect IC’s

from high current because it passes voltage and holds current

○ Also data buffer is a region of memory used to temporarily hold data while it is being moved from one place to another.

○ Buffers IC’s like 74244, 74245.

AVR AVR microcontrmicrocontroller oller ArchitectuArchitecture.re.

AVR AVR microcontrmicrocontroller oller ArchitectuArchitecture.re.

ATmega16 FeaturesATmega16 Features From the data Sheet.

C Review:C Review: Include Files: “according to Codevision”

AVR header files e.g. mega8535, mega16, 902313, tiny22,…ect.

C header files e.g. math.h, string.h, stdlib.h, stdio.h,...ect.

Other useful header files e.g. Delay.h, lcd.h, spi.h, I2C.h, Gray.h,…ect.

C Review:C Review: C functions

C main function must be endless.Other function could be used.

○ Function prototype declaration.Return-type function-name(Arguments or “the inputs”);

○ Function itself.Return-type function-name(Arguments or “the inputs”){

}

C Review:C Review: Variable Declaration:

Type Size (Bits) Rangebit 1 0 , 1char 8 -128 to 127unsigned char 8 0 to 255signed char 8 -128 to 127int 16 -32768 to 32767short int 16 -32768 to 32767unsigned int 16 0 to 65535signed int 16 -32768 to 32767


Type Size (Bits) Rangelong int 32 -2147483648 to

2147483647unsigned long int 32 0 to 4294967295signed long int 32 -2147483648 to

2147483647float 32 ±1.175e-38 to

±3.402e38double 32 ±1.175e-38 to

±3.402e38


Type Size (Bits) Rangelong int 32 -2147483648 to

2147483647unsigned long int 32 0 to 4294967295signed long int 32 -2147483648 to

2147483647float 32 ±1.175e-38 to

±3.402e38double 32 ±1.175e-38 to

±3.402e38

C Review:C Review: Operators:

Assignment operator (x=y) … (+=, -=, /=, *=) Increment/decrement operator ++/-- Equal operator (==) Less than (<) … less than or equal (<=) Greater than (>) … less than or equal (>=) Not equal (!=) Logical operators:

○ And (&&) Bitwise AND (&)○ Or (||) Bitwise OR(|)○ Not (!) Bitwise XOR(^)○ Complement (~)○ Right shifted (>>) … Left shifted (<<)

If Statement:If(condition is true){Do whatever here…}Else if (another condition is true){Do whatever here…}:.Else{Do a default operation}

If there are no braces the next statement is the only

statement under the condition

C Review:C Review:

The For statementFor(initial; condition ; increment){Do whatever here…}for (count = 100; count > 0; count--)for (count = 0; count < 1000; count += 5)count = 1;for (x=5 ; count < 1000; count++)for (count = 0; count < 100; ){count++;}for (i = 0, j = 999; i < 1000; i++, j--)b[j] = a[i];

C Review:C Review:If there are no braces the next

statement is the only statement under the for

statement

While statementWhile(condition){Do whatever here…}

Do{

}while(condition);

C Review:C Review:

Arrays:○ Char arr1[5];○ Char arr2[]=“legend”;○ Char arr1[5]={1,2,3,4,5};○ Arr1[5] … from arr1[0] to arr1[4]○ Indexed by integer.○ Tow dimensional array x[4][3];

Pointers○ Char *x; char *x=“legend”;○ x++; *x++;○ Char x; &x++; x++;

C Review:C Review:

Pin description: 4 ports A,B,C,D each has 8 pins. RESET input. A low level on this pin

for longer than the minimum pulse length will generate a reset.

XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC.

AREF is the analog reference pin for the A/D Converter.

ATmega16ATmega16

Status Register

Bit 7 – I: Global Interrupt EnableThe Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions.

#asm(‘’sei”); #asm(“cli”);

ATmega16ATmega16

Status Register

Bit 6 – T: Bit Copy Storage Bit 5 – H: Half Carry Flag Bit 4 – S: Sign Bit, S = N ^ V Bit 3 – V: Two’s Complement Overflow Flag Bit 2 – N: Negative Flag Bit 1 – Z: Zero Flag Bit 1 – Z: Zero Flag

ATmega16ATmega16

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls.

The AVR Stack Pointer is implemented as two 8-bit registers.

ATmega16ATmega16

ATmega16 MemoriesATmega16 Memories In-System Reprogrammable Flash Program

Memory

The ATmega16 contains 16K bytes On-chip In-System Reprogrammable Flash memory for program storage.

The Flash is organized as 8K x 16. The Flash memory has an endurance of at least 10,000

write/erase cycles. The ATmega16 Program Counter (PC) is 13 bits wide.

ATmega16 MemoriesATmega16 Memories SRAM Data Memory

1120 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 1024 locations address the internal data SRAM.

ATmega16 MemoriesATmega16 Memories EEPROM Data Memory

The ATmega16 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.

EEPROM Read/Write AccessThere are a several registers we will deal with:○ The EEPROM Address Register – EEARH and EEARL.○ The EEPROM Data Register – EEDR.○ The EEPROM Control Register – EECR.

ATmega16 MemoriesATmega16 Memories The EEPROM Address Register – EEARH and EEARL.

EEPROM Data Register – EEDR.

ATmega16 MemoriesATmega16 Memories The EEPROM Control Register – EECR.

○ Bit 3 – EERIE: EEPROM Ready Interrupt EnableWriting EERIE to one enables the EEPROM Ready Interrupt if the

I-bit in SREG is set.Writing EERIE to zero disables the interrupt. The EEPROM Ready

interrupt generates a constant interrupt when EEWE is cleared.


○ Bit 2 – EEMWE: EEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one cause the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect.When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.


○ Bit 1 – EEWE: EEPROM Write Enable.

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place.

ATmega16 MemoriesATmega16 Memories The following procedure should be followed when

writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEWE becomes zero.2. Wait until SPMEN in SPMCR becomes zero.3. Write new EEPROM address to EEAR (optional).4. Write new EEPROM data to EEDR (optional).5. Write a logical one to the EEMWE bit while writing

a zero to EEWE in EECR.6. Within four clock cycles after setting EEMWE,

write a logical one to EEWE.

ATmega16 MemoriesATmega16 Memories Cautions:

An interrupt between step 5 and step 6 will make the write

cycle fail, since the EEPROM Master Write Enable will time-out.

If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

ATmega16 MemoriesATmega16 Memories Cautions:

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte.

When EEWE has been set; the CPU is halted for two cycles before the next instruction is executed.


○ Bit 0 – EERE: EEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the

EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately.

ATmega16 MemoriesATmega16 MemoriesCautions:

○When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.○The user should poll the EEWE bit before starting the read operation.○ If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

ATmega16 MemoriesATmega16 Memoriesvoid EEPROM_write(unsigned int uiAddress, unsigned char ucData){/* Wait for completion of previous write */while(EECR & (1<<EEWE));/* Set up Address and Data Registers */EEAR = uiAddress;EEDR = ucData;/* Write logical one to EEMWE */EECR |= (1<<EEMWE);/* Start eeprom write by setting EEWE */EECR |= (1<<EEWE);}

ATmega16 MemoriesATmega16 Memoriesunsigned char EEPROM_read(unsigned int uiAddress){/* Wait for completion of previous write */while(EECR & (1<<EEWE));/* Set up Address Register */EEAR = uiAddress;/* Start eeprom read by writing EERE */EECR |= (1<<EERE);/* Return data from Data Register */return EEDR;}

ATmega16 I/O PortsATmega16 I/O Ports Three I/O memory address locations are allocated for each

port, one each for the Data Register, Data Direction Register, and the Port Input Pins.

The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write.

The DDxn bit in the DDRx Register selects the direction of

this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.

ATmega16 I/O PortsATmega16 I/O Ports If PORTxn is written a logic one when the pin is configured

as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin.

If PORTxn is written a logic one when the pin is configured

as an output pin, the port pin is driven high. If PORTxn is written a logic zero when the pin is configured as an output pin, the port pin is driven low.

Reading the Pin Value: Independent of the setting of Data

Direction bit DDxn, the port pin can be read through the PINxn Register bit.

ATmega16 I/O PortsATmega16 I/O Ports Register Description for I/O-Ports: Port A Data Register – PORTA

Port A Data Direction Register - DDRA

Port A Input Pins Address – PINA

ATmega16 I/O PortsATmega16 I/O Ports I/O ports registers are bit-addressable registers, in

codevision you can use this feature… If you want to get the second bit in the register DDRA you simply

say DDRA.1 . If you intend to use IAR compiler - or any other compiler- you

need first to declare the I|O ports that you’ll use as bit-addressable register as following:

Method1Unsigned char porta @ port 0x3b;SFR PORTA =0x3b;#define PORTA (*(volatile unsigned char*)0x3b)

#define bit(x) (1<<(x))DDRA |= bit(1); /*set*/DDRA &= ~bit(1);// clearDDRA ^= bit(1); // complement.

ATmega16 I/O PortsATmega16 I/O Ports Method1

#define bit(x) (1<<(x))

#define setbit(P,B) (P)|= bit(B); /*set*/#define clrbit(P,B) (P) &= ~bit(B); //clear#define cmpbit(P,B) (P)^= bit(B); // complement.

Method2 Typedef struct {

unsigned bit0 :1, bit1 :1, bit2 :1, bit3 :1, bit4 :1, bit5 :1, bit6 :1, bit7 :1,}IOREG;

#define PORTA(*(IOREG *)0x3B)Int i=PORTA.bit1; PORTA.bit1=0;

ATmega85ATmega8535 35 InterruptsInterrupts

ATmegaATmega16 16 InterrupInterruptsts

ATmegaATmega16 16 InterrupInterruptsts

ATmega16 InterruptsATmega16 Interrupts// Interrupt definitions for code vision interrupt [program address] void my_function(void){// Place your code here}

// Interrupt definitions for IAR#pragma vector= program address __interrupt void my_function(void){// Place your code here}

ATmega16 External ATmega16 External interruptsinterrupts The ATmega16 or ATmega8535 has three interrupt INT0,INT1

and INT2 … each of them could be activated on the rising and/or falling edge or level sensed.

To enable any interrupt of them the GICR is used. To select the mode of sensing the MCUCR & MCUCSR is used. To sense the occurrence of the interrupt the CIFR is used. General Interrupt Control Register – GICR

ATmega16 External ATmega16 External interruptsinterrupts MCU Control Register – MCUCR

ATmega16 External ATmega16 External interruptsinterrupts MCU Control Register – MCUCR

ATmega16 External ATmega16 External interruptsinterrupts MCU Control and Status Register – MCUCSR

Bit 6 – ISC2: Interrupt Sense Control 2The asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG I-bit

and the corresponding interrupt mask in GICR are set. If ISC2 is written to zero, a falling edge on INT2 activates the interrupt. If ISC2 is written to one, a rising edge on INT2 activates the interrupt. Edges on INT2 are registered asynchronously. When changing the ISC2 bit, an interrupt can occur. Therefore, it is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally, the INT2 Interrupt Flag should be cleared by writing a logical one to its Interrupt Flag bit (INTF2) in the GIFR Register before the interrupt is re-enabled.

ATmega16 External ATmega16 External interruptsinterrupts#include <mega8535.h>

// External Interrupt 0 service routineinterrupt [EXT_INT0] void ext_int0_isr(void){// Place your code herePORTC++;}

void main(void){PORTC=0x00;DDRC=0xFF;

GICR|=0x40;MCUCR=0x02;MCUCSR=0x00;GIFR=0x40;#asm("sei")

while (1);}

8-bit Timer/Counter0 8-bit Timer/Counter0 with PWM with PWM Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter

module. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source, The

Timer/Counter is inactive when no clock source is selected When no clock source is selected the timer is stopped.

The clock source is selected by the Clock Select logic which is controlled by the clock select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0).

Timer/Counter Interrupt Mask Register – TIMSK : to Enable the timer interrupts.

Timer/Counter Interrupt Flag Register – TIFR: to monitor the timer interrupts

Timer/counter Register (TCNT0): hold the count value Output compare Register (OCR0): hold the value to be compared with

the value in TCNT0.

8-bit Timer/Counter0 8-bit Timer/Counter0 with PWM with PWM Timer/Counter Register (TCNT0)

Output Compare Register (OCR0)

8-bit Timer/Counter0 8-bit Timer/Counter0 with PWM with PWM Timer/Counter Control Register – TCCR0


Modes of Operation: The mode of operation, i.e., the behavior of the Timer/Counter and the

output compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits.


Modes of Operation: Normal Mode: In this mode the counting direction is always up

(incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value and

then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero.

The output compare unit can be used to generate interrupts at some given time. Using the output compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.


Modes of Operation: CTC Mode “Clear Timer On Compare”: In CTC mode the counter is

cleared to zero when the counter value (TCNT0) matches the OCR0. The OCR0 defines the top value for the counter, hence also its resolution.

This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0, and then counter (TCNT0) is cleared.

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0 Flag.


Modes of Operation: For generating a waveform output in CTC mode, the OC0 output can be

set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM01:0 = 1). The OC0 value will not be visible on the port pin unless the data direction for the pin is set to output.


The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0 is set to zero (0x00). The waveform frequency is defined by the following equation:

The “N” variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the normal mode of operation, the TOV0 Flag is set in the same

timer clock cycle that the counter counts from MAX to 0x00.

8-bit Timer/Counter0 8-bit Timer/Counter0 with PWM with PWM

In CTC Mode:


In CTC Mode:


Modes of Operation: Fast PWM Mode: The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3)

provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope

operation (saw-tooth wave form). The counter counts from BOTTOM to MAX then restarts from BOTTOM. The generated wave form change from zero volt to five volt, then reset to zero.


Modes of Operation: Fast PWM Mode- In non-inverting Compare Output mode, the Output Compare (OC0) is

cleared on the Compare Match between TCNT0 and OCR0, and set at BOTTOM.

- In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM.


In Fast PWM Modethe counter is incremented until the counter value matches the MAX value.

The counter is then cleared at the following timer clock cycle.


Modes of Operation: Phase Correct PWM Mode:

The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation (triangular wave form). The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM.


Modes of Operation: Phase Correct PWM Mode:In non-inverting Compare Output mode, the Output Compare (OC0) is

cleared on the Compare Match between TCNT0 and OCR0 while up-counting, and set on the Compare Match while down-counting. In inverting Output Compare mode, the operation is inverted.


Modes of Operation: Phase Correct PWM Mode:The dual-slope operation has lower maximum operation frequency than

single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits.


In phase correct PWM mode: the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle.


Bit 7 – FOC0: Force Output CompareThe FOC0 bit is only active when the WGM00 bit specifies a non-PWM

mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0 output is changed according to its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare.

A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP.

8-bit Timer/Counter0 8-bit Timer/Counter0 with PWM with PWM Timer/Counter Interrupt Mask Register – TIMSK

Bit 0 – TOIE0: Timer/Counter0 Timer Overflow Interrupt Enable

Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable

8-bit Timer/Counter0 8-bit Timer/Counter0 with PWM with PWM Timer/Counter Interrupt Flag Register – TIFR

Bit 0 – TOV0: Timer/Counter0 Overflow Flag Bit 1 – OCF0: Output Compare Flag 0

16-bit Timer/Counter116-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution

timing (event management), wave generation, and signal timing measurement. The main features are: True 16-bit Design (i.e., Allows 16-bit PWM) Two Independent Output Compare Units Double Buffered Output Compare Registers One Input Capture Unit Input Capture Noise Canceller Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator External Event Counter Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

16-bit Timer/Counter116-bit Timer/Counter1 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source, The

Timer/Counter is inactive when no clock source is selected When no clock source is selected the timer is stopped.

The clock source is selected by the Clock Select logic which is controlled by the clock select (CS02:0) bits located in the Timer/Counter Control Register (TCCR1B).

The Mode of operation is selected by (TCCR1A) and (TCCR1B). Timer/Counter Interrupt Mask Register – TIMSK : to Enable the timer

interrupts. Timer/Counter Interrupt Flag Register – TIFR: to monitor the timer interrupts Timer/counter Register (TCNT1)hold the count value Output compare Register (OCR1A/B): hold the value to be compared with the

value in TCNT0. The input capture unit capture the timer value in the Input capture register

(ICR1). Each of (TCNT1, OCR1A, OCR1B, ICR1) is a 16-bit register divided into high and

low.

8-bit Timer/Counter18-bit Timer/Counter1 Timer/Counter1 – TCNT1H and TCNT1L

Output Compare Register 1 A (OCR1AH and OCR1AL)

Output Compare Register 1 B (OCR1BH and OCR1BL)

8-bit Timer/Counter18-bit Timer/Counter1 Input Capture Register 1 (ICR1H and ICR1L)

When ever edge change is occurred on the ICP1 the value of the timer which is in the TCNT1 will be copied in the ICR1. the Analog comparator output (ACO) inThe Analog comparator control and status Register (ACSR) could be used in stead of theICP to trigger the input capture unit.

8-bit Timer/Counter18-bit Timer/Counter1 Timer/Counter1 Control Register A – TCCR1A

Bits from 7:4 in Non PWM modes.


Bits from 7:4 in Fast PWM modes.


Bits from 7:4 in Phase correct PWM modes.


Bit 3 – FOC1A: Force Output Compare for Channel A Bit 2 – FOC1B: Force Output Compare for Channel B

it is the value present in the COM1x1:0 bits that determine the effect of the forced compare.

A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP.

FOC1A/FOC1B bits are always read as zero.

8-bit Timer/Counter18-bit Timer/Counter1 Timer/Counter1 Control Register B – TCCR1B

Wave Generation Mode Bits WGM13:10

8-bit Timer/Counter18-bit Timer/Counter1 Wave Generation Mode Bits

8-bit Timer/Counter18-bit Timer/Counter1 Timer/Counter1 Control Register B – TCCR1B

Bits from 0:2 are the clock Select bits as in timer 0.

Bit 7 – ICNC1: Input Capture Noise Canceler Bit 6 – ICES1: Input Capture Edge Select

8-bit Timer/Counter18-bit Timer/Counter1 Timer/Counter Interrupt Mask Register – TIMSK(1)

Timer/Counter Interrupt Flag Register – TIFR

8-bit Timer/Counter18-bit Timer/Counter1 Modes of Operation:

Normal Mode:The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this

mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero.

The output compare units can be used to generate interrupts at some given time. Using the output compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.


Clear Timer on Compare: In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the

OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events.


Fast PWM ModeThe fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5,6,7,14,

or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM.


Phase Correct PWM Mode.The phase correct Pulse Width Modulation or phase correct PWM mode

(WGM13:0 = 1,2,3,10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM.

The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or

defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).


Phase Correct PWM Mode.

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AVR Microcontroller