Basic Computer Organization-2013 HGS REV

8/13/2019 Basic Computer Organization-2013 HGS REV

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Digital SystemsBasic Computer Organization & Design


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Basic Computer Organization & Design

Instruction Codes

Computer Registers

Computer Instructions

Timing and Control

Instruction Cycle

Memory Reference Instructions

Complete Computer Description

Design of Basic Computer

Design of Accumulator Logic


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Computer Organization

To implement a stored program computer which can execute a set of

instructions. (A stored program computer behaves as different machines by loading

different programs, i.e., sequences of instructions.)


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Computer Organization, contd.

Computer hardware = registers + ALU + bus (data path) + control unit

The computer goes through instruction cycles: Fetch an instruction from memory

Decode the instruction to a sequence of control signals

Execute the decoded sequence of microoperations

Control unit: Instruction a timed sequence of control signals to trigger

microoperations Input/output is implemented using an interrupt cycle


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Introduction

Every different processor type has its own design (different registers,

buses, microoperations, machine instructions, etc)

The modern processor is a very complex device, which contains

Many registers

Multiple arithmetic units, for both integer and floating point calculations

The ability to pipeline several consecutive instructions to speed execution

Etc.

However, to understand how processors work, we will start with a

simplified processor model (similar to what real processors were like

~25 years ago)

M. Morris Mano introduces a simple processor model he calls the

Basic Computer

We will use this to introduce processor organization and the

relationship of the RTL model to the higher level computer processor


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The Basic Computer

The Basic Computerhas two components, a processorand memory

The memory has 4096 words in it 4096 = 212, so it takes 12 bits to select a word in memory

Each word is 16 bits long Store each instruction code(program) and operand (data)

CPU RAM0

4095

015


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Instructions (Instruction Codes)

Program A sequence of (machine) instructions

(Machine) Instruction A group of bits that tell the computer toperform a specific

operation(a sequence of microoperation)

The instructions of a program, along with anyneeded data are stored in memory

The CPU reads the next instruction from memory

It is placed in an Instruction Register(IR)

Control circuitry in the control unit then translatesthe instruction into the sequence of microoperations

necessary to implement it


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Instruction Format

A computer instruction is often divided into two parts

An opcode(Operation Code) that specifies the operation for that instruction

An addressthat specifies the registers and/or locations in memory to use for

that operation

In the Basic Compu ter, since the memory contains 4096 (= 212)

words, we needs 12 bits to specify which memory address this

instruction will use In the Basic Compu ter, bit 15 of the instruction specifies the

addressing mode(0: direct addressing, 1: indirect addressing)

Since the memory words, and hence the instructions, are 16 bits

long, that leaves 3 bits for the instructions opcode

Opcode Address

Instruction Format

15 14 12 0

I

11

Addressing

mode


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Addressing Modes

The address field of an instruction can represent either

Direct address: the address in memory of the data to use (the address of the operand), or Indirect address: the address in memory of the address in memory of the data to use

Effective Address (EA)

The address, that can be directly used without modification to access an operand for acomputation-type instruction, or as the target address for a branch-type instruction


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Processor Registers

A processor has many registers to hold instructions, addresses, data, etc.

The Program Counter(PC) holds the memory address of the next instruction

to be read from memory after the current instruction is executed Since the memory in the Basic Computeronly has 4096 locations, the PC only needs 12 bits

Instruction words are read and executed in sequence unless a branch instruction is

encountered

A branch instruction calls for a transfer to a nonconsecutive instruction in the program

The address part of a branch instruction is transferred to PC to become the address of the nextinstruction

To read an instruction, the memory read cycle is initiated, and PC is incremented by one (next

instruction fetch)

In direct or indirect addressing, the processor needs to keep track of what

locations in memory it is addressing: TheAddress Register(AR) is used for

this The AR is a 12 bit register in the Basic Computer

When an operand is found, using either direct or indirect addressing, the data

stored in its effective address is placed in the Data Register(DR). The

processor then uses this value as data for its operation


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Processor Registers

The Basic Compu ter has a single general purpose registerthe

Accumulator(AC)

The significance of a general purpose register is that it can be referred to in

instructions e.g. load AC with the contents of a specific memory location; store the contents of AC into a

specified memory location

Often a processor will need a scratch register to store intermediate results orother temporary data during processing; in the Basic Compu ter this is the

Temporary Register(TR)

The Basic Compu ter uses a very simple model of input/output (I/O)

operations

Input devices can send 8 bits of character data to the processor

The processor can send 8 bits of character data to output devices

The Input Register(INPR) holds an 8 bit character obtained from an input

device

The Output Register(OUTR) holds an 8 bit character to be sent to an output

device


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Basic Computer Registers

List of BC Registers

DR 16 Data Register Holds memory operand

AR 12 Address Register Holds address for memory

AC 16 Accumulator Processor register

IR 16 Instruction Register Holds instruction code

PC 12 Program Counter Holds address of instruction

TR 16 Temporary Register Holds temporary data

INPR 8 Input Register Holds input character

OUTR 8 Output Register Holds output character

Registers in the Basic Computer

11 0PC

15 0

IR

15 0TR

7 0

OUTR

15 0DR

15 0

AC

11 0

AR

INPR

0 7

Memory

4096 x 16

CPU


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Common Bus System

The registers in the BasicComputerare connected using a

bus

This gives a savings in circuitry

over complete connections

between registers


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Common Bus System

The Basic Computer has eight registers, a memory unit, and a

control unit. Paths must be provided to transfer information from one register to

another and between memory and registers.

A more efficient scheme for transferring information in a system with

many registers is to use a common bus.

The connection of the registers and memory of the Basic Computerto a common bus system:

The outputs of seven registers and memory are connected to the common

bus

The specific output is selected by mux(S0, S1, S2) :

Memory(7), AR(1), PC(2), DR(3), AC(4), IR(5), TR(6) When LD(Load Input) is enabled, the particular register receives the data from

the bus

Control Input: LD, INR, CLR, Write, Read

Load input (LD): Enables the input of a register connected to the common bus

Increment input (INR): Increments the contents of a register

Clear input (CLR): Clear the contents of a register to zero


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Common Bus System

Three control lines, S2, S1, and S0control which register the bus

selects as its input

Either one of the registers will have its load signal activated, or

the memory will have its read signal activated

Will determine where the data from the bus gets loaded

The 12-bit registers, AR and PC, have 0s loaded onto the bus in

the high order 4 bit positions

When the 8-bit register OUTR is loaded from the bus, the data

comes from the low order 8 bits on the bus

0 0 0 x0 0 1 AR0 1 0 PC0 1 1 DR

1 0 0 AC1 0 1 IR1 1 0 TR1 1 1 Memory

S2S1S0 Register


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Basic Computer Instructions

3 Instruction Code Formats:

Memory-Reference Instruction

Register-Reference Instruction

Input-Output Instruction

I Opcode Address

15 14 12 11 0

0 1 1 1 Register Operation

15 14 12 11 0

1 1 1 1 I/O Operation

15 14 12 11 0

Hex Code

Symbol I = 0 I = 1 Description

AND 0xxx 8xxx And memory word to ACADD 1xxx 9xxx Add memory word to AC

LDA 2xxx Axxx Load memory word to AC

STA 3xxx Bxxx Store content of AC in memory

BUN 4xxx Cxxx Branch unconditionally

BSA 5xxx Dxxx Branch and Save return address

ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E

CMS 7200 Complement AC

CME 7100 Complement E

CIR 7080 Circulate right AC and E

CIL 7040 Circulate left AC and E

INC 7020 Increment AC

SPA 7010 Skip next instruction if AC positive

SNA 7008 Skip next instruction if AC negativeSZA 7004 Skip next instruction if AC zero

SZE 7002 Skip next instruction if E is 0

HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC

SKI F200 Skip on input flag

SKO F100 Skip on output flag

ION F080 Interrupt OnIOF F040 Interrupt Off

I=0 : Direct,I=1 : Indirect


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Basic Computer Instructions

Basic Computer Memory Reference Instruction Format Indirect bit, bit 15

3-bit opcode, bits 14-12

23= 8 possible instructions

This leaves 12 bits for the address, bits 11-0

212= 22 210= 4K = 4096 16-bit words

15 14 12 11 0

I Opcode Address

Memory-Reference Instructions (OP-code = 000 ~ 110)


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Instruction Set Completeness

Instruction Types

A computer should have a set of instructions so that the user can

construct machine language programs to evaluate any function that isknown to be computable.

Functional Instructions:

- Arithmetic, logic, and shift instructions- ADD, CMA, INC, CIR, CIL, AND, CLA

Transfer Instructions:- Data transfers between the main memory

and the processor registers

- LDA, STA

Control Instructions:- Program sequencing and control

- BUN, BSA, ISZ

Input/Output Instructions:- Input and output

- INP, OUT


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Control Unit

Control Unit (CU) of a processor translates frommachine instructions to the control signals for the

microoperations that implement them

Control units are implemented in one of two ways1. HardwiredControl

CU is made up of sequential and combinational circuits to

generate the control signals

2. MicroprogrammedControl

A control memory on the processor contains microprograms thatactivate the necessary control signals

We will consider a hardwired implementation of the

control unit for the Basic Computer


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Instruction Cycle

In the Basic Compu ter, a machine instruction is executed in the

following cycle:1. Fetch an instruction from memory

2. Decode the instruction

3. Read the effective address from memory if the instruction has an indirect

address

4. Execute the instruction

After an instruction is executed, the cycle starts again at step 1,

for the next instruction

Note: Every different processor has its own (different) instruction

cycle

The fetch and decode phases of the instruction cycle consists of

the following microoperations synchronized with the timing

signals (clocking principle).

T0: AR PC

T1: IR M[AR], PC PC + 1

T2: D0, ..., D7 Decode IR(12-14), AR IR(0-11), I IR(15)


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Instruction Cycle

T0: Since only AR is connected to the address inputs of memory, the

address of instruction is transferred from PC to AR.1. Place the content of PC onto the bus by making the bus selection inputs S2S1S0=

010.

2. Transfer the content of the bus to AR by enabling the LD input to AR

( AR PC).

T1: The instruction read from memory is then placed in the instruction

register IR. At the same time, PC is incremented to prepare for the

address of the next instruction.1. Enable the read input of the memory.

2. Place the content of memory onto the bus by making the bus selection inputs

S2S1S0= 111. (Note that the address lines are always connected to AR, and we

have already placed the next instruction address in AR.)

3. Transfer the content of the bus to IR by enabling the LD input to IR (IRM[AR]).

4. Increment PC by enabling the INR input of PC ( PC PC + 1 ).

T2: The opcode in IR is decoded; the indirect bit is transferred to I; the

address part of the instruction is transferred to AR. (See the common

bus skeleton diagram.)


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Instruction Cycle

Control circuit for

instruction fetch


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Determine the Type of Instruction

D'7IT3: AR M[AR], indirect memory transfer

D'7I'T3: Nothing, direct memory transfer

D7I'T3: Execute a register-reference instructionD7IT3: Execute an input-output instruction


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Instruction CycleMemory Reference

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Basic Computer Organization-2013 HGS REV