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Basic Computer Organization Chapter 2 S. Dandamudi

Basic Computer Organization Chapter 2 S. Dandamudi

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  • Basic Computer OrganizationChapter 2S. Dandamudi

    S. Dandamudi

  • OutlineBasic componentsThe processorExecution cycleSystem clockNumber of addresses3-address machines2-address machines1-address machines0-address machinesLoad/store architecture

    Flow controlBranchingProcedure callsMemoryBasic operationsTypes of memoryStoring multibyte dataInput/OutputPerformance: Data alignment2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Basic ComponentsBasic components of a computer systemProcessorMemoryI/OSystem busAddress busData busControl bus2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Basic Components (contd)2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • The ProcessorProcessor can be thought of executing Fetch-decode-execute cycle foreverFetch an instruction from the memoryDecode the instructionFind out what the operation isExecute the instructionPerform the specified operation2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Instruction Execute Cycle

    S. Dandamudi

  • Instruction Execution Cycle cont'dInstruction FetchInstruction DecodeOperand FetchExecute Result Writeback

    S. Dandamudi

  • The Processor (contd)System clockProvides timing signal to synchronize the operations of the system.

    Clock period = (instruction execution time) 2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *1Clock frequency

    S. Dandamudi

  • Number of AddressesFour categories3-address machines2 for the source operands and one for the result2-address machinesOne address doubles as source and result1-address machineAccumulator machinesAccumulator is used for one source and result0-address machinesStack machinesOperands are taken from the stackResult goes onto the stack2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Number of Addresses (contd)Three-address machinesTwo for the source operands, one for the resultRISC processors use three addressesSample instructionsadd dest,src1,src2 ; M(dest)=[src1]+[src2] sub dest,src1,src2 ; M(dest)=[src1]-[src2] mult dest,src1,src2 ; M(dest)=[src1]*[src2]2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Number of Addresses (contd)ExampleC statementA = B + C * D E + F + AEquivalent code:mult T,C,D ;T = C*Dadd T,T,B ;T = B+C*Dsub T,T,E ;T = B+C*D-Eadd T,T,F ;T = B+C*D-E+Fadd A,T,A ;A = B+C*D-E+F+A2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Number of Addresses (contd)Two-address machinesOne address doubles (for source operand & result)Last example makes a case for itAddress T is used twiceSample instructionsload dest,src ; M(dest)=[src] add dest,src ; M(dest)=[dest]+[src] sub dest,src ; M(dest)=[dest]-[src] mult dest,src ; M(dest)=[dest]*[src]2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Number of Addresses (contd)ExampleC statementA = B + C * D E + F + AEquivalent code:load T,C ;T = Cmult T,D ;T = C*Dadd T,B ;T = B+C*Dsub T,E ;T = B+C*D-Eadd T,F ;T = B+C*D-E+Fadd A,T ;A = B+C*D-E+F+A2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Number of Addresses (contd)One-address machinesUses special set of registers called accumulatorsSpecify one source operand & receive the resultCalled accumulator machinesSample instructionsload addr ; accum = [addr] store addr ; M[addr] = accum add addr ; accum = accum + [addr] sub addr ; accum = accum - [addr] mult addr ; accum = accum * [addr] 2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Number of Addresses (contd)ExampleC statementA = B + C * D E + F + AEquivalent code:load C ;load C into accummult D ;accum = C*Dadd B ;accum = C*D+Bsub E ;accum = B+C*D-Eadd F ;accum = B+C*D-E+Fadd A ;accum = B+C*D-E+F+Astore A ;store accum contents in A2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Number of Addresses (contd)Zero-address machinesStack supplies operands and receives the resultSpecial instructions to load and store use an addressCalled stack machines (Ex: HP3000, Burroughs B5500)Sample instructionspush addr ; push([addr]) pop addr ; pop([addr]) add ; push(pop + pop) sub ; push(pop - pop) mult ; push(pop * pop) 2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Number of Addresses (contd)ExampleC statementA = B + C * D E + F + AEquivalent code:push E subpush C push Fpush D addMult push Apush B addadd pop A2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Load/Store ArchitectureInstructions expect operands in internal processor registersSpecial LOAD and STORE instructions move data between registers and memoryRISC and vector processors use this architectureReduces instruction length2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Load/Store Architecture (contd)Sample instructionsload Rd,addr ;Rd = [addr] store addr,Rs ;(addr) = Rs add Rd,Rs1,Rs2 ;Rd = Rs1 + Rs2sub Rd,Rs1,Rs2 ;Rd = Rs1 - Rs2mult Rd,Rs1,Rs2 ;Rd = Rs1 * Rs2

    2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Number of Addresses (contd)ExampleC statementA = B + C * D E + F + AEquivalent code:load R1,B mult R2,R2,R3load R2,C add R2,R2,R1load R3,D sub R2,R2,R4load R4,E add R2,R2,R5load R5,F add R2,R2,R6load R6,A store A,R22005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Flow of ControlDefault is sequential flowSeveral instructions alter this default executionBranchesUnconditionalConditionalProcedure callsParameter passingRegister-basedStack-based2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Flow of Control (contd)BranchesUnconditionalbranch targetAbsolute addressPC-relativeTarget address is specified relative to PC contentsExample: MIPSAbsolute addressj targetPC-relativeb target2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Flow of Control (contd)2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Flow of Control (contd)BranchesConditionalJump is taken only if the condition is metTwo typesSet-Then-JumpCondition testing is separated from branchingCondition code registers are used to convey the condition test resultExample: Pentium codecmp AX,BXje target2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Flow of Control (contd)Test-and-JumpSingle instruction performs condition testing and branchingExample: MIPS instructionbeq Rsrc1,Rsrc2,targetJumps to target if Rsrc1 = Rsrc22005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Flow of Control (contd)Procedure callsRequires two pieces of information to return End of procedurePentiumuses ret instructionMIPSuses jr instructionReturn addressIn a (special) registerMIPS allows any general-purpose registerOn the stackPentium2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Flow of Control (contd)2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Flow of Control (contd)Parameter passingRegister-basedInternal registers are used FasterLimit the number of parametersDue to limited number of available registersStack-basedStack is usedSlowerRequires memory accessGeneral-purposeNot limited by the number of registers2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • MemoryMemory can be viewed as an ordered sequence of bytesEach byte of memory has an addressMemory address is essentially the sequence number of the byteSuch memories are called byte addressable Number of address lines determine the memory address space of a processor2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Memory (contd)Two basic memory operationsRead operation (read from memory)Write operation (write into memory)Access timeTime needed to retrieve data at addressed locationCycle timeMinimum time between successive operations2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Memory (contd)Steps in a typical read cyclePlace the address of the location to be read on the address busActivate the memory read control signal on the control busWait for the memory to retrieve the data from the addressed memory locationRead the data from the data busDrop the memory read control signal to terminate the read cycleA simple Pentium memory read cycle takes 3 clocksSteps 1&2 and 4&5 are done in one clock cycle eachFor slower memories, wait cycles will have to be inserted2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Typical read cycle2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

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  • Memory (contd)Steps in a typical write cyclePlace the address of the location to be written on the address busPlace the data to be written on the data busActivate the memory write control signal on the control busWait for the memory to store the data at the addressed locationDrop the memory write control signal to terminate the write cycleA simple Pentium memory write cycle takes 3 clocksSteps 1&3 and 4&5 are done in one clock cycle eachFor slower memories, wait cycles will have to be inserted2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Memory (contd)Some properties of memoryRandom accessAccessing any memory location takes the same amount of timeVolatilityVolatile memoryNeeds power to retain the contentsNon-volatile memoryRetains contents even in the absence of powerBasic types of memoryRead-only memory (ROM)Read/write memory (RAM)2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Memory (contd)Read-only memory (ROM)Cannot be written into this type of memoryNon-volatile memoryMost are factory programmed (i.e., written)Programmable ROMs (PROMs)Can be written once by userA fuse is associated with each bit cellSpecial equipment is needed to write (to blow the fuse)PROMS are usefulDuring prototype developmentIf the required quantity is smallDoes not justify the cost of factory programmed ROM 2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Memory (contd)Erasable PROMs (EPROMs)Can be written several timesOffers further flexibility during system prototypingCan be erased by exposing to ultraviolet lightCannot erase contents of selected locationsAll contents are lostElectrically erasable PROMs (EEPROMs)Contents are electrically erasedNo need to erase all contentsTypically a subset of the locations are erased as a groupMost EEPROMs do not provide the capability to individually erase contents of a single location2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Memory (contd)Read/write memoryCommonly referred to as random access memory (RAM)Volatile memoriesTwo basic typesStatic RAM (SRAM)Retains data with no further maintenanceTypically used for CPU registers and cache memoryDynamic RAM (DRAM)A tiny capacitor is used to store a bitDue to leakage of charge, DRAMs must be refreshed to retain contentsRead operation is destructive in DRAMs2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Memory (contd)DRAM typesFPM DRAMsFPM = Fast Page ModeEDO DRAMsEDO = Extended Data OutputUses pipelining to speedup accessSDRAMsUse an external clock to synchronize data outputAlso called SDR SDRAMs (Single Data Rate)DDR SDRAMsDDR = Double Data Rate Provides data on both falling and rising edges of the clockRDRAMsRambus DRAM2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

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  • Storing Multibyte Data2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

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  • Storing Multibyte Data (contd)Little endianUsed by Intel IA-32 processorsBig endianUsed most processors by defaultMIPS supports both byte orderingsBig endian is the defaultNot a problem when working with same type of machinesNeed to convert the format if working with a different machinePentium provides two instructions for conversionxchg for 16-bit databswap for 32-bit data2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

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  • Input/OutputTypes of I/O Devices:

    - Purely input device (e.g., keyboard, mouse). - Purely output device (e.g., printer, display screen) - Both an input and output device (e.g., Touch Screens, disks)2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

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  • Input/Output ControllerI/O devices are connected to the system bus via I/O controllers.

    I/O controller acts as an interface between the system and the I/O device.

    I/O controller is used to help the processor to understand and respond to each I/O device.

    2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Input/Output ControllerI/O controller is used for two reasons: 1- To provide the necessary low-level commands and data for proper operation of the associated I/O device. 2- I/O controller contains driver hardware to send current over long cables that connect the I/O device (i.e. The amount of electrical power used to send signals on the system bus is very low, so we need vary short cable to connect I/O device).

    2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Input/Output ControllerI/O controller has three types of registers: Data Register, Status Register, and Command Register.2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

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  • Input/Output ControllerI/O controller has three types of registers: - Data Register: holds the data to be input or output. - Status Register: Determines the status of I/O device (e.g. idle, valid, busy,etc.) - Command Register: Tells the controller the operation requested by the processor. 2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Input/Output PortsProcessor and I/O interface points for exchanging data are called I/O portsTwo ways of mapping I/O portsMemory-mapped I/OI/O ports are mapped to the memory address spaceReading/writing I/O is similar to reading/writing memory Can use memory read/write instructionsMotorola 68000 and MIPS processors uses memory-mapped I/OIsolated I/OIn these systems, I/O address space is separated from the memory space.Requires special I/O instructions (like in to read data from I/O port and out to write data to I/O port in Pentium)Intel 80x86 processors support isolated I/O2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

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  • Input/Output (contd)Pentium I/O address spaceProvides 64 KB I/O address spaceCan be used for 8-, 16-, and 32-bit I/O portsCombination cannot exceed the total I/O address spacecan have 64 K 8-bit ports can have 32 K 16-bit portscan have 16 K 32-bit portsA combination of these for a total of 64 KBI/O instructions do not go through segmentation or pagingI/O address refers to the physical I/O address2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

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  • Performance: Data AlignmentBy using Data Alignment: The processor can read data items in one read cycle, and then internally assemble them.2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

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  • Performance: Data Alignment2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

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  • Performance: Data Alignment (contd)2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *UnalignedAlignedThis figure shows the impact of data alignment on the sort time of the bubble sort. These results were obtained on a 2.4-GHz Pentium 4 processor system. The unaligned sort time is approximately three times more than the aligned sort time.

    S. Dandamudi

    Chart1

    0.030.09

    0.120.38

    0.290.86

    0.511.51

    0.82.38

    AL version

    C version

    Array size

    Sort time (seconds)

    Sheet1

    ASM sort time

    SONY (P III/645MHz)

    Array sizeAlign (secs)UNalign (secs)%improvementslow factor

    50000.160.320.52

    100000.641.30.50769230772.03125

    150001.462.930.50170648462.0068493151

    200002.65.220.50191570882.0076923077

    250004.078.190.50305250312.0122850123

    PIV/2.4GHz

    50000.030.090.66666666673

    100000.120.380.68421052633.1666666667

    150000.290.860.66279069772.9655172414

    200000.511.510.66225165562.9607843137

    250000.82.380.66386554622.975

    Sheet1

    AL version

    C version

    Array size

    Sort time (seconds)

    Sheet2

    AL version

    C version

    Array size

    Sort time (seconds)

    Sheet3

    P III

    P IV

    Array size

    Speedup

  • Performance: Data Alignment (contd)Data alignmentSoft alignmentData is not required to be alignedData alignment is optionalAligned data gives better performanceUsed in Intel IA-32 processors

    Hard alignmentData must be alignedUsed in Motorola 680X0 and Intel i860 processors2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *

    S. Dandamudi

  • Performance: Data Alignment (contd)Data alignment requirements for byte addressable memories1-byte dataAlways aligned2-byte dataA 16-bit data item is aligned if the data is stored at an even address (i.e., at an address that is a multiple of 2 and the least significant bit must be 0)4-byte dataA 32-bit data item is aligned if the data is stored at an address that is a multiple of 4 and the least significant 2 bits must be 0)8-byte dataA 64-bit data item is aligned if the data is stored at an address that is a multiple of 8 and the least significant 3 bits must be 0)2005To be used with S. Dandamudi, Introduction to Assembly Language Programming, Second Edition, Springer, 2005. S. DandamudiChapter 2: Page *Last slide

    S. Dandamudi

    Clock period = instruction execution time**