Bi-directional battery management system

7/30/2019 Bi-directional battery management system

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ECE 536 - Digital Control Systems

Design of a bi-directional Battery Management System (BMS) for

renewable energy applications

Arun Kadavelugu, Ajit Narwal and Jason Houston

Abstract: Power electronic converters play a

pivotal role in harnessing power from renewable

energy sources (RES) and processing it into a

utility- friendly form. From the supply end DC-

DC converters are widely used in RES like

Distributed Generation (DG), in places where it

is required to harness and process power from

DC sources like solar cells, fuel cells or battery

banks. Energy storage media is inevitable in

renewable energy systems like distributed

generation (DG), due to the highly intermittent

nature of the RES. For such applications a bi-directional battery management system (BMS)

is used which is capable of charging the battery

bank in buck mode and discharging the same in

the boost-mode. A digital current programmed

mode control technique has been used for the

circuit implementation in real-time.

Literature: The rapid growth in industries and

depletion of fossil fuels along with increase in

green-house emissions has lead to thedevelopment of technology featuring naturally

occurring RES like wind, solar, biomass, biogas,

tidal etc. However the RES are intermittent in

nature and hence have reduced availability. In

order to over-come this shortfall the systems

employing RES must possess energy storage

media like a battery bank. The storage medium

enhances the availability of the system by

absorbing energy when generated in surplus by

the RES and supplying the same when there is a

deficit from the RES.

The usage of a storage media is inevitable for

such systems, with battery banks being the most

popular ones, due to their low cost and

simplicity. A typical distributed generation

setup would have an AC grid operating at a

specified voltage level. Therefore it is needed to

interface the battery bank with the grid. This is

done through the BMS, which is typically a bi-

directional dc-dc converter. The battery bank

will both charge and discharge through the

BMS. The proposed BMS is designed to feed

the DC bus of a front-end inverter which in turn


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would feed the AC grid at the specified voltage

level. However in order to charge the battery

bank the front-end converter will act as a

rectifier and provide a constant voltage input to

the BMS. Here the aim is to provide a fixed DC

bus voltage to the subsequent stages of the

power module which may include an inverter

stage and then a load stage.

Such a technology is critical to several

applications wherein battery banks are

employed; several of these involve hybrid

vehicles, space applications, stand-alone,

renewable source-dependent systems, electric

vehicles, inverters.

In addition to this future work involving

integrated parallel operation of RES is

proposed; these cases are frequently witnessed

where the load is grid-isolated and has to

entirely depend on varied RES for supply. This

topology yields several benefits over a single

centralized high power converter system which

include

a) Improvement in reliability due to introductionof redundancy.

b) Improvement in reliability due to even stress

distribution and enhanced fault tolerance

capability in the event of failure of a converter

module.

c) Standardization of components leading to

lesser inventories and reduction in

manufacturing cost and time.

d) The system can be easily

configured for a different

power level or input-output

requirement.

e) Allows multiphaseoperation (interleaving) of

the paralleled converters, which decreases the

input and output ripple currents and therefore

reduces the filter ratings.

In the discharge mode the BMS effectively acts

as a boost converter. In this mode the converter

has to maintain its output DC-bus voltage at a

fixed reference irrespective of load variations

and changes in battery voltage. Further thesystem has to be monitored so that the battery

bank is not allowed to deep discharge. Thus the

second objective is a tight output voltage

control, without causing any damage to the

batteries.

Once the battery bank has discharged, it needs

to be recharged. Hence, the converter inputs and

outputs reverse and the BMS effectively acts as

a buck converter. The control algorithm has tobe switched in order to charge the battery bank.

It has to be first charged in the constant current

charging mode or boost charging mode, till the

battery voltage reaches a preset voltage level.

Once this voltage level is reached the controller

must be switched in order to maintain the

battery voltage at this level, till the charging

current reduces to a small value. Any overshoots

in the charging current or voltage might damage

the battery bank. Thus the third objective is to

perform a controlled charging of the battery

bank.


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Battery

Management

System (BMS): The

battery management

system circuit is

shown in Fig. 1).

Typically battery banks have a much lower

voltage rating with respect to the DC bus

voltage and a large ampere-hour (Ah) rating.

Therefore the batteries have to be charged and

discharged in the buck and boost modes

respectively such that fewer capital is spent on

the batteries.

Fig 1) Battery Management System (BMS).

The BMS is capable of charging the battery

bank in buck mode and discharging it in boost

mode. While discharging the battery bank, the

lower switch, S2 is controlled and the upper

switch, S1 is kept continuously off, thereby only

leaving the corresponding reverse diode D1 in

circuit.

Fig 2) BMS operated in boost mode.

In order to charge the battery bank the converse

sequence is employed. The upper switch, S1 is

controlled and the current freewheels through

the reverse diode D2 of the lower switch which

is kept continuously off.

Fig 3) BMS operated in buck mode.

Plant Modeling:

a) Boost mode

b) Buck mode

This section briefly deals with theory behind

both Boost and Buck converters along with their

applications.

Fig 4) Switching converter with its controller.

The power levels encountered in high-efficiency

switching converters range from (1) less than

one watt, in dcdc converters within battery-

operated portable equipment, to (2) tens,

hundreds, or thousands of watts in power


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supplies for computers and office equipment, to

(3) kilowatts to Megawatts, in variable speed

motor drives, to (4) roughly 1000 Megawatts in

the rectifiers and inverters that interface dc

transmission lines to the ac utility power system.

A power supply system for a laptop computer,

for example, utilizes dc-dc converters. A lithium

battery powers the system, and several dcdc

converters change the battery voltage into the

voltages required by the loads. A buck converter

produces the low-voltage dc required by the

microprocessor. A boost converter increases the

battery voltage to the level needed by the disk

drive. In a distributed power system, an

intermediate dc voltage appears at the computerbackplane. Each printed circuit card contains

high-density dcdc converters that produce

locally-regulated low voltages. Commercial

applications of power electronics include off-

line power systems for computers, office and

laboratory equipment, uninterruptable ac power

supplies, and electronic ballasts for gas

discharge lighting.

Fig 5) Buck converter structure.

In a dcdc converter, like a Buck converter, the

dc input voltage is converted to a dc output

voltage having a larger or smaller magnitude,

Fig 6) Output voltage waveform, Vs of the ideal switch in

buck converter.

possibly with opposite polarity or with isolation

of the input and output ground references [1].

The switch reduces the dc component of the

voltage: the switch output voltage has a dc

component that is less than the converter dcinput voltage From Fourier analysis, we know

that the dc component of is given by its average

value or

(1)

The inductor and capacitor represent the low-pass filter to filter out the undesirable harmonics

of the switching frequency such that the output

voltage is equal to the dc component Vs. If the

corner frequency, fo, is sufficiently less than the

switching frequency, fs, then the filter

essentially passes the dc component Vs(t) [1].

Fig 7) DC conversion ratio for buck converter,

Vo/Vg=M(D).

From the figure above it can be seen that the

maximum output voltage that can be obtainedwith a buck converter would be equal to the

supply voltage.

Design of low-pass filter for converter:

Continuing the example of buck-converter the

design of inductor, L, is discussed here.


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Fig 8) Steady-state inductor voltage (Vl) waveform for

buck converter.

For design of inductor and capacitance two vital

principals need to be introduced briefly, the

principal of inductor volt-second balance and

capacitor charge-balance.

Since no filter is perfect so the output voltage ofthe converter can be stated as

(2)

This is a sum of dc component V and a small

undesired ac component vripple which is normally

considered to be less than 1% of the dc voltage

magnitude; hence the output voltage can be

approximated as V with the small ripple

neglected. Now focusing attention to fig. 5) and

8) it can be seen that when switch is in position

1 inductor voltage is given by

(3)

During the first interval, when Vl is

approximately (Vg-V) the slope of the inductorcurrent waveform is

(4)

Similarly for the subinterval 2:

(5)

Or (6)

The above equations give

Fig 9) Steady-state inductor current waveform for buck

converter.

It can be seen that

This gives

(7)

The inductor value can be chosen such that adesired current ripple is attained [1]

(8)


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Similar procedure used for a boost converter (in

Fig. 10) yields a dc conversion ratio for it such

as given in Fig. 11)

Fig 10) Boost converter.

Fig 11) DC conversion ratio for boost converter,

Vo/Vg=M(D).

An analysis for capacitor sizing is similar to that

of inductor and involves capacitor charge

balance based on the waveform given below.

Fig 12) Capacitor current DC conversion ratio for boost

converter, Vo/Vg=M(D).

From subinterval 1:

(9)

And subinterval 2 yields:

(10)

Combining the above two the following

equation is obtained [1]:

(11)

This can be used to size the filter capacitor to

obtain a given output voltage ripple peakmagnitude v.


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Controller Design and Simulation Results:

This section deals with the modeling of the plant

for both charge and discharge regimes in the

current programmed mode control scheme.

Then the design of the inner current loop usingthe Predictive Digital Current Programmed

Fig 13) Current program mode control (CPM )

Mode control techniques (or PDCPM) approach

along with stability analysis is discussed.

Finally the plant modeling and the designed

controllers are validated through simulation.

The CPM control mode involves the control of

the output voltage of a converter by the choice

of either peak, average or valley of the switch

current. The schematic diagram of this scheme

is as shown in Fig.4.3. Typically the output

voltage of the converter is compared with a

reference and the error is fed to a controller. The

controller then generates a reference current Ic.

When the switch is turned ON the switch

current increases with a slope m1. Peak current

control approach has been used in this study [2].

Hence, the switch current is continuously

compared with Ic. Once the switch current

reaches this peak reference, it is turned OFF for

the remaining switching interval during which

the inductor current falls with a slope of m2.

The converter is operated with a constant

switching frequency. Therefore the switch is

turned ON again in the beginning of the next

switching interval.

CPM being used in this work has a strong

rationale behind it. This proves instrumental

especially in case of the circuit working in buck

mode. While charging, batteries are charged

through constant current mode till the voltage

rises up to the nominal voltage of the bank after

which control is shifted to constant voltage

mode (also called float/trickle charging) which

effectively maintains the voltage of the batteries

to the final desired voltages.

A few other advantages of CPM as follows:

a) CPM has simpler control dynamics.

b) The output to control input transfer function

Vo(s)/Ic(s) can be considered tobe of first order

since the pole corresponding to the inductorcurrent is pushed to the deep left half of the s-

plane.

c) Since the plant effectively resembles a first

order plant the design of controller is much

simpler. In most of the cases a simple PI

controller will suffice.

d) CPM is instrumental in case of several

converters operating in parallel mode for pre-

determined current sharing despite parametric

variations [3].


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Current Control Law- Predictive Digital

Current Programmed Control [4]

The current programmed mode control is

basically an analog control technique involving

continuous comparison of the control currentreference with the switch current or the inductor

current. However in order to implement in

digital platforms like DSP, continuous

comparison implies a large sampling frequency.

In other words the currents have to be sampled

at very short intervals in order to mimic the

analog CPM technique. However with larger

switching frequencies this method becomes

more and more complicated due to the

requirement of faster ADCs and large signal

processing capabilities. In order to overcome

these problems the Predictive Digital Current

Programmed Mode control technique (PDCPM)

[2] has been used. In this technique, the duty

ratio for the present switching cycle is

calculated using the switch current and the

converter input and output voltages sampled at

the end of the previous switching cycle. The

duty ratio is predicted such that the error incurrent is minimized in the subsequent cycles.

Current Control Law for Boost Mode

Fig 15) Inductor current with perturbation.

From Fig. 15) it is seen that the error in the

current at the start of nth switching cycle is

sought to be corrected at the start of (n+1)th

switching cycle or at the end of the nth

switching cycle so that Ic = IL[n +1]. This is

achieved by feedback of the inductor current IL

and the input and output voltages Vin and Vo,

sensed at the beginning nth switching cycle. The

inductor current at the end of nth switching

cycle is given by

ssLL

TndmTndmnini 12 '1 ----a)

Using

Buck Boost

1m

L

vvoin

)(

L

vin

2m

L

vo L

vvino

)(

Table 1) Slopes and constants for buck and boost modes.

This gives

L

Tndnv

L

Tndnvvnini

sinsoin

LL

][][]['])[(][]1[

=

L

Tndnv

L

Tnvni

sosin

L

]['][][][

(12)

=L

Tndnv

L

Tnv

L

Tnvni

sososin

L

]['][][][][

For the control objective to be achieved the

condition IL[n +1]= Ic has to be satisfied.

][][][][])[( ndnvnvnvniiT

LooinLc

s

(13)

This gives:

][

][1])[(

][][

nv

nvnii

Tnv

Lnd

o

in

Lc

so

(14)

If the inductor current peak at the start of nth

switching cycle is greater than ic then, from the


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above d[n] equation the duty ratio is decreased

by a factor proportional to the current error i =

IL[n]Ic. When this error is reduced to zero (i.e

IL = Ic), d[n] simplifies to (1 vin)/vo, which is

the steady state duty ratio of a boost converter.

Thus any given reference current peak can be

tracked directly using this method.

Current at the end of the nth switching cycle is

given by

L

ndTnv

L

TViini

sosin

cL

])[1(][]1[

(15)

Which yields

iL

DTnv

L

Tnv

L

TnViinini

sososin

cL

][][][]1[]1[

= ))1]([][( DnvnvL

T

oin

s

= ])[][( nvnvL

T

inin

s (16)

Thus we obtain, 0]1[ ni

Thus it is proved that the perturbation in current

dies down within one switching period thereby

achieving a dead-beat operation. Hence, the

predictive peak CPM using leading edge

modulation is stable for all values of D.

Current Control Law for Buck Mode

Derivation of the control law for the buck mode

is similar to that of the boost mode. The duty

ratio for the nth switching cycle is computed

based on the sensed inductor current

iL[n], output voltage vo[n] and the input voltage

vin[n] at the beginning of the nth switching

cycle. Substituting the slopes for buck converter

from Table.1 in Eqn. a) we obtain

L

Tndnvnv

L

Tndvnini

soinso

LL

][])[][(]['][]1[

(17)

Since i [n +1]= i we have,

L

Tnvnd

L

Tndnv

L

Tnvnd

L

Tnvnii

osinsoso

Lc

][][]1[][][][]['][

=L

Tnv

L

nvTndsoins

][][][

(18)

simplifying the above equation, we obtain the

expression for the predicted value of duty ratio

for the buck mode:

][

][]][[

][]1[

nv

nvnii

Tnv

Lnd

in

o

Lc

sin

(19)

A similar procedure shown for the boost

converter case can be followed for the buck

converter control law and results in stable

operation for any D. Thus the benefit of using

the PDCPM controller can achieve the benefits

of traditional CPM control but avoid thecomplexity of high performance ADCs and also

without the subharmonic instabilities that are

inherent with traditional CPM control.

Buck Converter Controller Design

VO

CO

VREFPWM

Modulator

Current

SenseVIN

LO

HFB

+-

iOiL

QU

QL

D

VSW

ESRRO

Compensator

DCR

iC

Fig 16) Simplified Buck Converter Diagram.


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A simplified buck converter diagram is shown

in Fig 16. Based on the steady state and

switching ripple analysis developed in a

previous section the buck converter and boost

converter plant parameters are chosen as shown

in the Table 2.

Parameter Value Comment

D Converter Duty Cycle

VIN 100V Input Voltage

Fsw 20kHz Switching Frequency

Fsample 50kHz ADC Sample Rate

Lo 1mH Output Inductor

DCR 200mOhms Inductor Resistance

Current Gain 1A/A Current Sense Gain

Co 100uF Output Capacitor

ESR 1mOhm Capacitor Resistance

Ro 25Ohm Load Resistor

HFB 1V/V Voltage Sense Gain

Table 2) Buck and Boost Converter Parameters.

A mathematical model is derived to show the

benefits of current mode control versus voltage

mode control for the buck converter. Figure 16

is used to derive the DC and AC characteristics

of the buck converter plant, controller andmodulator. First the variables for the system are

defined as shown in Figure 17 and the reference

designators match Table 2 and Figure 16.

Fig 17) Define Buck Converter Parameters.

The procedure of inductor volt-second balance

and capacitor charge-balance described

previously is used to find the DC and AC

characteristics of the buck converter. The

equations are shown here:

D( ) Vin DCR IL Vo 1 D( ) DCR IL Vo VL 0 (20)

D( ) ILVoRo

1 D( ) ILVoRo

IC 0

(21)

These equations are used to derive vo/d for the

duty cycle to output voltage transfer function

shown below which is the plant of the voltage

mode buck converter

vo

d

V

in

ESR1

s Co

ESR 1

s Co DCR s Lo

(22)

ESR is the resistance of the capacitor; DCR is

the resistance of the inductor. To demonstrate

the control challenge using voltage mode

control a simple PWM modulator is used with a

sawtooth ramp of 1V. This is used to derive the

open loop system gain to the output voltage

from the duty cycle control signal with the

modulator gain applied. The open loop gain and

phase margin are shown in Figure 18.

Fig 18) Open Loop Buck Converter with VM Control.


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Without compensation the loop bandwidth is

~5kHz and the phase margin is 7deg. This

system is very nearly unstable due to the -

180deg phase shift due to the underdamped LC

filter. A PID controller would be needed to

boost the phase sufficiently to stabilize the loop.

To investigate the benefit of current mode

control, the transfer functions are derived

assuming a simple PI controller. The current

mode plant model is first order as described

previously and the inductor pole is essentially

removed from the transfer function. The

inductor current to output voltage transfer

function is shown below.

vo

iL

ESR1

Co s

(23)

The PI parameters can be designed based on the

plant model transfer function and analysis of the

bode plot. For example the figure below shows

the open loop gain of the plant model and

modulator of the current mode buck converter.

The red dot marks the loop bandwidth where the

gain equals one. And the blue dot marks the

phase margin at that frequency.

Since the final system is digital the s-domain

results should be modified to show the phase

shift of a digital system. This can be achieved

by adding the transfer function of the ZOH and

the phase shift from the sampling nature of the

peak current mode feedback loop.

The resulting system bode plot is shown below.The proportional gain of the compensator, Kp

can be increased to increase the loop bandwidth

until the phase margin is reduced to some

minimal value. For this design, the gain is

increased until the phase margin drops to 60deg.

Therefore analytical expressions for the Kp and

Ki of the analog compensator

Hs Kp

Ki

s

(24)

Can be determined as shown in Equations (25).

221.0

'

1

)(

PBWI

BW

BWP

I

P

I

IPC

KfK

f

fK

K

s

K

K

s

s

KKsH

(25)


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Choosing some parameters for a PI controller,

the open loop gain and phase margin plots are

shown in Figure 19. The gain curve is shown to

have a -20dB/dec slope over a very large

frequency range demonstrating the single pole

response characteristic of current mode control.

Therefore a simple PI controller is sufficient for

the controller.

Fig 19) Open Loop Buck Converter with CPM Control.

Based on the bode plot analysis the continuous

controller coefficients are Kp=2 and Ki=1000.

The integrator is needed to minimize steadystate error and the proportional gain is needed to

add a zero for stability and to improve transient

response.

The bilinear transformation is used to derive the

coefficients for the equivalent discrete filter

coefficients for the digital controller. The

digital controller equation is:

Kp

Ki Tsample

2

z

Ki Tsample

2 Kp

z 1 (26)

And Kp=2.01 and Ki=-1.99. As shown in

Figure 19, this controller yields open loop

bandwidth of ~650Hz and phase margin of

~63deg.

Buck Converter Simulation Results

To simulate the regulation and voltage and

current dynamics of the buck converter design a

continuous analog switching model is built in

the SIMPLIS simulation tool and the digital

switching model is built in Matlab. The

schematics are shown in Figure 20 and 21.


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Fig 20) SIMPLIS Schematic of Analog Buck Converter Model.

Fig 21) Matlab Schematic of Digital Buck Converter Model with

PDCPM Control.


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The buck converter of Figure 21 output voltage

step response is shown in Figure 22. The top

waveform is the inductor current and the bottom

waveform is the output voltage stepping from

0V to 50V. There is very little overshot and the

response is stable. Figure 23 shows the step

response from 50V to 70V again showing stable

response with little overshoot. Also, note the

system does not exhibit subharmonic oscillation

even though the duty cycle is >> 50% exhibiting

the benefit of PDCPM control.

Fig 22) Buck converter step response from 0V to 50V.

Fig 23) Buck converter step response from 50V to 70V.

Figure 24 shows the load transient response and

single cycle response of PDCPM. The load step

applied is 2A and the output voltage response is

stable and well damped. Figure 25 shows a

zoom in of the transient response showing

inductor current very nearly single-cycle

response.

Fig 24) Buck converter load step response for 2A step.

Fig 25) Buck converter load step response for 2A step.

For comparison the analog controller is

simulated in SIMPLIS tool. Figure 26 shows

the open loop Bode plot for the buck converterwith a similar PI controller.


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Fig 26) Buck converter bode plot for analog controller.

Boost Converter Controller Design

VO

CO

VREFPWM

Modulator

VIN

LO

HFB

+-

iOiL

QU

QLD ESR

RO

Compensator

DCR

iC

Current

Sense

DVo

Fig 27) Simplified Boost Converter Diagram.

A similar design procedure is followed for the

boost converter. A simplified boost converter

diagram is shown in Fig 27. The boost

converter parameters were shown in Table 2

except the VIN will be lower than the output

voltage.

A mathematical model is derived to show the

benefits of current mode control versus voltage

mode control for the boost converter. Figure 28

is used to derive the DC and AC characteristics

of the boost converter plant, controller and

modulator. First the variables for the system are

defined as shown in Figure 28.

Fig 28) Define Boost Converter Parameters.

The procedure of inductor volt-second balance

and capacitor charge-balance described

previously is used to find the DC and AC

characteristics of the boost converter. The

equations are shown here:

D( ) Vin DCR IL 1 D( ) Vin DCR IL Vo VL(26)

D( )Vo

Ro

1 D( ) IL

Vo

Ro

Ic

(27)

These equations are used to derive vo/d for the

duty cycle to output voltage transfer functionshown below which is the plant for the boost

converter.

vo

d

Vo

Vo DC R Lo s Ro D 1( )

D

1

Ro

Co s

Co ESR s 1

DC R Lo s

D 1 1

(28)

To demonstrate the control challenge using voltagemode control a simple PWM modulator is used with

a sawtooth ramp of 1V. This is used to derive the

open loop system gain to the output voltage from

the duty cycle control signal with the modulator

gain applied. The open loop gain and phase margin

are shown in Figure 29.


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Fig 29) Open Loop Boost Converter with VM Control.

Without compensation the loop bandwidth is

~5kHz and the phase margin is -13deg. This

system is unstable due to the -180 deg phase

shift of the double pole and also the right-half

plane zero. A complex controller would be

needed to boost the phase sufficiently to

stabilize the loop.

To investigate the benefit of current mode

control, the transfer functions are derived

assuming a simple PI controller. The current

mode plant model is first order as described

previously and the inductor pole is essentially

removed from the transfer function. The

inductor current to output voltage transfer

function is shown below. This time the

derivation includes capacitor ESR and output

load resistor for better accuracy.

v

oiL

ESR1

s C

o

Ro

ESR1

s Co Ro

(29)

Choosing some parameters for a PI controller,

the open loop gain and phase margin plots are

shown in Figure 30. The gain curve is shown to

have a -20dB/dec slope over a very large

frequency range demonstrating the single pole

response characteristic of current mode control.

Therefore a simple PI controller is sufficient for

the controller.

Fig 30) Open Loop Boost Converter with CPM Control.

The controller is designed using the bode plots.

The proportional gain can be varied until the

phase margin drops to ~60deg which is a good

tradeoff between stability and transient

response. The analog controller equation is

shown:

Hs KpKi

s

(30)

Based on the bode plot analysis the continuous

controller coefficients are Kp=1 and Ki=1000.

The integrator is needed to minimize steady

state error and the proportional gain is needed to

add a zero for stability and to improve transient

response.

The bilinear transformation is used to derive thecoefficients for the equivalent discrete filter

coefficients for the digital controller. The

digital controller equation is:


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Kp

Ki Tsample

2

z

Ki Tsample

2 Kp

z 1 (31)

And Kp=1.01 and Ki=-0.99. As shown in

Figure 19, this controller yields open loop

bandwidth of ~470Hz and phase margin of

~68deg.

Boost Converter Simulation Results

To simulate the regulation and voltage and

current dynamics of the boost converter design a

continuous analog switching model is built in

the SIMPLIS simulation tool and the digital

switching model is built in Matlab. Theschematics are shown in Figure 31 and 32.


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Fig 31) SIMPLIS schematic of Analog Boost Converter.

Fig 32) Matlab schematic of Digital Boost Converter.


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The boost converter of Figure 32 output voltage

step response is shown in Figure 33. The top

waveform is the inductor current and the bottom

waveform is the output voltage stepping from

0V to100V. There is a small amount of

overshoot and the response is stable. Figure 34

shows the step response from 100V to 120V

again showing stable response with little

overshoot. Also, note the system does limit the

peak current so the transition to 120V is not as

fast. This is another benefit of peak current

mode control; it is easy to limit peak current.

Fig 33) Boost converter step response from 0V to 100V.

Fig 34) Boost converter step response from 100V to 120V.

Figure 35 shows the load transient response and

single cycle response of PDCPM. The load step

applied is 2A and the output voltage response is

stable and well damped. Figure 36 shows a

zoom in of the transient response.

Fig 35) Boost converter load step response for 2A step.

Fig 36) Boost converter load step response for 2A step.


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20

Experimental Setup and Results

Fig. 37) shows the experimental setup of the bi-

directional buck and boost converter with a 32-

bit fixed point DSP (TMS320F2812) for digital

control implementation. The inductor,capacitors and the load bank can be seen in the

figure.

Fig 37: Experimental setup of the bi-directional buck/boost converter

The open loop results of the bi-directional

converter running in buck mode under open-

loop condition are given in Fig 38. The input

voltage is 100 V and a duty cycle of 0.25 is

chosen. The corresponding output voltage,

inductor current and PWM pulse for theMOSFET are seen in the figure. It can be seen

that the output is slightly lower than 25% due to

the drop across the diode and the inductor.

Fig 38: Open loop result in the buck mode

(Ch1: Input voltage, Ch2: Output voltage, Ch3:

PWM and Ch4: Inductor current)

The open loop results of the bi-directional

converter running in boost mode under open-

loop condition are given in Fig 39 The input

voltage of 25 V is given a duty cycle of 75%.

The corresponding output voltage, PWM pulse

and the inductor current is shown in the figure.

It can be seen that the output is considerabledifferent from ideally expected value (of 100

V). This is due to drop across the diode and

inductance as mentioned for buck converter. But

as the current value is much higher here, the

drop is also significantly higher, making the

values move farther from the ideal.


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Fig 39: Open loop result in the boost mode

(Ch1: Input voltage, Ch2: Output voltage, Ch3:

PWM and Ch4: Inductor current)

Issue in closed loop implementation:

A 32-bit fixed point DSP processor has been

used for the control implementation. While

writing the assembly code, 12.20 format has

been chosen which allows flexibility in

representing integer values up to + 2048 from

2048, while maintaining good accuracy of

fractional part representation with 20 bits.

Based on the discussion on control

implementation in the earlier sections, the plant

parameters (Vin, Vo and iL) are sampled for the

control system only once in a switching period.

So, proper sampling of these parameters has to

be done using an ADC and fed to the controller.

But there has been an issue in making the ADC

work. The CCS compiler as such was not

showing any error but it is possible that the

sequence of initialization is faulty. However,

when the code was executed assuming certain

values for Vin, Vo and iL(ref) the duty cycle

prediction for a given current, iL, was correct. It

is matching with the analytical expressions

shown in the previous sections.

The DSP code for the predictive current

algorithm for the boost mode is shown in the

appendix.

References:

[1] Robert W. Erickson and Dragan Maksimovic,

Fundamentals of Power Electronics, Kluwer academic

publishers, 2004, 2nd edition.

[2] J. Chen, A. Prodic, R. Erickson and D. Maksimovic,

Predictive Digital Current Programmed Control , IEEE

Trans. Power Electron., vol. 18, no. 1, Jan. 2003, pp. 411-419.

[3] V.J.Thottuvelil and G.C.Verghese, "Analysis and

control design of paralleled DC/DC converters with

current sharing," Power Electronics, IEEE Transactions

on , vol.13, no.4, pp.635-644, Jul 1998.

[4] R. Mirzaei and V. Ramanarayanan, Digital Deadbeat

Current Control Method for DC-DC Converters, in Proc

NPEC conference Dec. 2007.


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22

AppendixDSP Code

****** Battery Management discharge emulation - Current loop ******

.sect "vectors2"

int2_4: .long isr_timer1

******************************************************************

; BEGIN DATA INITIALISATION

******************************************************************

.data

uk .long 0x000C7FCE ; value of angular freq w, rad/sec. corresponding to 50 Hz.

uk_1 .long 0x00000000

KI .long 0x01000000

KiT .long 0x00000347 ; KiT = KI * T/2 where Ki=1 & T = 100uS

y2k .long 0x00000000

y2k_1 .long 0x00000000

CONV .long 0x00014000

CONV1 .long 0x000015D8

ZERO .long 0x00000000

ONE1220 .long 0x00100000

ADC1 .long 0x00000000

ADC .word 0x0000

flag1 .word 0x0000

shift4 .word 0x0004

csgainpv .long 0x00253594 ; 2.33 (=1/0.43) in 12.20 format

vsgbm1 .long 0x02FC0000 ; 47.75 in 12.20 format

vsgbm2 .long 0x02F26666 ; 47.15 in 12.20 format

Iref_PV .long 0x00200000 ; 1 A in 12.20

Vin_PV .long 0x06400000 ; 3.74 in 8.24 format (170 V)

Vout_PV .long 0x06400000 ; 6.6 in 8.24 format (300 V)

Vinout .long 0x00000000 ; to store 1-(Vin/Vout)

VoutTs .long 0x00000000 ; to store Vout*Ts

iL1_PV .long 0x00100000 ; 1.5 in 8.24 (1.5*0.784)

iL2_PV .long 0x0012D0E5


23/28


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******************************************************************

; SET-UP CLOCK

******************************************************************

MOVL XAR1,#PCLKCR; Peripheral Clock Control Register (address: 0x00701C)

MOV *XAR1,#0003H ; Enabling highspeed clock(HSPCLK) WITH IN EV-A peripheral and eCAN

MOVL XAR1,#PLLCR; PLL Control Register

MOV *XAR1,#000AH; CLKIN or SYSCLKOUT = OSCCLK*10/2

MOVL XAR1,#HISPCP; High-Speed Peripheral Clock(HSPCLK) Prescaler Register for HSPCLK clock

MOV *XAR1,#0000H ; HSPCLK = SYSCLKOUT/1

******************************************************************

; CONFIGURING GPIO PINS ...

******************************************************************

Removed due to space constraint

*****************************************************************

; ENABLING INTERRUPTS

*****************************************************************


******************************************************************************************

; SETTING TIMER REGISTERS

******************************************************************************************


************************************************************************

; START OF THE PROGRAM

************************************************************************

start:

MOV DP,#flag1

MOV @flag1,#0000H

************************************************************************

; Sensing iL, Vin and Vout using ADCs (12.20 format)


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************************************************************************

; LCR _sample_inputs

; Sensing iL and converting it into 12.20 format (multiplied with sensor gain also)

; MOVW DP,#iL1_PV

; MOVL @iL1_PV,P ; iL1_PV, Vin_PV, Vout_PV has the current value

; MOVL ACC,@P

; Limiting the startup inductor curret.

; MOVW DP,#iL1_lim

; CMP AH,@iL1_lim

; B LOOP1,LEQ

; MOVL XAR1,#T1CMPR

; MOV *XAR1,#03A98H

; B here1,UNC

LOOP1:

; Calculation of duty ratio for the boost converter1

MOVW DP,#Vin_PV ; Vin_PV/Vout_PV in 12.20 format

MOVL XAR1,@Vin_PV

MOVW DP,#Num32

MOVL @Num32,XAR1

MOVW DP,#Vout_PV

MOVL XAR1,@Vout_PV

MOVW DP,#Den32

MOVL @Den32,XAR1

LC FracDiv32 ; Calling FracDiv32 Module (output in 12.20 format)

MOVW DP,#Quot32

MOVL XAR2,@Quot32 ; Vin_PV/Vout_PV in XAR2 (12.20 format)

MOVW DP,#ONE1220

MOVL ACC,@ONE1220

SUBL ACC,@XAR2

MOVW DP,#Vinout

MOVL @Vinout,ACC ; Vinout is stored with 1-(Vin_PV/Vout_PV)

MOVW DP,#Vout_PV ; Vout_PV*Ts_PV in 12.20 format

MOVL XT,@Vout_PV ; 12.20*12.20 multiplication

SPM 0


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MOVW DP,#Ts_PV

IMPYL P,XT,@Ts_PV ; lower 32-bit of 32*32 product. Note this instruction uses SPM also

QMPYL ACC,XT,@Ts_PV ; higher 32-bit of 32*32 product. No SPM is considered by this instruction

ASR64 ACC:P,#16

ASR64 ACC:P,#4 ; Final product output in 12.20 format in P register

MOVW DP,#VoutTs

MOVL @VoutTs,P ; Vout_PV*Ts_PV in VoutTs (12.20 format)

MOVW DP,#L1_PV ; L1_PV/Vout_PV*Ts_PV in 12.20 format

MOVL XAR1,@L1_PV

MOVW DP,#Num32

MOVL @Num32,XAR1

MOVW DP,#VoutTs ; VoutTs contains Vout_PV*Ts_PV

MOVL ACC,@VoutTs

MOVW DP,#Den32

MOVL @Den32,ACC

LC FracDiv32 ; Calling FracDiv32 Module (output in 12.20 format)

MOVW DP,#Quot32

MOVL XAR4,@Quot32 ; L1_PV/Vout_PV*Ts_PV in XAR4/ Quot32 (12.20 format)

MOVW DP,#new1 ; new

MOVL @new1,XAR4

MOVW DP,#Iref_PV

MOVL ACC,@Iref_PV

MOVW DP,#iL1_PV

SUBL ACC,@iL1_PV ; (Iref_PV - iL1_PV) in ACC

MOVW DP,#new2 ; new

MOVL @new2,ACC

MOVL XT,@ACC ; ACC contains (Iref_PV - iL1_PV)

SPM 0

MOVW DP,#Quot32 ; Quot32 contains L1_PV/Vout_PV*Ts_PV

IMPYL P,XT,@Quot32 ; lower 32-bit of 32*32 product. Note this instruction uses SPM also

QMPYL ACC,XT,@Quot32 ; higher 32-bit of 32*32 product. No SPM is considered by this instruction

ASR64 ACC:P,#16


MOVL @ACC,P ; ACC contains (L1_PV/Vout_PV*Ts_PV)*(Iref_PV - iL1_PV) (12.20 format)


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MOVW DP,#Vinout ; 1-(Vin_PV/Vout_PV) in Vinout (12.20 format)

ADDL ACC,@Vinout ; Now ACC has "duty ratio" in 12.20 format. convert it into apt number for TCMP

MOVL XT,@ACC ; 12.20*12.20 multiplication of 00003A98 & 12.20 version of duty ratio

SPM 0

MOVW DP,#TMR_PV

IMPYL P,XT,@TMR_PV ; lower 32-bit of 32*32 product. Note this instruction uses SPM also

QMPYL ACC,XT,@TMR_PV ; higher 32-bit of 32*32 product. No SPM is considered by this instruction

ASR64 ACC:P,#16


MOV AL,@PL

MOVW DP,#d_limit

CMP AL,@d_limit ; duty ratio limiter - 0.7 max

B dlim1,LOS

MOVW DP,#d_limit

MOV AL,@d_limit

dlim1: MOVW DP,#temp_pv1

MOV @temp_pv1,AL ; PL contains binary number of dutyratio1 to compare with timer value

SETC SXM

MOV ACC,#3A98H


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isr_timer1:

MOV DP,#flag1

MOV @flag1,#01FFH

OR IER,#0002H ; Enabling global interrupt

MOVL XAR1,#EVAIFRA

MOV *XAR1,#0000000010000000B ; GP Timer1 period interrupt flag is reset

MOVL XAR1,#PIEACK

MOV *XAR1,#0002H

CLRC INTM

IRET

.include "FracDiv32.asm" ; Note that the output is in 12.20 format

.include "init.asm"

.include "adc.asm"

; .include "ivt.asm"

.include "pwm_init.asm"

; .include "variable.asm"

; .include "vectors.asm"

.include "reg_2812.h"

; .include "var.inc"

Note: The subroutines have not been included in the above code.

Documents

Bi-directional battery management system