Bi-directional dc-dc Converter - energy.gov · Inductor Current of Boost Converter 3 SABER Schematic Operating Modes • Motoring mode, where the power flows from the 100 – 180

2008 DOE MeritReview Guidelines

Bi-directional dc-dc ConverterIncluding Vehicle System Study to determine Optimum Battery and DC Link Voltages

Dr. Abas GoodarziEmail: [email protected]

Phone: 310-375-7555Organization: US Hybrid Corporation

Dr. Sudip Mazumder University Of Illinois, Chicago

February 28, 2008Project Duration: FY2007 to FY2010

This presentation does not contain any proprietary or confidential information

mailto:[email protected]

2008 DOE MeritReview GuidelinesThe Challenge

• PHEV requires high power density battery/energy storage for hybrid operation and high energy density battery for EV mode range.

• Battery Technologies to maximize power density and energy density simultaneously, are not commercially feasible.

• The use of bi-directional dc-dc converter allow use of multiple energy storage, and the flexible dc-link voltages can enhance the system efficiency and reduce component sizing.

• Design a bi-directional dc-dc converter and fabricate a 5kW POC unit to demonstrate the following;

– High inlet and ambient temperatures ( > 105 °C)

– High efficiency ( > 90 %)

– High power density (20 – 50 W/in3)

– Low cost ( ≤ $75 /kW)

2008 DOE MeritReview GuidelinesPurpose of Work for FY08

1. Vehicle modeling, simulation, and operation voltages optimization.

2. DC-DC Power converter and control modeling.

3. Silicon Carbide device specifications.

4. Silicon Carbide and MOSFET comparative performance evaluation.

Key Technical Challenges• High inlet and ambient temperatures ( > 105 °C)• High efficiency ( Target > 90 %), Estimated 95% (@ rated power)• High power density (20 – 50 W/in3), Estimated > 16 W/in3• Cost: ≤ $ 75 /kW for 75,000 quantities

2008 DOE MeritReview GuidelinesDC Link Voltage Optimization

Inverter and

Motor Drive

Battery Vehicle

Time

SOC

Inverter and Motor

DriveBattery Vehicle

Time

SOC DC-DC

Fig 1. Base Line PHEV, charge depletion Operation Mode.

Fig 2. Single Battery with DC-DC converter and DC link Voltage Regulation

2008 DOE MeritReview GuidelinesDC Link Voltage Optimization Cont.

Vehicle Data

Drive Cycle

VehiclePower

Required

Inverter and

Motor Drive Model

High Power Battery_HP

30 Sec Power

DC-DC

High EnergyBattery_HE10-40 miles

LV Variable

HV Variable

Time

SOC

Time

SOC

Fig 3. Dual Energy Storage System (one optimized for power density and one optimized for energy density) with DC-DC

converter and DC link Voltage Regulation

Determine Vehicle Power for Drive cycle

Determine Drive line losses for Drive cycle

Battery_HP HV=250V ..500Vdc

DC-DC

HV=150V .300VdcBattery_HE

Fig 4. Vehicle System Modeling Diagram

2008 DOE MeritReview GuidelinesDC Link Voltage Optimization Cont.

$/kW of Power Density

$/kWhr Energy D

ensity

HEV B

attery

EV Battery

DC-DC

Fig 5. Typical Battery cost $/kWhr vs. $/kW.

Operating SOC (∆)Life cycle cost $/EV-PH

EV/Miles

0% 100%

Fig 6. Battery cycle life cost $/ EV-PHEV/mile.


Bat

tery

(100

–20

0 V

)

Module (2)

Module (1)

S1

S2

S1

S2

Module (3)

S3

S3

C1 C2

Prop

ulsi

on B

atte

ry

or U

ltrac

apac

itor

(200

–40

0 V

)

Load

Bidirectional DC-DC Converter

Inverter

PowerStage

Controller

S3

i1

Vin Vout

Gate Driverand Protection

S1



S2

LogicSupply Brick

Bat

tery

(100

–20

0 V

)

Module (2)

Module (1)

S1

S2

S1

S2

Module (3)

S3

S3

C1 C2

Prop

ulsi

on B

atte

ry

or U

ltrac

apac

itor

(200

–40

0 V

)

Load

Bidirectional DC-DC Converter

Inverter

PowerStage

Controller

S3

i1

Vin Vout


S1



S2

LogicSupply Brick

All-SiC Dc-Dc Bidirectional Converter

PlanarInductor

SiCVJFET

L = 100 μH Imax = 22 ATmax = 140 C

Vrated = 600 VIrated = 10 ARdson = 0.4 Ω (@ 200 C)Coss = 350 pF (@ 200 C)

Mixed-signal

Bandwidth ≥ 20 kHz

2008 DOE MeritReview GuidelinesSiC VJFET Advantages

Comparison of the on resistances and output capacitances of SiC VJFET with state-of-the-art MOSFETs.

On resistance (ohm) Output Capacitance (pF)Device Type Ratings 25 oC 150 oC 200 oC 25 oC 150 oC 200 oCSiC VJFET

(SiCED) 600 V, 10 A 0.42 0.74 0.8 ~ 350 ~ 350 ~ 350

SuperFET FCPF11N60 600 V, 11 A 0.38 0.83 N/A ~ 700 ~ 700 N/A

CoolMOS SPB11N60C3 600 V, 11 A 0.38 0.95 N/A ~ 550 ~ 550 N/A

CoolMOS 20N60S5 600 V, 20 A 0.2 0.49 N/A ~ 900 ~ 900 N/A

• For the same device rating, SiC VJFET provides superior on resistance and output capacitance as compared to the Si field-effect devices. That implies lower conduction as well as switching losses.• For a Si device with higher current rating, lower on resistance comes at the price of higher output capacitance. This implies, lower conduction loss, but higher switching losses. The latter can limit maximum switching frequency and power density.


Optimal Number of Converter Modules and Switches per Module

NswNmodule

Effic

ienc

y

NswNmodule

Effic

ienc

y

NswNmodule

Cos

t

NswNmodule

Cos

t

• Selection based on estimated efficiency and cost

– SiC VJFET operating at 175 C– Planar magnetics operating at 140 C

• Optimized values– Number of converter modules: 3– Number of switches per module: 2 x 4

Temperature (°C)

On-

stat

e R

esis

tanc

e(mΩ

)

300

400

500

600

700

800

0 50 100 150 200Temperature (°C)

On-

stat

e R

esis

tanc

e(mΩ

)

300

400

500

600

700

800

0 50 100 150 200

Variations of SiC VJFET On-

resistance with Temperature

0

100

200

300

400

500

0 50 100 150 200 250

Temperature (°C)

Out

put C

apac

itanc

e(pF

)

0

100

200

300

400

500

0 50 100 150 200 250

Temperature (°C)

Out

put C

apac

itanc

e(pF

)Variations of SiC VJFET Device

Capacitance with Temperature

2008 DOE MeritReview GuidelinesGate Driver and Protection

0 V

-24 V

Gate Drive Signal for SiC VJFET

Dead TimeS1 S1

Ids

ENOver-current

Region

Ids

ENOver-current

Region

Protection CircuitsSaber Simulation Results

Vgs

Vds

Vin

325 V

5 kV

< 600 V325 V

Vgs

Vds

Vin

325 V

5 kV

< 600 V325 V

Overcurrent Protection

Overvoltage Protection

- 25 V

0V

MAX 5060

Average Current-mode

Controller

Issues: • SiC are normally-on devices and require ≤ - 25 V to turn off• Self-contained ASICs are not available leading to discrete design of protection circuits

RS

Gate Driver

IXDD430

GND

OUT

Rf

Cf

Vref

RG

+

-

LM339

RG1

PGND

PGND

PGND

SRFLIP -FLOP

SQ

Q’

VCC

EN

IN

MonostableMultivibrator

R

PWM

Q

Q

VP+

JFET

CG

RS

Gate Driver

IXDD430

GND

OUT

Rf

Cf

Vref

RG

+

-

LM339

RG1

PGND

PGND

PGND

SRFLIP -FLOP

SQ

Q’

VCC

EN

IN

MonostableMultivibrator

R

PWM

Q

Q

VP+

JFET

CG

SiC VJFETOver-currentProtection

Gate driveover -currentprotection

SiC VJFETover -voltage

protection

Gate driveover -voltage

protection

T1

SiCVJFET

T2

D1

D2

Rg

Built-in UV lockout

2008 DOE MeritReview GuidelinesPreliminary, Experimental Gate-drive Results

11

Vds (50 V/div)

Ids (2 A/div)

Vgs (20 V/div)

Vds (50 V/div)

Ids (2 A/div)

Vgs (20 V/div)

0

40

80

120

160

0 1 2 3 4 5

Rise TimeFall Time

Rg (Ohms)

Tim

e (n

s)

T = 150 °C0

40

80

120

160

0 1 2 3 4 5

Rise TimeFall Time

Rg (Ohms)

Tim

e (n

s)

T = 150 °C

0

50

100

150

200

250

300

0 200 400 600 800 1000

Rise TimeFall Time

Tim

e (n

s)

Dead time (ns)

T = 150 °C0

50

100

150

200

250

300

0 200 400 600 800 1000

Rise TimeFall Time

Tim

e (n

s)

Dead time (ns)

T = 150 °C

Parametric: Rise and Fall times with variations in Gate Resistance

Parametric: Rise and Fall times with variations in Dead Time

Time Domain

Vds

Ids

Vgs

2008 DOE MeritReview GuidelinesPlanar Inductors Design

• Core: Ferrite LP3A• Number of turns: 18• Loss increases by 1.2 W/C

0

2

4

6

8

10

12

14

0 5 10 15 20 25Average Current (A)

Pow

er L

oss (

W)

Variation of Flux Density with Temperature

71.0

0

82.00

1

2

Variation of Power Losswith Load

Operating Range

Rated operatingpoint@ 105 C

2008 DOE MeritReview GuidelinesCAD Layout Design

SiC VJFETSwitchesSiC VJFET

Gate Driversand Accessories

PlanarInductors

ControllerBoard

VoltageSensorOutput

ConnectorInput

Connector

Main Logic Power Brick

OutputCapacitors

InputCapacitors

SiC VJFETSwitchesSiC VJFET

Gate Driversand Accessories

PlanarInductors

ControllerBoard

VoltageSensorOutput

ConnectorInput

Connector


OutputCapacitors

InputCapacitors

PlanarInductor

PlanarInductor

PlanarInductor

VoltageSensor

VoltageSensor

ControllerBoard

OutputCapacitors

OutputConnector

InputConnector

InputCapacitors


CurrentSensors

PlanarInductor

PlanarInductor

PlanarInductor

VoltageSensor

VoltageSensor

ControllerBoard

OutputCapacitors

OutputConnector

InputConnector

InputCapacitors


CurrentSensors

2008 DOE MeritReview GuidelinesControl System

DC Bus Voltage

Load Transients Load TransientsLoad Transients

Ultracapacitor Current

Sum of the Boost Inductor Currents

DC Bus Voltage

Load Transients Load TransientsLoad Transients

Ultracapacitor Current

Sum of the Boost Inductor Currents

Inductor Current of Boost Converter 1






SABER Schematic

Operating Modes• Motoring mode, where the power flows from the 100

– 180 V energy-source battery to the dc bus• Generating mode, where the power transfer is in the

opposite direction• Charging mode, where the plug-in energy is

transferred most likely from the dc bus to the 100 –180 V battery energy source.

Simulation WaveformsTransient

Steady State

2008 DOE MeritReview GuidelinesEfficiency Variations (Design Estimations)

15

90

92

94

96

98

100

100 120 140 160 180 200Input Voltage (V)

Effic

ienc

y (%

)

90

92

94

96

98

100

100 120 140 160 180 200Input Voltage (V)

Effic

ienc

y (%

)

Variation with Input Voltage

80

84

88

92

96

100

1000 2000 3000 4000 5000Load Power (W)

Effic

ienc

y (%

)80

84

88

92

96

100

1000 2000 3000 4000 5000Load Power (W)

Effic

ienc

y (%

)80

84

88

92

96

100

1000 2000 3000 4000 5000Load Power (W)

Effic

ienc

y (%

)80

84

88

92

96

100

1000 2000 3000 4000 5000Load Power (W)

Effic

ienc

y (%

)

Projected efficiency withDynamic Power Management

Variation with Load


16

Phase I Activities for 2008

• Collect data from battery and other sub-system supplier

• Complete the dc voltage optimization modeling

•Characterize the power devices and magnetic components.

• Fabricate and Characterize the Sic converter

• Fabricate and characterize the Si converter

• Design the integrated magnetic, sensor and Power Silicon.

2008 DOE MeritReview GuidelinesSummary

DC voltage optimizations.– Vehicle Configurations defined– Motor and inverter Supplier Cost and loss model data is needed.– Battery Supplier Cost and loss model data is needed.– Drive Cycle for the study is US06

Sic Converter.– Magnetic and power stage designed– Gate Driver designed and molded.– Converter System modeling.

Si Converter.– Magnetic and power stage design on-going.– Integrated Magnetic, Silicon and Sensors design ongoing.

Documents

Bi-directional dc-dc Converter - energy.gov · Inductor Current of Boost Converter 3 SABER Schematic Operating Modes • Motoring mode, where the power flows from the 100 – 180