Embed Size (px)
Citation preview
Boundary Scan .1
Boundary Scan! Objectives! History! Family of 1149! Architecture! Bus Protocol! Boundary scan cell! TAP controller! Instruction set! Boundary Scan Description Language
Boundary Scan .2
! Standards for board level testing; can be used to test
1. chips 2. chip interconnections 3. modules 4. module interconnections 5. subsystems 6. systems 7. Multi-Chip Modules
Objectives
Boundary Scan .3
History! 1985: Joint European Test Action Group (JETAG, Philips)! 1986
VHSIC Element-Test & Maintenance (ETM) bus standard (IBM etal.)
VHSIC Test & Maintenance (TM) Bus structure (IBM et al.)! 1988: Joint Test Action Group (JTAG) proposed Boundary Scan
Standard! 1990
Boundary Scan approved as IEEE Std. 1149.1-1990 Boundary Scan Description Language (BSDL) proposed by HP
! 1993: 1149.1a-1993 approved to replace 1149.1-1990! 1994: 1149.1b BSDL approved! 1995: 1149.5 approved! 1999: 1149.4 approved
Boundary Scan .4
Overview of P1149 FamilyNumber Title Status
1149.1 Testing of digital chips and interconnections between chips
Std. 1149.1-1990 Std. 1149.1a-1993 Std. 1149.1b-1994 (BSDL)
1149.2 Extended Digital Serial Interface
Near completion
1149.3 Direct Access Testability interface
Discontinue
1149.4 Mixed-Signal Test Bus Std. 1149.4-1999 1149.5 Standard Module Test and
Maintenance (MTM) Bus Protocal
Std. 1149.5-1995
1149 Unification Not yet started
Boundary Scan .5
1149.1-1990, 1149.1a-1993
! Testing of chips and interconnections on board! For digital circuits! Most successful among 1149 family! Widely used in industry, e.g., in advanced CPU,
HDTV, satellite system, etc.
Boundary Scan .6
Basic Chip Architecture for 1149.1
U
I/O Pins I/O Pins
TDI
TRST*
M
X
Miscellaneous Registers
Bypass Register
Instruction Register
TAPControllerTMS
TDO
TCK
Boundary Scan Cell
Boundary Scan Path
Internal Logic
Sin Sout
Boundary Scan .7
Boundary Scan Circuitry in a Chip
TAP
IR decode
Instruction Register
Design-Spec. Reg.
BS Register
Bypass Reg.(1 bit)
Device-ID Reg.
TAPC
MUXTDO
TDI
TMSTCK
0
1
1D
C1 EN
SelectTCK Enable
ClockDRShiftDRUpdateDR
ClockIRShiftIRUpdateIR
Reset*
TRST*
Data Registers
3
3
Boundary Scan .8
Hardware Components of 1149.1! TAP (Test Access Port) :
TMS, TCK, TDI, TDO, TRST* (optional)! TAP Controller :
A finite state machine with 16 states Input : TCK, TMS Output : 9 or 10 signals included ClockDR, UpdateDR, ShiftDR, ClockIR, UpdateIR, ShiftIR, Select, Enable, TCK and the optional TRST*.
! IR (Instruction Register)! TDR (Test Data Registers) :
Mandatory: Boundary scan register and Bypass register Optional: Device-ID register, Design-Specific registers, etc.
Boundary Scan .9
! Signals TDI: Test Data In TDO: Test Data Out TMS: Test Mode Selection TCK: Test Clock TRST* (optional): Test Reset
! Basic operations Instruction sent (serially) over TDI into instruction register. Selected test circuitry configured to respond to instruction. Test instruction executed. Test results shifted out through TDO; new test data on TDI
may be shifted in at the same time.
Bus Protocol
Boundary Scan .10
A Typical Boundary Scan Cell
shiftDR
SOUT
UpdateDRClockDR
IN OUT01
MUX
Mode_ControlID QQB
SIN
ID QQA
01
M U X
Operation modes: 1. Normal: Mode_Control=0; IN->OUT 2. Scan: ShiftDR=1,ClockDR; TDI->...->SIN->SOUT->...TDO 3. Capture: ShiftDR=0, ClcokDR; IN-> QA, OUT driven by IN or QB
4. Update: Mode_Control=1, UpdateDR; QA->OUT
Boundary Scan .11
State Diagram of TAP Controller
1
1
0
Test-Logic-Reset0
1 1
10
0
1 0 1
0
1
1
1 0 1 0
1
1
0
1
0
0
1
0
0
0
1
0 0
Select-DR-Scan Select-IR-Scan
Capture-DR Capture-IR
Shift-DR Shift-IR
Exit1-DR Exit1-IR
Pause-DR Pause-IR
Exit2-DR Exit2-IR
Update-DR Update-IR
Run-test/idle
Control of instruction registersControl of data registers
1
Boundary Scan .12
States of TAP Controller! Test-Logic-Reset: normal mode! Run-Test/Idle: wait for internal test such as BIST! Select-DR-Scan: initiate a data-scan sequence! Capture-DR: load test data in parallel! Shift-DR: load test data in series! Exit1-DR: finish phase-1 shifting of data! Pause-DR: temporarily hold the scan operation (allow
the bus master to reload data)! Exit2-DR: finish phase-2 shifting of data! Update-DR: parallel load from associated shift registers
Boundary Scan .13
Timing of instruction scan
IDCODE New instruction
Old data
Instruction register
Inactive Active Inactive Active Inactive
TCK
TMS
Control State
TDI
Data input to IR
IR shift-register
Parallel output of IR
Data input to TDR
TDR shift-register
Parallel output of TDR
Register selected
TDO enable
TDO
Test-Logic- R
eset
Run-test/
Idle
Select-DR
- Scan
Select-IR-
Scan
Capture-IR
Shift-IR
Exit
1-IR
Pause-IR
Exit
2-IR
Shift-IR
Exit
1-IR
Update-IR
Run-Test/Idle
= Don't care or undefined
1 1 00 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0
Boundary Scan .14
Timing of data scan TCK
TMS
Control State
TDI
Data input to IR
IR shift-register
Parallel output of IR
Data input to TDR
TDR shift-register
Parallel output of TDR
Instruction Register
TDO enable
TDO
Instruction IDCODE
Old data New data
Test data register
Inactive Active Inactive Inactive
= Don't care or undefined
Active
Run-Test/Idle
SelectDR
-Scan
Capture-D
R
Shift-DR
Exit
1-DR
Pause-DR
Exit
2-DR
Shift-DR
Exit1-D
R
Update-D
R
Run-Test/Idle
SelectDR
-Scan
SelectIR-Scan
Test-Logic- R
eset
0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 1
Boundary Scan .15
Instruction Set! EXTEST:
Test interconnection between chips of board! SAMPLE/PRELOAD:
Sample and shift out data or shift in data only! BYPASS:
Bypass data through a chip! Optional :
INTEST, RUNBIST, CLAMP, IDCODE, USERCODE, HIGH-Z, etc.
Boundary Scan .16
EXTEST
1. Shift-DR (Chip1)
2. Update-DR (Chip1)3. Capture-DR (Chip2)
4. Shift-DR (Chip2)
TDI
TDI
TAP Controller
0 Internal Logic
RegistersTAP Controller
Internal Logic
Registers
TAP Controller
0 Internal Logic
RegistersTAP Controller
0 Internal Logic
Registers
TAP Controller
Internal Logic
RegistersTAP Controller
0 Internal Logic
Registers
TDI
TDI
TDI
TDITDO
TDO
TDO TDO
TDO
TDO
Chip1 Chip2
Boundary Scan .17
EXTEST
TDITDO
TDO
TDI TDO
OutputMUXQBQA
MUX
Internal Logic
TDI
Input
QA QB
MUX
MUX
Internal Logic
Input
2. Update-DR (Chip1)
Output to Chip2
QAQA QBQB
MUX
MUX
Internal Logic
Input from Chip1
3. Capture-DR (Chip2)
Output
QAQA QBQB
OutputMUXQBQA
MUX
Internal Logic
TDI
Input4. Shift-DR (Chip2)
QA QB
TDO
1. Shift-DR (Chip1)
Boundary Scan .18
SAMPLE/PRELOAD
OutputMUX
QBQA
MUX
Internal Logic
TDI TDO
Input
SAMPLE
MUX
MUX
Internal Logic
TDI TDO
Input
PRELOAD Output
QA
QA QA
QB
QB QB
Sample/Preload is one instruction that allows 1. Sample and shift (out) or 2. Shift (in) only
Boundary Scan .19
BYPASS
TAP Controller
Internal Logic
BypassRegister
(1 bit)
TDI TDO
Boundary Scan .20
INTEST
TDO
TAP Controller
0 Internal Logic
RegistersTDI TDO
1.Shift-DR
TAP Controller
0 Internal Logic
RegistersTDI TDO
2.Update-DR
TAP Controller
0 Internal Logic
RegistersTDI TDO
3.Capture-DR
TAP Controller
0 Internal Logic
RegistersTDI
4. Shift-DR
Boundary Scan .21
INTEST
TDITDO
TDO
TDI TDO
OutputMUXQBQA
MUX
Internal Logic
TDI
Input
QA QB
MUX
MUX
Internal Logic
Input
2. Update-DR Output
QAQA QBQB
MUX
MUX
Internal Logic
Input
3. Capture-DROutput
QAQA QBQB
OutputMUXQBQA
MUX
Internal Logic
TDI
Input
4. Shift-DR QA QB
TDO
1. Shift-DR
Boundary Scan .22
Test Bus Configuration
Ring configuration
TD0TDITMSTCK
#1
#2
#N
Busmaster
Application chipsTDITCKTMSTDO
TDI TCK TMSTDO
TDITCKTMSTDO
TD0TDI
TMS1TMS2
TMSNTCK
#1
#2
#N
Busmaster
Application chipsTDITCKTMSTDO
TDITCKTMSTDO
TDITCKTMSTDO
Star configuration
Boundary Scan .23
A Printed Circuit Board with 1149.1 (Ring configuration, test controller on board)
TAP Controller
Internal Logic
TAP Controller
Internal Logic
Chip1 Chip2
Chip3
TDI
TDO
TMS
TCK
MASTERController
M U X
M U X
Registers Registers
TAP Controller
Internal Logic
MUX
Registers
Boundary Scan .24
Boundary Scan Description Language (BSDL)
! Now the IEEE 1149.1b standard! Purposes:
To provide a standard description language for boundary scandevices.
To simplify the design work for boundary scan---automatedsynthesis is possible.
To promote consistency throughout ASIC designers, devicemanufacturers, foundries, test developers and ATEmanufacturers.
For easy incorporation into software tools for test generation,analysis and failure diagnosis.
To reduce possibility of human error when employing boundaryscan in a design.
Boundary Scan .25
Features of BSDL! BSDL describes the testability features of boundary
scan devices which are compatible with 1149.1.! It's a subset of VHDL.! Elements of a design which are absolutely mandatory
for the 1149.1 and system-logic are not included in thelanguage. Examples: BYPASS register, TAP controller, etc.
! BSDL may be used in a full or in a partial VHDLenvironment.
Boundary Scan .26
A Complete Example
TMS
CLK
CORE
LOGIC
TAPController
D1
D2
D3
D4
D5 Q5
Q4
Q3
Q2
Q1
Q6D6
CORE
LOGIC
D1
D2
D3
D4
D5 Q5
Q4
Q3
Q2
Q1
Q6D6
CLK
4
5
1
0
3
6
2
12
10
9
7
8
11
TDI TCK TDO
1
6
7
8
9
10
11
5432
12
13
14
15
16
17
Boundary Scan .27
Entityentity demo is
generic(PHYSICAL_PIN_MAP:string:="UNDEFINED"); port(CLK:in,bit;Q:out,bit_vector(1 to 6);D:in,bit_vector(1 to 6); GND,VCC:linkage,bit;TDO:out,bit;TMS,TCK,TDI:in,bit); use STD_1149_1_1990.all; attribute PIN_MAP of demo:entity is PHYSICAL_PIN_MAP; constant DW_PACKAGE:PIN_MAP_STRING:="CLK:1," & "Q(6,7,8,9,10,11),D(12,13,14,15,16,17),GND:18,VCC:19," & "TDO:5,TMS:4,TCK:3,TDI:2"; attribute TAP_SCAN_IN of TDI:signal is true; attribute TAP_SCAN_MODE of TMS:signal is true; attribute TAP_SCAN_OUT of TDO:signal is true; attribute TAP_SCAN_CLOCK of TCK:signal is (20e6,BOTH); attribute INSTRUCTION_LENGTH of demo:entity is 4;
attribute INSTRUCTION_OPCODE of demo:entity is "BYPASS (11111),"& "EXTEST(0000)," & "SAMPLE(1100,1010)," & "INTEST(1010)";
Boundary Scan .28
Entity (Cont.) attribute INSTRUCTION_CAPTURE of demo:entity is "0101";
attribute BOUNDARY_CELLS of demo:entity is "BC_1"; attribute BOUNDARY_LENGTH of demo:entity is 12; attribute BOUNDARY_REGISTER of demo:entity is -- num cell port function safe [ccell disval rslt] "12 (BC_1,CLK,input,X)," & "11 (BC_1,D(1),input,X)," & "10 (BC_1,D(2),input,X)," & "9 (BC_1,D(3),input,X)," & "8 (BC_1,D(4),input,X)," & "7 (BC_1,D(5),input,X)," & "6 (BC_1,D(6),input,X)," & "5 (BC_1,Q(1),output3,X,000,1,Z)," & "4 (BC_1,Q(2),output3,X,000,1,Z)," & "3 (BC_1,Q(3),output3,X,000,1,Z)," & "2 (BC_1,Q(4),output3,X,005,1,Z)," & "1 (BC_1,Q(5),output3,X,005,1,Z)," & "0 (BC_1,Q(6),output3,X,005,1,Z)";end demo;
Boundary Scan .29
Package package STD_1149_1_1990 is
attribute PIN_MAP:string; subtype PIN_MAP_STRING is string;
type CLOCK_LEVEL is (LOW, BOTH); type CLOCK_INFO is record FREQ:real; LEVEL:CLOCK_LEVEL; end record;
attribute TAP_SCAN_IN: boolean; attribute TAP_SCAN_OUT:boolean; attribute TAP_SCAN_CLOCK:CLOCK_INFO; attribute TAP_SCAN_MODE:boolean; attribute TAP_SCAN_RESET:boolean;
attribute INSTRUCTION_LENGTH:integer; attribute INSTRUCTION_OPCODE:string; attribute INSTRUCTION_CAPTURE:string;
Boundary Scan .30
Package (Cont.) type ID_BITS is ('0', '1', 'X');
type ID_STRING is array (31 downto 0) of ID_BIT
attribute REGISTER_ACCESS:string
type BSCAN_INST is (EXTEST, SAMPLE, INTEST,RUNBIST);type CELL_TYPE is (INPUT, INTERNAL, CLOCK, CONTROL, OUTPUT2, OUTPUT3, BIDIR_IN, BIDIR_OUT);type CAP_DATA is (PI, PO, UPD, CAP, X, ZRRO, ONE);type CELL_DATA is record CT:CELL_TYPE; I:BSCAN_INST; CD:CAP_DATA;end record;type CELL_INFO is array(positive range<>) of CELL_DATA;constant BC_1:CELL_INFO;
attribute BOUNDARY_CELLS:string;attribute BOUNDARY_LENGTH:integer;attribute BOUNDARY_REGISTER:string;attribute DESIGN_WARING:string;end STD_1149_1_1990;
Boundary Scan .31
Package Body constant BC_1:CELL_INFO:=(
(INPUT,EXTEST,PI), (OUTPUT2,EXTEST,PI), (INPUT,SAMPLE,PI), (OUTPUT2,SAMPLE,PI), (INPUT,INTEST,PI). (OUTPUT2,INTEST,PI), (OUTPUT3,EXTEST,PI), (INTERNAL,EXTEST,PI), (OUTPUT3, SAMPLE,PI), (INTERNAL,SAMPLE,PI), (OUTPUT3, INTEST,PI), (INTERNAL,INTEST,PI), (CONTROL,EXTEST,PI),(CONTROL,EXTEST,PI), (CONTROL,SAMPLE,PI),(CONTROL,SAMPLE,PI), (CONTROL,INTEST,PI),(CONTROL,INTEST,PI)
);
