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1998 Morgan Kaufmann Publishers
Capítulo 6Pipeline
1998 Morgan Kaufmann Publishers
Pipeline: analogia com linha de produção
• Tempo de fabricação de um carro: C+M+C+P+A• Taxa de produção (carros/h): medido na saída
– Throughput (vazão): depende do número de estágios e do balanceamento
• Objetivo do pipeline:– distribuir e balancear o tempo em cada estágio– otimizar o uso de HW dos estágios (taxa de ocupação)– resumo: aumentar a velocidade e diminuir o hardware
carro1 Chassi Mec Carroc. Pint. Acab.
carro2 Chassi Mec Carroc. Pint. Acab.
carro3 Chassi Mec Carroc. Pint. Acab.
→ tempo
1998 Morgan Kaufmann Publishers
Pipelines• Melhorar o desempenho através do aumento do throughput
• tempo de execução de uma instrução: 8 ns e 9 ns (com ou sem pipe)• throughput: 1 instr / 8ns (sem pipeline) ou 1 instr / 2 ns (com)• # de estágios = 5; ganho de 4:1;
Instructionfetch Reg ALU Data
access Reg
8 ns Instructionfetch Reg ALU Data
access Reg
8 ns Instructionfetch
8 ns
Time
lw $1, 100($0)
lw $2, 200($0)
lw $3, 300($0)
2 4 6 8 10 12 14 16 18
2 4 6 8 10 12 14
. . .
Programexecutionorder(in instructions)
Instructionfetch Reg ALU Data
access Reg
Time
lw $1, 100($0)
lw $2, 200($0)
lw $3, 300($0)
2 ns Instructionfetch Reg ALU Data
access Reg
2 ns Instructionfetch Reg ALU Data
access Reg
2 ns 2 ns 2 ns 2 ns 2 ns
Programexecutionorder(in instructions)
1998 Morgan Kaufmann Publishers
Pipeline
• O que o torna factível?– Todas as instruções são do mesmo tamanho– Poucos formatos de instruções– Operandos de memória aparecem apenas em loads e stores
• O que o torna difícil– Hazards estruturais: recursos compartilhados (Ex: memória)– Hazards de controle: Preocupação com instruções de saltos– Hazards de dados: uma instrução depende dos resultados
gerados pela instrução anterior
• Nosso foco: um pipeline simples abordando essas questões!
• Posteriormente (ou durante essa parte do curso..)– Tratamento de exceções...– Execução inorder, foradeordem, etc.
1998 Morgan Kaufmann Publishers
Pipeline: Idéia básica
• O que é necessário para dividir a via de dados em estágios de execução?
Instructionmemory
Address
4
32
0
Add AddresultShiftleft 2
Instruction
Mux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1Readregister 2
16 Signextend
WriteregisterWritedata
ReaddataAddressData
memory1
ALUresultMux
ALUZero
IF : Instruction fetch ID: Instruction decode /register file read
EX: Execute/address calculation
MEM: Mem ory access WB: Write back
1998 Morgan Kaufmann Publishers
IM Reg DM RegALU
IM Reg DM RegALU
CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7
Time (in clock cycles)
lw $2, 200($0)
lw $3, 300($0)
Programexecutionorder(in instructions)
lw $1, 100($0) IM Reg DM RegALU
Uma representação para o pipeline
• Hachurado representa “atividade”• Representação alternativa: imaginando que cada instrução tenha a sua
própria via de dados• Outra representação: foto no tempo (snapshot)
1998 Morgan Kaufmann Publishers
Via de dados com pipeline
• O que é produzido em cada estágio é armazenado em um registrador de pipeline para uso pelo próximo estágio
• Problemas com o endereço do registrador de escrita?? Caminhando para esquerda?
Instructionmemory
Address
4
32
0
Add AddresultShiftleft 2
Instruc
tion
IF/ID EX/MEM MEM/WB
Mux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1Readdata 2
Readregister 1Readregister 2
16 Signextend
WriteregisterWritedata
Readdata
1
ALUresultMux
ALUZero
ID/EX
Datamemory
Address
1998 Morgan Kaufmann Publishers
Via de dados corrigida
Instructionmemory
Address
4
32
0
Add AddresultShiftleft 2
Instruc
tionIF/ID EX/MEM MEM/WB
Mux
0
1
Add
PC
0
Address
W ritedata
Mux
1Registers
Readdata 1Readdata 2
Readregister 1Readregister 2
16 Signextend
Wr itereg is terWritedata
ReaddataDatamemory
1
ALUresultMux
ALUZero
ID/EX
Exemplo com sub e lw (1)
Instructionmemory
Address
4
32
0
Add Addresult
Shiftleft 2
Inst
ructi
on
IF/ID EX/MEM MEM/WB
Mux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
16Sign
extend
Writeregister
Writedata
Readdata
1
ALUresultM
ux
ALUZero
ID/EX
Instruction decodelw $10, 20($1)
Instruction fetchsub $11, $2, $3
Instructionmemory
Address
4
32
0
Add Addresult
Shiftleft 2
Instr
uctio
n
IF/ID EX/MEM MEM/WB
Mux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
16Sign
extend
Writeregister
Writedata
Readdata
1
ALUresultM
ux
ALUZero
ID/EX
Instruction fetchlw $10, 20($1)
Address
Datamemory
Address
Datamemory
Clock 1
Clock 2
Instructionmemory
Address
4
0
Add Addresult
Shiftleft 2
Inst
ructi
onIF/ID EX/MEM MEM/WB
Mux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
3216Sign
extend
Writeregister
Writedata
Memorylw $10, 20($1)
Readdata
1
ALUresultM
ux
ALUZero
ID/EX
Executionsub $11, $2, $3
Instructionmemory
Address
4
0
Add Addresult
Shiftleft 2
Instr
uctio
n
IF/ID EX/MEM MEM/WB
Mux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Writeregister
Writedata
Readdata
1
ALUresultM
ux
ALUZero
ID/EX
Executionlw $10, 20($1)
Instruction decodesub $11, $2, $3
3216Sign
extend
Address
Datamemory
Datamemory
Address
Clock 3
Clock 4
Exemplo com sub e lw (2)
Exemplo com sub e lw (3) Instruction
memory
Address
4
32
0
Add Addresult
1
ALUresult
Zero
Shiftleft 2
Instr
uctio
n
IF/ID EX/MEMID/EX MEM/WB
Write backMux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
16Sign
extend
Mux
ALUReaddata
Writeregister
Writedata
lw $10, 20($1)
Instructionmemory
Address
4
32
0
Add Addresult
1
ALUresult
Zero
Shiftleft 2
Inst
ructi
onIF/ID EX/MEMID/EX MEM/WB
Write backMux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
16Sign
extend
Mux
ALUReaddata
Writeregister
Writedata
sub $11, $2, $3
Memorysub $11, $2, $3
Address
Datamemory
Address
Datamemory
Clock 6
Clock 5
1998 Morgan Kaufmann Publishers
Representando pipelines graficamente
• Essa representação pode ajudar a responder questões como:– Quantos ciclos são necessários para executar esse código?– O que a ULA está fazendo no ciclo 4?
• Use essa representação para entender melhor como o pipeline funciona
IM Reg DM Reg
IM Reg DM Reg
CC 1 CC 2 CC 3 CC 4 CC 5 CC 6
Time (in clock cycles)
lw $10, 20($1)
Programexecutionorder(in instructions)
sub $11, $2, $3
ALU
ALU
1998 Morgan Kaufmann Publishers
Controle do pipeline
PC
Instructionmemory
Address
Instru
ction
Instruction[20–16]
MemtoReg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction[15–0]
0
0RegistersWriteregisterWritedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
Signextend
Mux1
Writedata
Readdata M
ux
1
ALUcontrol
RegWrite
MemRead
Instruction[15–11]
6
IF/ID ID/EX EX/MEM MEM/WB
MemWrite
AddressData
memory
PCSrc
Zero
Add Addresult
Shiftleft 2
ALUresult
ALUZero
Add
0
1
Mux
0
1
Mux
• campo function é usado para controle da ALU (EX)• sinais de controle: os mesmos do capítulo 5, ciclo único• PC e registradores de pipeline escritos em todos ciclos: não é necessário controle
1998 Morgan Kaufmann Publishers
• O que necessita ser controlado em cada estágio?– Busca da instrução e incremento do PC– Decodificação da instrução / Leitura do registrador– Execução– Leitura/Escrita da memória– Escrita no registrador
• Como o controle seria manipulado em um projeto de automóvel– Controle central indicando o que cada parte deve fazer?–
Controle do pipeline
1998 Morgan Kaufmann Publishers
• Os sinais de controle “passam” pelo pipeline assim como os dados
Controle do pipeline
Execution/Address Calculation stage control lines
Memory access stage control lines
Writeback stage control
lines
InstructionReg Dst
ALU Op1
ALU Op0
ALU Src Branch
Mem Read
Mem Write
Reg write
Mem to Reg
Rformat 1 1 0 0 0 0 0 1 0lw 0 0 0 1 0 1 0 1 1sw X 0 0 1 0 0 1 0 Xbeq X 0 1 0 1 0 0 0 X
Control
EX
M
WB
M
WB
WB
IF/ID ID/EX EX/MEM MEM/WB
Instruction
1998 Morgan Kaufmann Publishers
Controle na via de dados
PC
Instructionmemory
Instr u
ctio n
Add
Instruction[20–16]
Mem t
o Reg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction[15–0]
0
0
Mux
0
1
Add Addresult
RegistersWriteregisterWritedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
Signextend
Mux1
ALUresult
Zero
Writedata
Readdata M
ux
1
ALUcontrol
Shiftleft 2Re
gWri te
MemRead
Control
ALU
Instruction[15–11]
6
EX
M
WB
M
WB
WBIF/ID
PCSrc
ID/EX
EX/MEM
MEM/WB
Mux
0
1
MemW
r ite
AddressData
memory
Address
1998 Morgan Kaufmann Publishers
Exemplo (pag. 471)
Instructionmemory
Instruction[20–16]
Memt
oReg
ALUOp
Branch
RegDst
ALUSrc
4
Instruction[15–0]
0
Mux
0
1
Add Addresult
RegistersWriteregisterWritedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
Signextend
Mux1
ALUresultZero
ALUcontrol
Shiftleft 2Re
gWrite
MemRead
Control
ALU
Instruction[15–11]
EX
M
WB
M
WB
WB
Instru
ction
IF/ID EX/MEMID/EX
ID : b e fore<1> E X : b efore <2> M E M : be fore<3> W B : befo re < 4>
MEM/WB
IF : lw $10, 2 0($1)
000
00
0000
000
00
0000
00
000
00
Mux
0
1
Add
PC
0
Datamemory
Address
Writedata
Readdata Mux
1
WB
EX
M
Instructionmemory
Memt
oReg
ALUOp
Branch
RegDst
ALUSrc
4
0
Mux
0
1
Add Addresult
WriteregisterWritedata
Mux1
ALUresultZero
ALUcontrol
Shiftleft 2Re
gWrite
ALU
M
WB
WB
Instru
ction
IF/ID EX/MEMID/EX
ID : lw $10 , 20($1) E X : b efore <1> M E M : be fore<2> W B : befo re < 3>
MEM/WB
IF : sub $1 1 , $2, $3
010
11
0001
000
00
0000
00
000
00
Mux
0
1
Add
PC
0Writedata
Readdata Mux
1
lw Control
Registers
Readdata 1
Readdata 2
Readregister 1Readregister 2
X
10
20
X
1
Instruction[20–16]
Instruction[15–0] Signextend
Instruction[15–11]
20
$X
$1
10
X
MemW
rite
MemRead
MemW
rite
Datamemory
Address
Address
Address
C lo c k 2
C lo c k 1
lw $10, 20($1)sub $11, $2, $3and $12, $4, $5or $13, $6, $7add $14, $8, $9
1998 Morgan Kaufmann Publishers
Exemplo (pag. 471)
Instructionmemory
Address
Instruction[20–16]
Memt
oReg
Branch
ALUSrc
4
Instruction[15–0]
0
1
Add Addresult
RegistersWriteregisterWritedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
ALUresult
Shiftleft 2Re
gWrite
MemRead
Control
ALU
Instruction[15–11]
EX
M
WB
WB
Instru
ction
IF/ID EX/MEMID/EX
ID : sub $11, $ 2, $3 E X: lw $10, . . . M E M : b efo re<1 > W B : be fo re<2>
MEM/WB
IF : an d $12 , $4, $ 5
000
10
1100
010
11
0001
00
000
00
Mux
0
1
Add
PC
0Writedata
Readdata Mux
1
WB
EX
M
Instructionmemory
Address
Memt
oReg
ALUOp
Branch
RegDst
ALUSrc
4
0
0
1
Add Addresult
WriteregisterWritedata 1
ALUresult
ALUcontrol
Shiftleft 2Re
gWrite
M
WB
Instru
ction
IF/ID EX/MEMID/EX
ID : a nd $ 12, $ 4 , $5 E X: sub $1 1 , . . . M E M : lw $ 10 , . . . W B : be fo re<1>
MEM/WB
IF : or $1 3, $6 , $ 7
000
10
1100
000
10
1010
11
100
00
Mux
0
1
Add
PC
0Writedata
Mux
1
and Control
Registers
Readdata 1
Readdata 2
Readregister 1Readregister 2
12
X
X
5
4
Instruction[20–16]
Instruction[15–0]
Instruction[15–11]
X
$5
$4
X
12
MemW
rite
MemRead
MemW
rite
sub
11
X
X
3
2
X
$3
$2
X
11
$1
20
10Mux
0
Mux1
ALUOp
RegDst
ALUcontrol
M
WB
$3
$2
11Mux
Mux
ALUAddress ReaddataData
memory
10
WB
Zero
Zero
Signextend
Signextend
Datamemory
Address
C lo c k 3
C lo c k 4
lw $10, 20($1)sub $11, $2, $3and $12, $4, $5or $13, $6, $7add $14, $8, $9
1998 Morgan Kaufmann Publishers
Exemplo (pag. 471)
Instructionmemory
Address
Instruction[20–16]
Branch
ALUSrc
4
Instruction[15–0]
0
1
Add Addresult
RegistersWriteregisterWritedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
ALUresult
Shiftleft 2Re
gWrite
MemRead
Control
ALU
Instruction[15–11]
EX
M
WB
Instru
ction
IF/ID EX/MEMID/EX
ID : o r $ 13, $6 , $7 E X : and $12 , . . . M E M : sub $1 1 , . . . W B : lw $ 10, . . .
MEM/WB
IF : add $14, $ 8, $ 9
000
10
1100
000
10
1010
10
000
Mux
0
1
Add
PC
0Writedata
Readdata Mux
1
WB
EX
M
Instructionmemory
Address
Memto
Reg
ALUOp
Branch
RegDst
ALUSrc
4
0
0
1
Add Addresult
1
ALUresult
ALUcontrol
Shiftleft 2Re
gWrite
M
WB
Instru
ction
IF/ID EX/MEMID/EX
ID : a dd $14 , $8 , $ 9 E X : o r $1 3 , . . . M E M : an d $12 , . . . W B : su b $11 , . . .
MEM/WB
IF : a fte r< 1 >
000
10
1100
000
10
1010
10
000
10
Mux
0
1
Add
PC
0Writedata
Mux
1
add Control
Registers
Readdata 1
Readdata 2
Readregister 1Readregister 2
14
X
X
9
8
Instruction[20–16]
Instruction[15–0]
Instruction[15–11]
X
$9
$8
X
14
MemW
rite
MemRead
MemW
rite
or
13
X
X
7
6
X
$7
$6
X
13
$4
Mux
0
Mux1
ALUOp
RegDst
ALUcontrol
M
WB
$7
$6
13Mux
Mux
ALU Readdata
12
WB
11 10
10 $5
12
WB
Memto
Reg
11
11
11
WriteregisterWritedata
Zero
Zero
Datamemory
Address
Datamemory
Address
Signextend
Signextend
C lo c k 5
C lo c k 6
lw $10, 20($1)sub $11, $2, $3and $12, $4, $5or $13, $6, $7add $14, $8, $9
1998 Morgan Kaufmann Publishers
Exemplo (pag. 471)
Instructionmemory
Address
Instruction[20–16]
Branch
ALUSrc
4
Instruction[15–0]
0
1
Add Addresult
RegistersWriteregisterWritedata
ALUresult
Shiftleft 2Re
gWrite
MemRead
Control
ALU
Instruction[15–11]
Signextend
EX
M
WB
Instru
ction
IF/ID EX/MEMID/EX
ID: a fte r< 1 > E X: a dd $ 14, . . . M EM : or $13 , . . . W B: and $1 2 , . . .
MEM/WB
IF : a fte r<2>
000
00
0000
000
10
1010
10
000
Mux
0
1
Add
PC
0Writedata
Readdata Mux
1
WB
EX
M
Instructionmemory
Address
Memt
oReg
ALUOp
Branch
RegDst
ALUSrc
4
0
0
1
Add Addresult
1
ALUresultZero
ALUcontrol
Shiftleft 2Re
gWrite
M
WB
Instru
ction
IF/ID EX/MEMID/EX
ID: a fte r< 2 > E X: a fter<1> M EM : add $14, . . . W B: or $13, . . .
MEM/WB
IF : a fte r<3>
000
00
0000
000
00
0000
10
000
10
Mux
0
1
Add
PC
0Writedata
Mux
1
Control
Registers
Readdata 1
Readdata 2
Readregister 1Readregister 2
Instruction[20–16]
Instruction[15–0] Signextend
Instruction[15–11]
MemW
rite
MemRead
MemW
rite
$8
Mux
0
Mux1
ALUOp
RegDst
ALUcontrol
M
WB
Mux
Mux
ALU Readdata
14
WB
13 12
12 $9
14
WB
Memt
oReg
10
13
13
WriteregisterWritedata
Readdata 1
Readdata 2
Readregister 1Readregister 2 Zero
Datamemory
Address
Datamemory
Address
C lo c k 7
C lo c k 8
lw $10, 20($1)sub $11, $2, $3and $12, $4, $5or $13, $6, $7add $14, $8, $9
