CDA4253FPGASystemDesign

ThePicoBlazeMicrocontroller

HaoZhengCompSci&EngUofSouthFlorida

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OverviewofPicoBlaze

•  So:-coremicrocontrollerinVHDL:portabletootherplaAorms.

•  Small:occupies~20CLBs.•  Respectableperformance:50MIPS•  Predictableperformance:everyinstrucOon

takes2cycles.•  Suitableforsimpledataprocessingandcontrol.

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RequiredReading

• P.Chu,FPGAPrototypingbyVHDLExamples Chapter14,PicoBlazeOverview

RecommendedReading•  PicoBlaxe8-bitEmbeddedMicrocontrollerUser

Guide(UG129)•  K.Chapman,PicoBlazeforSpartan-6,Virtex-6,

and7-Series(KCPSM6)

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BlockdiagramofaGeneral-PurposeProcessor

ctrl

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BlockdiagramofaGeneral-PurposeProcessor(Microcontroller)

PicoBlazeOverview

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8-bitdatawidth,18-bitinstrucOonwidth,10-bitprogramaddress

SizeofPicoBlaze-6inSpartan6

1.  ResourceUOlizaOoninCLBSlices•  26CLBSlices

•  1.1%ofSpartan-6usedinNexys3

2.  NumberofPicoBlaze-6coresfi_nginsideoftheSpartan-6

FPGA(XC6SLX16)usedintheNexys3FPGAboard

•  87PicoBlazecores

SpeedofPicoBlazeonBasys-3

1.  MaximumClockFrequency

•  100MHz

2.  MaximumnumberofinstrucOonspersecond

•  50millionsofinstrucOonspersecond(MIPS)

FixedOming:idealforreal-OmecontrolapplicaOons,i.e.flightcontrol,manufacturingprocesscontrol,...

RegisterFileofPicoBlaze-3

0 1

7 7 7

0 0 0

Address

7 0 7 0 7 0 7 0 7 0

16 Registers

8-bit

7 0 F

s0 s1 s2 s3 s4 s5 s6 s7

2 3 4 5 6 7

sF

9

DefiniNonofFlags

Z = 1 if result = 0 0 otherwise

Zero flag - Z zero condition

Example*

C = 1 if result > 28-1 (for addition) or

result < 0 (for subtraction)

0 otherwise *Applies only to addition or subtraction related instructions,

refer to the following slides otherwise

Carry flag - C overflow, underflow, or various conditions

Flags are set or reset after ALU operations

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11

InterfaceofPicoBlaze

KCPSM=constant(K)codedprogrammablestatemachine

Inputs Outputs

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InterfaceofPicoBlaze

in_port[7:0]–inputdataportthatcarriesthedatafortheINPUTinstrucOon.

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InterfaceofPicoBlaze

out_port[7:0]–carriestheoutputdataforanOUTPUTinstrucOon.

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InterfaceofPicoBlaze

port_id[7:0]–addressesofcomponentsconnectedtoPicoBlaze.HoldsfortwocyclesduringanINPUT/OUTPUTinstrucOon.

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InterfaceofPicoBlaze

write_strobe–beingasserted‘1’validatesthedataontheoutput_port[7:0].

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InterfaceofPicoBlaze

read_strobe–beingasserted‘1’indicatesthecaptureofthedataontheinput_port[7:0]duringanINPUTinstrucOon.

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InterfaceofPicoBlaze

reset–needstobeassertedforatleastonecycle.

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InterfaceofPicoBlaze

interrupt–assertitforatleasttwocyclestotriggeraninterrupteventinPicoBlaze.

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InterfaceofPicoBlaze

interrupt_ack–acknowledgesthecurrentinterrupthasbeenrecognizedbyPicoBlaze.Usedtoclearthecurrentinterrupt.

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InterfaceofPicoBlaze–SummaryName Direction Size Function clk input 1 System clock signal. reset input 1 Reset signal. address output 10 Address of the instruction memory.

Specifies address of the instruction to be retrieved.

instruction input 18 Fetched instruction. port_id output 8 Address of the input or output port. in_port input 8 Input data from I/O peripherals. read_strobe output 1 Strobe associated with the input

operation. out_port output 8 Output data to I/O peripherals. write_strobe output 1 Strobe associated with the output

operation. interrupt input 1 Interrupt request from I/O peripherals.

interrupt_ack output 1 Interrupt acknowledgment to I/O peripherals

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UseofPicoBlazeinVHDLDesign

PicoBlaze 8-bit Embedded Microcontroller www.xilinx.com 61UG129 (v2.0) June 22, 2011

Chapter 9

Using the PicoBlaze Microcontroller in an FPGA Design

The PicoBlaze™ microcontroller is primarily designed for use in a VHDL design flow. However, both Verilog and black box instantiation are also supported, as described below.

VHDL Design FlowThe PicoBlaze microcontroller is supplied as a VHDL source file, called KCPSM3.vhd, which is optimized for efficient and predictable implementation in a Spartan-3, Spartan-6, and Virtex-6 FPGA. The code is suitable for both synthesis and simulation and was developed and tested using the Xilinx Synthesis Tool (XST) for logic synthesis and ModelSim for simulation. Designers have also successfully used other logic synthesis and simulation tools. The VHDL source code must not be modified in any way.

KCPSM3 ModuleThe KCPSM3 module contains the PicoBlaze ALU, register file, scratchpad, RAM, etc. The only function not included is the instruction store. The component declaration for the KCPSM3 module appears in Figure 9-1. Figure 9-2 lists the KCPSM3 component instantiation.

Figure 9-1: VHDL Component Declaration of KCPSM3

component KCPSM3port ( address : out std_logic_vector( 9 downto 0); instruction : in std_logic_vector(17 downto 0); port_id : out std_logic_vector( 7 downto 0); write_strobe : out std_logic; out_port : out std_logic_vector( 7 downto 0); read_strobe : out std_logic; in_port : in std_logic_vector( 7 downto 0); interrupt : in std_logic; interrupt_ack : out std_logic; reset : in std_logic; clk : in std_logic );end component;

PicoBlazeComponentDeclaraOon

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UseofPicoBlazeinVHDLDesign

PicoBlazeComponentInstanOaOon

62 www.xilinx.com PicoBlaze 8-bit Embedded MicrocontrollerUG129 (v2.0) June 22, 2011

Chapter 9: Using the PicoBlaze Microcontroller in an FPGA Design

Connecting the Program ROM The PicoBlaze program ROM is used within a VHDL design flow. The PicoBlaze assembler generates a VHDL file in which a block RAM and its initial contents are defined. This VHDL file can be used for both logic synthesis and simulation of the processor.

Figure 9-3 shows the component declaration for the program ROM, and Figure 9-4 shows the component instantiation. The name of the program ROM, shown as "prog_rom" in the following figures, is derived from the name of the PicoBlaze assembler source file. For example, if the assembler source file is named phone.psm, then the assembler generates a program ROM definition file called phone.vhd.

To speed development, a VHDL file called embedded_KCPSM3.vhd is provided. In this file, the PicoBlaze macro is connected to its associated block RAM program ROM. This entire module can be embedded in the design application, or simply used to cut and paste the component declaration and instantiation information into the user’s design files.

Figure 9-2: VHDL Component Instantiation of the KCPSM3

processor: kcpsm3 port map( address => address_signal, instruction => instruction_signal, port_id => port_id_signal, write_strobe => write_strobe_signal, out_port => out_port_signal, read_strobe => read_strobe_signal, in_port => in_port_signal, interrupt => interrupt_signal, interrupt_ack => interrupt_ack_signal, reset => reset_signal, clk => clk_signal );

Figure 9-3: VHDL Component Declaration of Program ROM

Figure 9-4: VHDL Component Instantiation of Program ROM

component prog_rom port ( address : in std_logic_vector( 9 downto 0); instruction : out std_logic_vector(17 downto 0); clk : in std_logic );end component;

program: prog_romport map( address => address_signal, instruction => instruction_signal, clk => clk_signal );

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UseofPicoBlazeinVHDLDesign

PicoBlazeProgramROMComponentDeclaraOon/InstanOaOon

62 www.xilinx.com PicoBlaze 8-bit Embedded MicrocontrollerUG129 (v2.0) June 22, 2011

Chapter 9: Using the PicoBlaze Microcontroller in an FPGA Design

Connecting the Program ROM The PicoBlaze program ROM is used within a VHDL design flow. The PicoBlaze assembler generates a VHDL file in which a block RAM and its initial contents are defined. This VHDL file can be used for both logic synthesis and simulation of the processor.

Figure 9-3 shows the component declaration for the program ROM, and Figure 9-4 shows the component instantiation. The name of the program ROM, shown as "prog_rom" in the following figures, is derived from the name of the PicoBlaze assembler source file. For example, if the assembler source file is named phone.psm, then the assembler generates a program ROM definition file called phone.vhd.

To speed development, a VHDL file called embedded_KCPSM3.vhd is provided. In this file, the PicoBlaze macro is connected to its associated block RAM program ROM. This entire module can be embedded in the design application, or simply used to cut and paste the component declaration and instantiation information into the user’s design files.

Figure 9-2: VHDL Component Instantiation of the KCPSM3

processor: kcpsm3 port map( address => address_signal, instruction => instruction_signal, port_id => port_id_signal, write_strobe => write_strobe_signal, out_port => out_port_signal, read_strobe => read_strobe_signal, in_port => in_port_signal, interrupt => interrupt_signal, interrupt_ack => interrupt_ack_signal, reset => reset_signal, clk => clk_signal );

Figure 9-3: VHDL Component Declaration of Program ROM

Figure 9-4: VHDL Component Instantiation of Program ROM

component prog_rom port ( address : in std_logic_vector( 9 downto 0); instruction : out std_logic_vector(17 downto 0); clk : in std_logic );end component;

program: prog_romport map( address => address_signal, instruction => instruction_signal, clk => clk_signal );

62 www.xilinx.com PicoBlaze 8-bit Embedded MicrocontrollerUG129 (v2.0) June 22, 2011

Chapter 9: Using the PicoBlaze Microcontroller in an FPGA Design

Connecting the Program ROM The PicoBlaze program ROM is used within a VHDL design flow. The PicoBlaze assembler generates a VHDL file in which a block RAM and its initial contents are defined. This VHDL file can be used for both logic synthesis and simulation of the processor.

Figure 9-3 shows the component declaration for the program ROM, and Figure 9-4 shows the component instantiation. The name of the program ROM, shown as "prog_rom" in the following figures, is derived from the name of the PicoBlaze assembler source file. For example, if the assembler source file is named phone.psm, then the assembler generates a program ROM definition file called phone.vhd.

To speed development, a VHDL file called embedded_KCPSM3.vhd is provided. In this file, the PicoBlaze macro is connected to its associated block RAM program ROM. This entire module can be embedded in the design application, or simply used to cut and paste the component declaration and instantiation information into the user’s design files.

Figure 9-2: VHDL Component Instantiation of the KCPSM3

processor: kcpsm3 port map( address => address_signal, instruction => instruction_signal, port_id => port_id_signal, write_strobe => write_strobe_signal, out_port => out_port_signal, read_strobe => read_strobe_signal, in_port => in_port_signal, interrupt => interrupt_signal, interrupt_ack => interrupt_ack_signal, reset => reset_signal, clk => clk_signal );

Figure 9-3: VHDL Component Declaration of Program ROM

Figure 9-4: VHDL Component Instantiation of Program ROM

component prog_rom port ( address : in std_logic_vector( 9 downto 0); instruction : out std_logic_vector(17 downto 0); clk : in std_logic );end component;

program: prog_romport map( address => address_signal, instruction => instruction_signal, clk => clk_signal );

KCPSM3andprog_romaregeneratedautomaOcallybytheassembler.

PicoBlazeDesignFlow

© Copyright 2010-2014 Xilinx .

Page 11

Program Memory

KCPSM6 Programs are stored in Block Memory (BRAM). The number of BRAMs required depends on the target device as well as the size of the program. Due to the flexibility of BRAM and FPGA devices it would be possible to implement a memory of any size up to the maximum of 4K instructions supported by KCPSM6. However the most natural and commonly used program sizes are shown in the table below showing how many BRAMs are required.

Hint – A program of up to 128 or 256 instructions can be implemented in just 9 or 18 Slices and this can be a useful technique when there is a high demand for block memory within a design (see page 47 for details). Even with such small programs, KCPSM6 can implement a complex state machine in ~40 Slices. However, it is strongly recommended that a program is always developed using block memory first using JTAG Loader to help you.

Programs Size (instructions)

0.125K / 0.25K

1K

2K

4K

Spartan-6 Vitex-6, Artix-7, Kintex-7, Virtex-7

9 / 18 Slices

1 BRAM

2 BRAMs

4 BRAMs

½ BRAM

1 BRAM

2 BRAM

The 36k-bit BRAMs found in Virtex-6 and 7-Series devices are naturally suited to programs of up to 2K instructions whereas the 18k-bit BRAMs of Spartan-6 are best suited to programs of 1K instructions. These are therefore the recommended sizes when initially setting up KCPSM6.

These sizes are also supported by the files provided and fit well in the devices when required.

Whilst a 4K memory is supported in a Spartan-6 is not such a natural fit and will result in a lower maximum clock frequency (i.e. Be aware of this when operating closer to device limits).

ROM_form.vhd ROM_form.v (Template)

KCPSM6 Assembler

your_program.psm

your_program.vhd your_program.v (Used in design)

Program Memory Definition To be completely compatible with the normal hardware design flow the program memory is defined by a standard HDL file which you include in your design in the same way as any other component (see next page). This file is generated by the KCPSM6 assembler and you will see how to do that later but the basic principle is as follows.... The KCPSM6 assembler reads and assembles your program (PSM file) into the instruction codes. It then reads an HDL template file called ‘ROM_form.vhd’ (or ROM_form.v) into which it inserts your assembled program and writes out the HDL file defining the program memory containing your program for use in your design.

Due to the errata described in EN148 there are no plans to support a 0.5K memory using a 9K BRAM in Spartan-6.

9 / 18 Slices

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DevelopmentFlowofaSystem

withPicoBlaze

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PicoBlazeProgrammingModel

AddressingModes

Direct mode

ADD sa, sf

INPUT s5, 2a

sa sa + sf

PORT_ID 2a s5 IN_PORT

Indirect mode STORE s3, (sa)

INPUT s9, (s2)

RAM[sa] s3

PORT_ID s2 s9 IN_PORT

s7 s7 – 07

s2 s2 + 08 + C

Immediate mode

SUB s7, 07

ADDCY s2, 08

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PicoBlazeInstrucNonSetSummary(1)

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PicoBlazeInstrucNonSetSummary(2)

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PicoBlazeInstrucNonSetSummary(3)

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