CDA 4253/CIS 6930 FPGA System Design

Hao ZhengDept of Comp Sci & Eng

U of South Florida

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Introduction• Traditional approaches to computation: HW & SW• HW (ASICs – Application Specific ICs)– Fixed on a particular application– Efficient: performance, silicon area, power– Higher cost/per application

• SW on microprocessors– Programmability: used in many applications– Less efficient: performance, silicon area, power– Lower cost/per application

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Introduction

• Field Programmable Gate Arrays (FPGAs)– Spatial computing: similar to HW– Reprogrammable: similar to SW– Faster than SW and more flexible than HW– More cost-effective for low volume applications – Harder to program than SW– Less efficient than HW: performance, silicon area,

power

• But ASIC HW is going away – design cost too high– FPGA design is promising!

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Course Descriptions• Overview of FPGA architectures– Basic building blocks– Field programmability

• Digital design with VHDL– Learn to write VHDL for synthesis and simulation– Analyze and understand existing examples– Modify or use the existing examples for new designs

• Basic concepts of FPGA design flow• Basic Ideas of high-level synthesis– Mapping from algorithms to VHDL.

• Other relevant topics: heterogeneous computing, partial reconfiguration, etc

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Course Outcomes• Use VHDL for design/simulation/synthesis

- One of the most basic and sought-after skills

• Understanding of high-level synthesis

• Knowledge of state-of-the-art FPGA Design tools

used in the industry

• Knowledge & experiences of a modern FPGA

platform.

• A design portfolio that can be added to your resume.

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Course Descriptions• No required textbook. But, you need access to a

good VHDL reference book.• We will use the following book extensively.– FPGA Prototyping by VHDL Examples by Chu.– VHDL code in the book is available at here.

• Additional reading materials will be distributed.• Required background: CDA 3201/3201L • Attendance is required.

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Reference Books

available online from USF library

Part I Basic Digital Circuits- combinational- sequential- state machines

Part II EMBEDDED SOC I: VANILLA FPRO SYSTEM video

Part III EMBEDDED SOC II: BASIC I/O CORES

PART IV EMBEDDED SOC III: VIDEO CORES

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Reference Books

available at http://www.zynqbook.com8

Course Descriptions: Evaluation• Around 6 lab assignments: 60%– Each assignment includes design problems.– All assignments are individual unless specified otherwise.

• One final project: 40%• Final grading scale:

• Be Honest!– Collaborate, but do not copy each other’s work. – Anyone found cheating (all parties) will get FF.

CDA 4253 Fall 2015 Zheng

Evaluation

Assignments/Exam Grades Date

Lab assignments 50% n/aMidterm 20% Oct. 1st, 2015

Final Project 30% Dec. 4th, 2015

Note: The date for the midterm exam is tentative.

Final grading scale:

< 60% 60%� 69.99% 70%� 79.99% 80%� 89.99% � 90%F D C B A

• The instructor reserves the right to give +/- letter grades for the final grades.

• The above grading scale may be subject to minor change depending on the overall classperformance statistics.

• No incomplete (I) grades will be given.

Assignments

• All assignments are individual, and the final submission must be your own work.

• Late submissions will NOT be accepted unless approvals for extensions are obtainedfrom the instructor beforehand.

• Requests for re-grading must be submitted via email or in writing within one weekafter a graded assignment is returned.

• Additional specific requirements may be imposed for individual assignments. Readcarefully each assignment description when it is distributed.

Midterm Exam The midterm will be 75 minutes during a normal class meeting time. Itwill cover all topics discussed prior to the exam date.

• During the exam, all electronics must be turned o↵. Not chatting or discussion.

• Requests for re-grading must be submitted via email or in writing within one weeksince the graded exam is returned. Asking for a re-grading after the final grade isassigned because you need an additional 0.5 points to get a B or C should be avoided.

• A written request for re-scheduling the midterm exam must be approved by the in-structor beforehand. No make-up exam will be granted unless a true emergencyis involved with either a doctor note or a police report as proof. Your car broken downon your way to school or “I thought the exam would be tomorrow”, or similar excusesare not deemed as true emergencies.

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Office Hour• Instructor– Time: 2:30-4pm, Mon. & Wed, or by appointment.– Office: ENB 312– Email: haozheng@usf.edu– Office phone: 813-874-4757

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Course Communication• Canvas:– Announcements– Download assignment descriptions– Submit your solutions– Check your grades– Discussions where you can collaborate

• www.cse.usf.edu/~haozheng/teach/cda4253– Slides– Other course related documents

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Course Topics

• Digital Design with VHDL– Modeling/synthesis/simulation

• FPGA architectures– Commercial (Xilinx / Altera)

• Basic concepts of FPGA CAD algorithms• Basic idea of high-level synthesis• Heterogeneous computing• Case studies• Other selected topics if time permits

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Zedboard – Overview

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ZedBoard (Zynq™ Evaluation and Development) 

Configuration and Booting Guide

Version 1.1 August 2012

• More related information can be found at– Digilent’s website – Digilent Zedboard resource center– zedboard.org

Zedboard Information

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Vivado Design Suite• An environment where you create VHDL

descriptions of designs.• Offers tools for– simulation, synthesis, FPGA configuration

• The version for this course:Vivado HLx 2018.1 Webpack (free)

– All your work will be evaluated with this tool

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Vivado – Documents• Vivado Design Suite User Guide -- Getting Started – Master guide

• Vivado® Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)

• Vivado Design Suite User Guide: Using the Vivado IDE (UG893)

• More information at xilinx.com Vivado HLx page

• Tutorial: Getting Started with Vivado– https://reference.digilentinc.com/vivado/getting_started/start

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