Embed Size (px)
Citation preview
CENG3420Lab 3-1: LC-3b Datapath
Bei Yu
Department of Computer Science and EngineeringThe Chinese University of Hong Kong
Spring 2018
1 / 22
Overview
Introduction
Lab3-1 Assignment
Golden Results
2 / 22
Overview
Introduction
Lab3-1 Assignment
Golden Results
3 / 22
The Slides are self-contained? NO!
Do please refer to following document:I LC-3b-datapath.pdfI LC-3b-ISA.pdf
3 / 22
LC-3b Microarchitecture
4 / 22
Input of Control Structure (7 bits)
I R: indicate whether memory data is ready (System_Latches::READY)I BEN: indicate whether BR been taken (System_Latches::BEN)I IR[15:11]: current instruction (System_Latches::IR)
5 / 22
Output of Control Structure: (35 bits)
I 26 bits to control data pathI J[5:0], COND[1:0],IRD: generate address of control structure for next clock cycle
6 / 22
LC-3b Control Structure
7 / 22
LC-3b Control Structure
7 / 22
How’s Microsequencer Actually Working?
R
PC<−BaseR
To 18
12
To 18
To 18
RR
To 18
To 18
To 18
MDR<−SR[7:0]
MDR <− M
IR <− MDR
R
DR<−SR1+OP2*set CC
DR<−SR1&OP2*set CC
[BEN]
PC<−MDR
32
1
5
0
0
1To 18
To 18To 18
R R
[IR[15:12]]
28
30
R7<−PCMDR<−M[MAR]
set CC
BEN<−IR[11] & N + IR[10] & Z + IR[9] & P
9DR<−SR1 XOR OP2*
4
22
To 111011
JSR
JMP
BR
1010
To 10
21
200 1
LDB
MAR<−B+off6
set CC
To 18
MAR<−B+off6
DR<−MDRset CC
To 18
MDR<−M[MAR]
25
27
3762
STW STBLEASHF
TRAP
XOR
AND
ADD
RTI
To 8
set CC
14
LDW
MAR<−B+LSHF(off6,1) MAR<−B+LSHF(off6,1)
PC<−PC+LSHF(off9,1)
33
35
DR<−SHF(SR,A,D,amt4)
NOTESB+off6 : Base + SEXT[offset6]
R
MDR<−M[MAR[15:1]’0]
DR<−SEXT[BYTE.DATA]
R
29
18, 19
MDR<−SR
To 18
R R
M[MAR]<−MDR
16
23
R R
17
To 19
24
M[MAR]<−MDR**
MAR<−LSHF(ZEXT[IR[7:0]],1)
15To 18
PC+off9 : PC + SEXT[offset9]
MAR <− PCPC <− PC + 2
*OP2 may be SR2 or SEXT[imm5]** [15:8] or [7:0] depending on MAR[0]
set CCDR<−PC+LSHF(off9,1)
13
31
[IR[11]]
R7<−PCPC<−BaseR
PC<−PC+LSHF(off11,1)R7<−PC
8 / 22
How’s Control Store Actually Implemented?
Finite-State-Machine (FSM)I States 10, 11 are emptyI 6 bits input enoughI Per state, output 35 bits
Hard to implement
9 / 22
How’s Control Store Actually Implemented?
Finite-State-Machine (FSM)I States 10, 11 are emptyI 6 bits input enoughI Per state, output 35 bits
Hard to implement
9 / 22
Good News!
I Part of FSM has been providedI See file “ucode3”
10 / 22
Overview
Introduction
Lab3-1 Assignment
Golden Results
11 / 22
Operations in One Clock Cycle
In “lc3bsim3-1.c”:
void cycle(){
eval_micro_sequencer();cycle_memory();eval_bus_drivers();drive_bus();latch_datapath_values();
CURRENT_LATCHES = NEXT_LATCHES;
CYCLE_COUNT++;}
11 / 22
Lab3-1 Assignment
I Input: CURRENT_LATCHESI Output: NEXT_LATCHES.MICROINSTRUCTION
12 / 22
Lab3-1 Assignment Tips
13 / 22
Lab3-1 Assignment Tips (cont.)
Some functions may help:I GetCOND()
I GetIRD()
I GetJ()
I partVal()
14 / 22
Overview
Introduction
Lab3-1 Assignment
Golden Results
15 / 22
Assignment Package
I lc3bsim3-1.c, lc3bsim3-1.h: codes to work onI libems3-1.a: libraryI ucode3: FSMI Makefile
I bench: folder with benchmarks
Run the simulator:
1. make, then binary “lc3bsim3-1” is generated
2. ./lc3bsim3-1 ucode3 bench/toupper.cod
15 / 22
Golden Results – case toupper.cod
1. run 6
Simulating for 6 cycles...
MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 1MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 2MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 3MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 4MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0
16 / 22
Golden Results – case toupper.cod (cont.)
2. rdump
Current register/bus values :-------------------------------------Cycle Count : 6PC : 0x3002IR : 0x0000STATE_NUMBER : 0x0023
BUS : 0x0000MDR : 0xe00fMAR : 0x3000CCs: N = 0 Z = 1 P = 0Registers:0: 0x00001: 0x00002: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
17 / 22
Golden Results – case toupper.cod (cont.)
3. Go on run 1
Simulating for 1 cycles...
MemCycleCnt = 1MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0
18 / 22
Golden Results – case toupper.cod (cont.)
4. rdump
Current register/bus values :-------------------------------------Cycle Count : 7PC : 0x3002IR : 0xe00fSTATE_NUMBER : 0x0020
BUS : 0xe00fMDR : 0xe00fMAR : 0x3000CCs: N = 0 Z = 1 P = 0Registers:0: 0x00001: 0x00002: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
19 / 22
Golden Results – case toupper.cod (cont.)
5. Go on run 5
Simulating for 5 cycles...
MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 0, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 0MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0MemCycleCnt = 1MEM_EN = 1, R_W = 0, WE0 = 0, WE1 = 0
20 / 22
Golden Results – case toupper.cod (cont.)
6. rdump
Current register/bus values :-------------------------------------Cycle Count : 12PC : 0x3004IR : 0xe00fSTATE_NUMBER : 0x0021
BUS : 0x0000MDR : 0x0000MAR : 0x3002CCs: N = 0 Z = 1 P = 0Registers:0: 0x30201: 0x00002: 0x00003: 0x00004: 0x00005: 0x00006: 0x00007: 0x0000
21 / 22
