Central Hw

SURPASS hiE 9200 V4.3, operating documentation, issue 5

Central Hardware

Approval Date 2009-06-04

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The information in this document is subject to change without notice and describes only the product defined in the introduction of this documentation. This documentation is intended for the use of Nokia Siemens Networks customers only for the purposes of the agreement under which the document is submitted, and no part of it may be used, reproduced, modified or transmitted in any form or means without the prior written permission of Nokia Siemens Networks. The documentation has been prepared to be used by professional and properly trained personnel, and the customer assumes full responsibility when using it. Nokia Siemens Networks welcomes customer comments as part of the process of continuous development and improvement of the documentation.

The information or statements given in this documentation concerning the suitability, capacity, or performance of the mentioned hardware or software products are given "as is" and all liability arising in connection with such hardware or software products shall be defined conclusively and finally in a separate agreement between Nokia Siemens Networks and the customer. However, Nokia Siemens Networks has made all reasonable efforts to ensure that the instructions contained in the document are adequate and free of material errors and omissions. Nokia Siemens Networks will, if deemed necessary by Nokia Siemens Networks, explain issues which may not be covered by the document.

Nokia Siemens Networks will correct errors in this documentation as soon as possible. IN NO EVENT WILL Nokia Siemens Networks BE LIABLE FOR ERRORS IN THIS DOCUMENTA-TION OR FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO SPECIAL, DIRECT, INDI-RECT, INCIDENTAL OR CONSEQUENTIAL OR ANY LOSSES, SUCH AS BUT NOT LIMITED TO LOSS OF PROFIT, REVENUE, BUSINESS INTERRUPTION, BUSINESS OPPORTUNITY OR DATA,THAT MAY ARISE FROM THE USE OF THIS DOCUMENT OR THE INFORMATION IN IT.

This documentation and the product it describes are considered protected by copyrights and other intellectual property rights according to the applicable laws.

The wave logo is a trademark of Nokia Siemens Networks Oy. Nokia is a registered trademark of Nokia Corporation. Siemens is a registered trademark of Siemens AG.

Other product names mentioned in this document may be trademarks of their respective owners, and they are mentioned for identification purposes only.

Copyright Nokia Siemens Networks 2007. All rights reserved

f Important Notice on Product Safety Elevated voltages are inevitably present at specific points in this electrical equipment. Some of the parts may also have elevated operating temperatures.

Non-observance of these conditions and the safety instructions can result in personal injury or in property damage.

Therefore, only trained and qualified personnel may install and maintain the system.

The system complies with the standard EN 60950 / IEC 60950. All equipment connected has to comply with the applicable safety standards.

The same text in German:

Wichtiger Hinweis zur Produktsicherheit

In elektrischen Anlagen stehen zwangslufig bestimmte Teile der Gerte unter Span-nung. Einige Teile knnen auch eine hohe Betriebstemperatur aufweisen.

Eine Nichtbeachtung dieser Situation und der Warnungshinweise kann zu Krperverlet-zungen und Sachschden fhren.

Deshalb wird vorausgesetzt, dass nur geschultes und qualifiziertes Personal die Anlagen installiert und wartet.

Das System entspricht den Anforderungen der EN 60950 / IEC 60950. Angeschlossene Gerte mssen die zutreffenden Sicherheitsbestimmungen erfllen.

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Table of ContentsThis document has 28 pages.

1 Call & Feature Control - Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.3 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Coordination Processor 113E (CP113E) . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.3 Mechanical design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.4 Technical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Central Clock Generator, Type E (CCGE) . . . . . . . . . . . . . . . . . . . . . . . . . 163.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.3 Mechanical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.4 Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 Message Buffer D (MBD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.3 Mechanical design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.4 Technical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5 Media Control Platform (MCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255.3 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265.4 Technical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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Central Hardware Call & Feature Control - Overview

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1 Call & Feature Control - OverviewOverviewThe call & feature control handles call control and the broad spectrum of features offered to the SURPASS network users.

User are connected via IP interfaces (H.323, SIP), or trunk gateways (MGCP / MEGACO controlled), or customer premises gateways (CPG, MGCP controlled). This involves the processing of call related signaling, the call control itself, the process-ing of voice related services, the call set-up including number translation / call routing and traffic management, and call related management aspects such as collection of accounting data.

The SURPASS hiE 9200 can operate as completely TDM-less call & feature control or in a mixed configuration containing both IP and time division multiplex (TDM) compo-nents.

1.1 FunctionsThe SURPASS hiE 9200 with its rich voice feature set provides the ultimate platform for next generation network (NGN) services by offering all features of traditional voice networks and more, such as: system features accounting multi-operator environment features and network control functions subscriber features intelligent network (IN) services The call & feature control communicates with the SS7 Control for SS7 signaling and control, the media control platform (MCP) and with the packet manager (PM) for media gateway signaling control and IP signaling and control.

1.2 StructureThe SURPASS hiE 9200 can operate as completely TDM-less call & feature control or in a mixed configuration containing both IP and time division multiplex (TDM) compo-nents.

The call & feature control consists of: Coordination processor 113E (CP113E) Central clock generator, type E (CCGE) Message buffer D (MBD)
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Call & Feature Control - Overview

Media control platform (MCP)

Coordination processor 113E (CP113E)The core of the call & feature control is the fully redundant coordinations processor 113E (CP113E) with a high performance call processing block containing a pair of basis pro-cessors (BAP 0, BAP 1) and up to 10 additional call processors (CAP 1...9).

The BAP manages the system, executes operation, administration and maintenance tasks, keeps and distributes the database, communicates with the NetManager. The CAP handle the call processing tasks (CPT).

For more information please refer to: Coordination processor 113E (CP113E).

Central clock generator, type E (CCGE)The central clock generator, type E (CCGE) supplies the SURPASS hiE 9200 with a highly accurate, stable clock, which is required for the information transfer within the switching network D (SND) and the information transport to the MCP.

For more information please refer to: Central clock generator, type E (CCGE).

Message buffer D (MBD)The message buffer D (MBD) controls the exchange of messages between the: CP113E and the media control platform (MCP) CP113E and the SND MBD and MCPFor more information please refer to: Message buffer D (MBD).

Media control platform (MCP)A scalable array of media control Platform (MCP) provides the call and feature process-ing and signaling interworking for the control of MGCP or H.248/MEGACO controlled media gateways, the intersoftswitch communication via BICC*, SIP-NNI or SIP-T, and IP subscribers connected via H.323 and MGCP (H.323 SW Clients, H.323 IP Phones, H.323 gateways, MGCP CPG / IAD). It handles the whole range of signaling protocols for voice traffic like ISDN user part (ISUP), transaction capabilities application part (TCAP), IN application part (INAP). universal call control interface.

Call & Feature Control

to PCU

to SS7 Control and

OAM&P Agent

MCP

CP113E

CCGE

to switching network (SN)

MCPMBD

MCP
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For more information please refer to: Media control platform (MCP).

1.3 SoftwareThe call & feature control software is based on a modular design. This means it can easily be adapted to meet the specific needs of each provider. It also means that new features and functions can be easily incorporated.

The coordination processor 113E (CP113E) software runs on the distributed multi-pro-cessor hardware platform of the CP113E. A multi-processor and multi process operating system forms the basic of the CP113E software. The important part of this operating system are the input/output control and the time management.

The large volume of different data for the media gateway controller are organized in the real time database. The administration runs on top of the operating system.

The call & feature processing is responsible for the call set-up and the related PSTN fea-tures. This software is part of the CP113E software as well as of the MCP software.
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Coordination Processor 113E (CP113E)

2 Coordination Processor 113E (CP113E)OverviewThe coordination processor 113E (CP113E) with up to 2 base processors (BAP) and up to 10 additional call processors (CAP) forms the core of the IP-TDM combined switch.

Benefits

improved performance (compared with CP113C/CR):call processors (CAP) = performance improved by factor 5 base processors (BAP) = performance improved by factor 3.5 ATM bridge processor (AMP) = performance improved by factor 1.5 input/output control (IOC) = performance improved by factor 2

traffic handling capacity of more than 16 million busy hour call attempts (BHCA) can be adapted to network nodes of any size smaller footprint reduced power consumption

2.1 FunctionsThe CP113E is responsible for the following functional complexes in the IP-TDM combined switch: Call processing functions Safeguarding functions Operation and maintenance functions

Call processing functionsThe main call processing functions of the CP113E are: digit translation routing zoning path selection through the switching network (SN) call charge registration traffic data administration network managementWhen a connection is being set up, address information is transfered from the line/trunk group (LTG) to the CP113E. The CP113E performs address translation on these infor-mations. The result of address translation is the requirred destination. In the case of an external connection, the CP113E then uses the routing function to find a free trunk leading to the destination.

Using the zoning function the CP113E identifies the zone where the destination is located. In the LTG the zoning result is used to determine the valid tariff for charge reg-istration.

The calling and called ends of a connection are interconnected via the switching network (SN). The CP determines the path through the switching network by means of path selection. For this purpose the idle/busy status of the switching network (SN) is stored in the CP database. The CP sends the path data to the switch group control with a command via the input/output processor for message buffer (IOP:MB).
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Central Hardware Coordination Processor 113E (CP113E)

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Call charge registration functions are split between the LTG and the CP113E. During a call, the LTGP adds the meter pulses. At the end of a call, or at predefined intervals in the case of lengthy calls, the meter pulses counted in the LTGP are passed to the CP113E. The CP113E stores the meter pulse count in the call charge memory assigned to the calling subscriber. When requested by an operator, the CP113E makes the charge data available for further processing.

Traffic data administration comprises traffic measurement, traffic monitoring, sub-scriber observation and traffic structure measurement tasks. The traffic data is important for the operating companys traffic engineering and forecasting activities. The CP113E contains a number of traffic data administration programs. These programs collect and process traffic data from all parts of an IP-TDM combined switch and the trunk groups.

The task of traffic management is to protect the network and the media gateways against overload and, if an overload situation does arise, to take appropriate action (traffic restrictions) to prevent the network from breaking down. In addition, network management provides the means to distribute traffic flexibly over the available routes and trunk groups in accordance with individual criteria.

Safeguarding functionsThe main safeguarding functions of the CP113E are as follows: self-monitoring error detection error handlingThe safeguarding functions deal with errors affecting the CP113E as well as errors in the other switch subsystems. As well as responding to errors, the safeguarding function in the CP113E also starts test and diagnostic programs.

The functions of the safeguarding programs are: to choose and establish a functioning system configuration at power-up or after

recovery to record and process safeguarding messages from the periphery and from the

CP113E processes to control the execution of regular tests to analyze alarm messages from the supervisory circuits in the CP113E to collect and save error symptoms to analyze errors and locate faults to restore an operable system configuration in the event of hardware faults to take adequate recovery actions to eliminate the effect of software errors which the

user programs are unable to neutralize themselves

Recovery in the IP-TDM combined switch is spread over several escalation levels. The main types of recovery are: installation recovery central recovery peripheral recovery

Operation and maintenance functionsThe principal operation and maintenance functions of the CP113E are as follows: Input and output to/from external memory Communication with the NetManager

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The NetManager is the point of access for all operation, administration and maintenance activities (OA&M). The NetManager is connected to the CP113E via data links, directly via input/output processor for serial data communication devices BX.25/X.25 protocol (IOP:SCDP) or can be reached via the ethernet interfaces on the SRP.

Dialog between the operator and the CP113E is conducted using the standardized man-machine language (MML). The CP113E controls the dialog with the NetManager and checks the validity of the entered commands.

2.2 StructureThe CP113E hardware consists of the following functional units: Basic processor (BAP) Call processor (CAP) Input/output control (IOC) ATM bridge processor (AMP) Common memory (CMY) Input/output processor (IOP)

The base processor (BAP), the call processor (CAP), the input/output controls (IOC) and the ATM bridge processor (AMP) are based on the same hardware: Processor module PEXEDepending on whether the processor module PEXE is used as BAP, CAP, IOC or AMP, specific hardware functions are activated according to the mounting location. With the memory submodule the memory can be configured to the requirements of the individual processor.

The processors are connected to the common memory (CMY) via 2 x 600 Mbit/s serial high-speed links.

The following functional units of the CP113E are redundant:

Basic processor (BAP)The basic processor (BAP) contains a duplicated base processor (BP). One of the two BAPs operates as master (BAPM), the other as spare (BAPS). The BAPM processes operation and maintenance tasks as well as some of the call-processing tasks. The

IOC 0

IOP 15

CMY1

IOP 1

IOP 15

IOP 1

CMY0

CAP 10

to SSNC

AMPn

BAP 0

BAP 1

IOC n

AMP 0

CAP 1

from/to e.g. SND over MBD
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BAPs processes call-processing tasks only. The two BAPs operate in task and load sharing mode. If the BAPM fails, the BAPS takes over the tasks of the BAPM.

The base processor (BAP) are realized by the program execution part, module BAP (PEXE:BAP).

Call processor (CAP)The call processor (CAP) handle call processing tasks only. They work in load sharing mode. Together with the BAPS and BAPM, the CAPs form a pool redundancy. As a result, even if one processor fails (BAP or CAP), the CP113E can continue to handle the full nominal load (n+1 redundancy).

The call processor (CAP) are realized by the program execution part, module CAP (PEXE:CAP).

Input/output control (IOC)The input/output controls (IOC) contain software for communication with the call pro-cessing, operation and maintenance, and data communication peripheries.

The IOCs are duplicated. If one IOC fails, the other IOC carries out the tasks of its partner unit.

The IOCs constitute the interface between the 2 x 600 Mbit/s high-speed serial links (HSSL) and the input/output processors (IOP).

The input/output controls (IOC) are realized by the program execution part, module IOC (PEXE:IOC).

ATM bridge processor (AMP)The ATM bridge processor (AMP) is the interface between the SSNC and the CP113E.

The AMP contains the software for communication with the SSNC. It converts packet-oriented data streams from the ATM area to the CP113E communication mode and vice versa. The components in the AMP are duplicated.

The AMPs are always operated in pairs in the CP113E. An AMP pair operates in work-ing/spare mode, i.e. both AMPs receive the same messages at the same time. However, only the active AMP sends messages.

The ATM bridge processor (AMP) are realized by the program execution part, module AMP (PEXE:AMP).

Common memory (CMY)The common memory (CMY) is the central memory medium for the connected BAPs, CAPs, IOCs, and AMPs.

The CMY contains, among other things, the common database for all processors, the input and output lists for the input/output processors for message buffer (IOP:MB) and the communication areas for the input/output processors (IOP) to the OA&M periphery.

The CMY is duplicated. Both CMYs (CMY0 and CMY1) can be reached by all proces-sors and IOCs as well as by the IOPs. In normal operation the two CMYs perform all read and write cycles synchronously. However, the two CMYs can also be operated sep-arately (splitting mode).

The common memory (CMY) consists of the common memory module (CMYE).

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Input/output processor (IOP)The IOPs control the exchange of data between the connected call processing and the operation, administration and maintenance periphery in the network node. Various types of input/output processors (IOP) link the CP113E with the other subsystems and func-tional units of the network node, the external mass memories, NetManager and the pro-cessing center (over data links).

The IOPs are connected to the IOC via the bus system for input/output control (BIOC). Up to 16 IOPs can be connected per IOC.

The following types of IOP are employed in the CP113E: Input/output processor for message buffer (IOP:MB)

The IOP:MB forms the interface between the CP113E and the other subsystems and functional units in the network node. For security, all subsystems and functional units are served by two IOP:MBs. If one of the two IOP:MBs fails, the other handles all data transfers alone.

Input/output processor unified for OA&M devices (IOP:UNI)The IOP:UNI allows the following devices and lines to be connected: magnetic disk device (MDD) magneto-optical disk device (MOD) and optionally one management system and two data links or three data linksThe MOD is used as a memory medium in addition to the magnetic disk in order to improve operational processes, and particularly to speed up recovery and backup times. The MOD can be connected together with the MDD to the same small computer system interface (SCSI) bus and is created using MML commands.

Input/output processor for serial data communication devices BX.25/X.25-protocol (IOP:SCDP)The IOP:SCDP consists of: Line control unit, module B (LCUB)

The LCUB is connected to the bus system for input/output control (BIOC) and handles control functions in the IOP:SCDP.

Line adaptation unit, module B (LAUB) The LAUB module provides the BX.25/X.25 interfaces of the IOP:SCDP and is controlled by the module LCUB.A line adaptation unit, module B (LAUB), has two interfaces with BX.25 or X.25 protocol for connection of data terminal equipment and data transmission equip-ment. X25LINKs (data lines) are used for connection. The cable connectors of the X25LINKs (data lines) must be suitable for one of the (physically) possible interfaces for X.21, V.24, V.35 or V.36.

Input/output processor for time and alarms (IOP:TA)The IOP:TA contains the hardware clock (clock, operation and clock, display) for the CP113E and the interfaces for connecting external alarms.

Input/output processor for authentication center (IOP:AUC)The IOP:AUC is only employed in the application where the CP113E is used in the authentication center of a mobile communication network.

Operation, administration and maintenance peripheryThe redundant OA&M periphery units are always connected to two different IOCs. If one IOC or the associated input/output processor (IOP) fails, inputs and outputs to/from the redundant OA&M unit are carried out via the other IOC in the pair. The bus systems to

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the call-processing periphery are cross-connected after the input/output processor for message buffer (IOP:MB).

InterfacesThe CP113E is connected via the input/output processors (IOP) to the message buffer D (MBD) and to the OA&M equipment of the network node. There is a direct interface to the signaling system network control (SSNC) via the ATM bridge processor (AMP). The asynchronous transfer mode (ATM) is used at this interface. The ATM interface to the SSNC reduces the CP load when distributing messages in the network node.

AvailabilityA wide range of safeguarding measures in hardware and software ensure the very high availability of the CP113E. The mean time between two total failures (MTBF) is more than 500 years.

Total failure is defined as: failure of both BAPs or failure of both CMYs or failure of all IOC pairs.The simultaneous failure of two or more processors handling call-processing tasks would only reduce the call handling capacity and, depending on the current load situa-tion, result in activation of overload control.

Capacity stagesIn the basic configuration the CP113E has only two base processors (BAP) and two input/output controls (IOC). Up to sixteen input/output processors (IOP) can be con-nected to each IOC. For an expansion, two more input/output controls (IOC) with addi-tional IOP can be added. In its maximum configuration the CP113E is equipped with 16 processors: two BAPs, four IOCs and 10 call processors (CAP). Depending on the system configuration, up to four ATM bridge processors (AMP) can also be used as an alternative to CAP.

In future configurations it will be possible to expand the CP113E by eight additional CAPs in order to have a total of 24 processors. Of the eight additional processors, four can also be used as AMPs.

2.3 Mechanical designThe CP113E is housed in one rack. For more informations, please refer to: Construction manual.

2.4 Technical dataTraffic-handling capacity

Depending on features implemented, traffic distribution and call mix

over 12 MBHCA (10 CAP)

over 16 MBHCA (16 CAP)

PEXE

Lock rate 50/75 MHz

414 MHz (AMP)

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Data width

- addresses

- data

32 bits + 8 bits ECC

32 bits + 8 bits ECC

Local memory

- capacity 128 Mbyte

Number of BAPs min. 2

max. 2

Number of CAPs min. 0

max. 10 (level 1)

max. 16 (level 2)

Number of AMPs min. 0

max. 4 (level 1)

max. 8 (level 2)

Number of IOCs min. 2

max. 4

Number of connectable IOPs 16 or 32 (with 2 IOCs)

48 (with 4 IOCs)

Power supply - 5 V, - 3.3 V, - 2.5 V

CMYE

Clock rate 75 MHz

Data width

- addresses

- data

32 bits, 8 ECC bits

32 bits, 8 ECC bits

Capacity max. capacity stages:

- 4 x 128 Mbyte

- 8 x 128 Mbyte

- 4 x 256 Mbyte

- 8 x 256 Mbyte

Power supply - 2.5 V, - 3.3 V

IOP:MB

Data width

- addresses

- data

32 bits

32 bits

Clock rate 20/40 MHz

Ports 1 (for MBG or CCG or Alarm Surveillance)

Local memory 128 kbyte

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IOP:TA

Time base 16,384 MHz (synchronized by CCG)

Clock rate 16 MHz

Alarm interfaces to 5 racks (maximum)

Alarm lines 8 per interface

IOP:UNI

Clock rate 32/16 MHz

Ports- MDD

- MOD

optionally

- PC/data links or

- data links

1

1

1/2

3

IOP:SCDP

Clock rate 16 MHz or 10 MHz

Ports 2 (X.21, V.24, V.35, V.36)

IOP:AUC

Clock rate 16 MHz

Ports 1 (V.24, for connection of a chip-card reader)

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Central Clock Generator, Type E (CCGE)

3 Central Clock Generator, Type E (CCGE)OverviewIn order to switch and transmit digital information, it is essential that all equipment involved in the process operates in synchronism. This means that every SURPASS hiE 9200 in a digital network must be supplied with timing signals that are extremely reliable, accurate and constant.

The central clock generator, type E (CCGE) supplies the IP-TDM combined switch with a highly accurate, stable clock.

The CCGE locks onto an external reference. The clock is available even if all reference signals fail.

Benifits

four reference inputs per redundant unit, capable of processing different signals simultaneous monitoring of all reference inputs flexible expansion options to up to 2 x136 T4 outputs filters to remove jitter and wander on the transmission links optimized signaling to deal with deterioration of quality at the T4 outputs rapid recovery after a power failure automatic active/standby switchover after signal failure in the redundant unit

3.1 FunctionsThe CCGE is installed in the IP-TDM combined switch in redundant pairs, to minimize the risk of failure. By installing a redundant pair of identically structured units (CCGE0 and CCGE1), it is ensured that the overall functionality of the CCGE is maintained if a hardware failure should occur in one of the units.

The CCGE supplies the following subsystems directly: Coordination processor 113E (CP113E) SS7 control Message buffer D (MBD) Furthermore the clock of the CCGE out external consumer available, e.g. synchronous Digital hierarchy (SDH).

The following subsystems are supplied via a clock provided by the MBD, which is syn-chronized with the CCGE: Switching network (SN) Line/trunk groups (LTG) Remote switching units (RSU) Digital line units (DLU) Via the four reference inputs the CCGE can be supplied with various clock signals. The sources of the clocks can be inside or outside a IP-TDM combined switch.

The following external reference sources can be connected: LTG output 2048 kHz or 1544 kHz (corresponding to E1 or T1) T4 output of a synchronous equipment clock (SEC) in a synchronous digital hierar-

chy (SDH) equipment 2048 kHz

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Central Hardware Central Clock Generator, Type E (CCGE)

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T3 signal, e.g. cesium reference (G.811), rubidium standard or a synchronization supply unit (SSU, G.812) 1000/2048/5000/10000 kHz

DS1/BITS signals with 1544 kbit/s, B8ZS-coded data signal (T1) or framed all ones network clock supply

In addition, the CCGE has up to 136 extension outputs (T4), to which clock users in other systems can be connected. These users may be SDH line equipment, mobile switching network node or other facilities belonging to the operator that are located in the same building as the network note.

Each CCGE unit provides 16 8-kHz clock outputs. The frame structure in the entire IP-TDM combined switch is kept in strict synchronism with this clock, in order to guarantee that the functions within the exchange are performed synchronously and without frame slip. The outputs from the two CCGE units in the redundant pair are active alternately and are phase-synchronized.

Each CCGE unit has two interfaces to the input/output processor for message buffer (IOP:MB). The redundant pair of CCGE units has four IOP:MB interfaces. This allows crossover connections to be made between the two redundant CP113E units and the two redundant CCGE units.

All four IOP interfaces in the CCGE are identical. The interface is capable of transmitting data at up to 500 kbyte/s.

For the clock generation under normal conditions, the oscillators in the two units of the redundant pair, CCGE0 and CCGE1, are fed by different references. If all external ref-erences connected to CCGE0 should fail, the unit that is still receiving external refer-ences (CCGE1) supplies CCGE0 via the internal crossover connection, assuming that the partner unit is still receiving a good reference.

CCGE1 is now acting as the "master" unit with respect to CCGE0. If, subsequently, all references connected to the master unit (CCGE1) should also fail, the master/slave

IOC (8 kHz)

Transmission network

network clock out-puts (8 kHz) MBD CP113E SSNC

CP113E interface

Service interface

SSNC

Reference inputs External references:PRCSDH (T4)LTG (E1) LTG (T1)T3 signalsDS1/BITS

Extension outputsT4 clock (2048 kHz)

CCGE
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configuration is maintained, in order to keep the two halves of the CCGE in synchronism with each other.

Under normal operating conditions, where different reference signals are being used, the phase of the oscillators is not constant. In order to simplify switchover, the 8 kHz cold-standby output signals for the internal clock users CP113E, MBD and SSNC are synchronized independently of the oscillators in the two units.

In each case, the output signal from the active unit is transferred to the standby unit via a crossover connection. The phase synchronization circuit there determines the phase correction required for the local oscillator at that moment. As a result, the output timing signals present at the output of the CCGE units are phase-synchronized when the units are activated after the switchover from standby to active.

In contrast to the 8-kHz cold standby output signals for the internal clock users, the 2048-kHz extension outputs (T4 clock) for external clock users, which also include the SSNC, are of the hot standby type. It is not necessary for these redundant clock outputs to be kept strictly in synchronism with each other.

The CCGE evaluates its reference clock inputs and selects one of them for clock syn-chronization, in accordance with its setting. As long as there is a valid input signal, the frequency of the delivered timing signals exactly matches the frequency of the selected reference signal. This is normally linked - in some cases via another IP-TDM combined switch or via the transport system (SDH) - to a highly accurate cesium frequency standard (PRC, primary reference clock). Consequently, the frequency delivered by the CCGE corresponds to that of a PRC.

The CCGE continuously evaluates all references offered to its inputs. If the reference used for synchronization is disturbed or if it fails completely, the CCGE switches over to a different reference in accordance with a configurable priority list. If only the redundant partner CCGE is receiving good reference signals, it can also be used for synchroniza-tion (master/slave operation).

CCGE1

CCGE0

Oscil-lator

T4 output

CCGED

CP113E MBD SSNC

CP113E MBD SSNC

CCGEDM U X

Reference 0 Reference 1 Reference 2 Reference 3

T4 output

Reference 0Reference 1Reference 2 Reference 3

phase- locked

M U X

Oscil-lator

phase- locked

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Central Hardware Central Clock Generator, Type E (CCGE)

Id:0900d80580090126

Each CCGE unit can be connected to up to four different reference sources. The failure of one reference leads to automatic switchover to another reference that is still intact. If all references connected to a CCGE unit should fail, the CCGE unit synchronizes itself to the redundant CCGE unit. The CCGE units are capable of bridging the failure of all references by means of holdover; at the same time, a master/slave configuration is set, i.e. one of the CCGEs synchronizes itself to the other.

Every clock user within the IP-TDM combined switch (MB, CP113E, SSNC) that receives a reference clock from the CCGE clock distribution is supplied with two equal timing signals, one from CCGE0 and one from CCGE1 (crossover connection).

The redundancy of these outputs is of the cold standby type, in other words, only one of the two outputs is active (either that of CCGE0 or that of CCGE1), and the other output does not deliver any timing signals (standby).

A mechanism is provided to ensure that the phase of the clock remains unchanged during the switchover from standby to active. As a result, clock users within the network node can switch between the two redundant clocks in response to a failure without having to make any adjustments to the phase alignment.

However, the method of cold standby redundancy employed here does require that the clock users report any clock failures immediately to the CP113E, which then initiates the switchover from the active to the standby CCGE.

Every clock receiver outside the network node (e.g. plesiochronous digital hierarchy (PDH) or synchronous digital hierarchy (SDH) transport system) which obtains a refer-ence clock from the CCGE is also supplied with redundant clocks, but these are of the hot standby type, i.e. both outputs are always active. If these outputs fail, the external clock user itself ensures that switchover of the reference clock is performed smoothly.

If, instead of a SSNC, an SSNC is used for signaling, it is also synchronized via the hot standby output signals (T4 output) from the CCGE.

A CCGED/CCGES self-supervision facility detects all hardware faults (except clock outputs) with very high reliability. The outputs of the CCGE are not monitored individu-ally. Errors at the clock outputs of the CCGE are detected by the connected clock users. In most cases, it is possible to diagnose the error down to module level. This can be checked by reading out internal registers.

If the appropriate control signal is not being received from the active redundant partner unit, switchover from standby to active is executed for the internal network outputs without any intervention by the CP113E.

3.2 StructureThe CCGE is composed of the following modules: Synchronization module (CCGES) Clock distribution module (CCGED)The synchronization module (CCGES) is the control and synchronization module of the CCGE. It performs the following tasks of the CCGE: evaluating and selecting references sources generating stabilized clock signals in accordance with G.812 distributing timing signals inside and outside the network node system control interfaces to the CP113E and the redundant unit

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The CCGES provides 16 network node clock outputs (8 kHz) for MBD and SSNC and two further clock outputs for the CP113E.

The clock distribution module (CCGED) provides 32 extension outputs (T4 clock outputs) operating at 2.048 MHz in four groups of eight outputs each for the external users. Clock users can be, for example, SDH line equipment or mobile switching network node.

3.3 Mechanical DesignThe rack for line/trunk group N (R:LTGN; example) can hold up one module frame for central clock generator, type E (F:CCGE) and two module frame for MBD (F:MBD).

For more informations, please refer to: Construction manual.

3.4 Technical DataExtension outputs (T4)

Frequency; nominal value 2,048 MHz

IP-TDM combined switch clock outputs

Frequency; nominal value 8,000 kHz

Reference from LTG output

Frequency; nominal value 2,048 MHz or

1,544 MHz

T3 parameters

Frequency; nominal value 1,000 MHz or

1,544 MHz or

2,048 MHz or

5,000 MHz or

10 MHz Input sensitivity and return loss val ues may deteriorate by up to 6 dB

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Central Hardware Message Buffer D (MBD)

Id:0900d8058051c7eb

4 Message Buffer D (MBD)OverviewFrom an architectural point of view the message buffer D (MBD) acts as a gateway for messages within and between the different networks being connected.

The MBD interprets the destination address supplied with each message from the trans-mitting subsystem, and transfers these messages to the appropriate receiving subsys-tem.

Benefits

MBDE board connects IBUS with 4 * fast Ethernet (10/100BaseT) external interface ATM interface to the SSNC to reduce the CP113E load when distributing messages

in the hiE 9200 higher performance of the message channel Compact design with reduced Reduction of the load on the CP during message distribution in the network node Option of straightforward expansion to a maximum of 2016 LTG connections Maximum reliability due to redundancy

4.1 FunctionsThe MBD interprets the destination address supplied with each message from the trans-mitting subsystem, and transfers these messages to the appropriate receiving subsys-tem.

The local area network (LAN) is connected via a MBD Ethernet board.

The Ethernet module (MBDE) builds the bridge between the IP-TDM combined switch system and the SURPASS Evolution.

MBD is equipped with an Asynchronous Transfer Mode interface (ATM interface) for the signaling system network control (SSNC) and utilizes the resultant benefits of increased speed.

The MBD offers interfaces to switching network D (SND) coordination processor 113E (CP113E) local area network (LAN) asynchronous transfer mode (ATM) network central clock generator, type E (CCGE)

4.2 StructureThe MBD incorporates the following modules: MBD Ethernet module (MBDE) Interface module to the ATM (MBDA) Message buffer controller (MBDC) Clock generator module (MBDCG) Interface module to the HDLC (MBDH)

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Message Buffer D (MBD)

All the modules are connected to the internal bus by means of high-speed serial inter-faces. The internal bus operates in synchronism with the MBD system clock. The link between a module and the redundant module in the second half of the MBD is also an internal bus link.

Each MBDE Ethernet module (MBDE) carries 4 Ethernet interfaces. The MBDE connects MBD internal bus (IBUS) with 4* fast Ethernet (10/100BaseT) external inter-face anticipated throughput approx. 40000 message signal units (MSU) per second.

The LAN-Ethernet interface between MBD and IP network will be build up by hubs or switch with 100BaseT interface. These hubs or switch will concentrate the 100BaseT interface from the packet control unit (PCU) the media control platform (MCP) and SURPASS hiG Media gateway for access towards the MBDE. The stream control trans-mission protocol (SCTP) is used.

The MBDE are plugged into the slots which are not used by MBDH modules.

The interface module to the ATM (MBDA) connects the MBD via optical links to the asynchronous transfer mode multiplexer (AMX) of the SS7 Control.

One MBDA supports a maximum of four fiber optic transceiver, type X (FOTX) interface modules. In this way, two redundant ATM connections can be set up.

Each module is capable of processing 24,000 SS7 message signal units (MSU) per second. A maximum of five MBDA can be deployed. The maximum configuration for transporting data is 120,000 MSU/s.

Messages arriving via the ATM (MBDA) interface from the SSNC and destined for the LTG are routed directly via the Ethernet interface (MBDE) to the LTGs. The ATM inter-faces operate in active/standby mode. In the event of failure of one ATM interface, the tasks are performed by the standby interface. The data rate of the ATM interface is 200 Mbit/s for each connection.

SND 0

MBD0

MCP / PCU/ OSP/hiG 1600 V2

MBDA 0...4

MBDC MBDCG

CP113E(IOP:MB)

CCGE 0/1

Internal bus (IBUS)

SSNC (AMX)LTG

MBDH 0...7

MBDA 0...4

MBDC MBDCG

SND 1CP113E(IOP:MB)

CCGE 0/1

SSNC (AMX)

LTG

MBD1

MBDH 0...7

MBDE 0...7

MBDE 0...7

MCP / PCU/ OSP/hiG 1600 V2

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The message buffer controller (MBDC) interface is the link between the MBD and the CP113E. Via the CP113E interface the MBD transmits messages to the CP113E and receives commands from the CP113E. The MBDC also takes over control during startup of the MBD. The MDBC transmits reset commands via the reset bus to the individual units. The MBDC collects the acknowledgments from the addressed units and relays them as a collective acknowledgment to the CP113E.

The clock generator module (MBDCG) forms part of the synchronous clock distribu-tion of the hiE 9200 and, at the same time, the clock generator for the MBD. In addition, it performs the function of a multiplexer/demultiplexer for the interface between the MBD and the SND.

The MBD is synchronized by the CCGE. Each of both MBD has two clock inputs, which are connected to CCGE0 and CCGE1.

The interface module to the HDLC (MBDH) provides the interface via the SND to the line/trunk group (LTG).

The 64 kbit/s interface between the MBD and the SND is used to control the SND via the CP113E and for clock distribution to the SND and to the other subsystems.

A maximum of 252 LTGs can be linked to an individual HDLC interface module. Each module carries 4 PCM interfaces and 6 SGC interfaces.

The interface between the MBD and the LTG via the SND is an 8 Mbit/s interface with 128 channels of 64 kbit/s each.

4.3 Mechanical designThe MBD frame (F:MBD) can hold up to eight MBDH modules (MBDH0 to MBDH7) or eight MBDE modules (MBDE0 to MBDE7), or a combination of the two modules.

In the MBD frame the MBD Ethernet modules (MBDE) are plugged into the free slots of the HDLC interface module (MBDH). The MBD frame also contains up to five MBDA modules, an MBDC module and an MBDCG module.

For more informations, please refer to: Construction manual.

4.4 Technical dataGeneral

Minimum expansion stage MBD for up to 252 LTGs

Maximum expansion stage MBD for up to 2016 LTGs total MBD for up to 504 LTGs in SURPASS hiG Media gateway for access

IOP:MB interface Expandable according to the specified design

AMXE interface Expandable according to the specified design

Clock 49.152 MHz

Internal data traffic between all the MBD modules of an MBD

240 Mbit/s, 460,000 messages/s

External data traffic between the two redundant MBDs

80 Mbit/s, 140,000 messages/s
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Message Buffer D (MBD)

Module MBDE

interfaces four 10/100BaseT (Ethernet)

max. number of modules 8

specific functions interface to LAN via Ethernet

Power supply Exchange voltage -60 V (-48 to -75 V) Operating voltage 3.3 V, 2.5 V, 1.8 V

Module MBDA

interfaces four 207 Mbit/s ATM channels via 4 FOTX interface modules to the AMX


Power supply Exchange voltage -60 V (-48 to -75 V) Operating voltage 3.3 V, 5 V

Module MBDC

Interface to an IOP:MB via 9 bidirectional and 10 unidirec-tional channels

Connection options 7 IOP:MB15 internal bus connections

IOP interface handshake procedure Transmission rate: max. 500 kbyte/s byte-parallel

internal bus serial point-to-point connection Transmission rate: max. 50 Mbit/s

Power supply Exchange voltage -60 V (-48 to -75V) Operating voltage 3.3 V

Module MBDCG

Interface to the CCGE 2 reference inputs

Permissible frequency at the reference input (CCG0 or CCG1)

8 kHz

Network node system clock 8.192 MHz2,000 kHz frame mark bit

Power supply Exchange voltage -60 V (-48 to -75 V) Operating voltage 3.3 V, 5 V

Module MBDH

Interfaces to the LTG via four 8-Mbit/s Channels (per 63 LTGs), to the SGC via three 128 kbit/s Channels (128 LTGs)


Power supply Exchange voltage -60 V (-48 to -75 V) Operating voltage 3.3 V

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Central Hardware Media Control Platform (MCP)

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5 Media Control Platform (MCP)OverviewA scalable array of media control platform (MCP) provides the call and feature pro-cessing and signaling interworking for the control of MGCP or H.248 / MEGACO con-trolled media gateways, the intersoftswitch communication via BICC*, SIP-NNI or SIP-T, and IP subscribers connected via H.323 and MGCP (H.323 SW Clients, H.323 IP Phones, H.323 CPE, MGCP CPG/IAD). It handles the whole range of signaling proto-cols for voice traffic like ISDN user part (ISUP), transaction capabilities application part (TCAP), IN application part (INAP).

5.1 FunctionsThe MCPs handle all the protocol specific processing, including country specific signal-ing and feature variants. For each signaling protocol the MCPs provide mediation onto a universal call control interface.

The coordination processor 113E (CP113E) and the MCPs communicate via the univer-sal call control interface, which is designed to facilitate the unlimited interworking between all the different protocols and feature sets.

Each MCP controls an engineerable number of media gateway trunk ports, H.323 or media gateway control protocol (MGCP), customer premises gateways (CPG) subscrib-ers or SIP trunk. The number can be flexibly assigned in order to adapt for different traffic patterns, e.g. low call rates for dial-in traffic or high call rates for voice over IP (VoIP).

The MCP communicates with the connected external system components via LAN.

Up to 63 media control tasks (MCT) can run on top of module MCPUE.

Up to 126 media control tasks (MCT) can run on top of module MCPUF.

5.2 StructureThe media control platform (MCP) consists of: media control platform unit (MCPU) MCP shelf (F:MCPA) Ethernet switch board (ETX24)One MCP itself consists of two media control platform units (MCPU), providing for redundancy. The redundant Ethernet switch connects the MCPs to the outer world, i.e. to the interface module to the Ethernet in the MBD (MBDE) or possibly the packet control units (PCU) via redundant Ethernet interfaces.

The interconnection between the MCPU and the Ethernet switches is done via the back-plane, hence cabling, as well as the use of rear transitioning modules (RTMs), is avoided to a large extent. Thus in a fully equipped shelf with 8 MCPs and two Ethernet switches,
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Media Control Platform (MCP)

32 cables and 64 connectors are saved. Up to 4 MCP shelves (F:MCPA) can be inter-connected, thus providing up to 32 MCPs.

The MCP, MBD, PCU, IP control network communicate via 100Base-TX Ethernet with each other. An Ethernet switch (ETX24) is necessary to provide 100Base-TX Ethernet communication between these controller platforms.

The ETX24 is part of the media control platform (MCP) and serves as a connection between the MCP processor boards and the outer system.

The Ethernet switch provides dedicated bandwidth and full-duplex capability between the controller units. Additionally the switch uses frame-based flow control.

The ETX24 provides 24x10/100Base-T/TX Ethernet ports to the backplane (16 to MCPUs, 4 to MBDE and up to 4 ports for the connection between different ETX24 and the router).

For physical connection of E1/T1 if a MCP variant based on different hardware is avail-able. It consists of a group processor (GP) for TDM signaling and PCM30 / PCM24 pro-cessing, an optical interface and special line/trunk unit (LTU) for testing and large conference.

5.3 SoftwareEach of the media control tasks (MCT) functional units has its own software. It super-vises the timing actions in the MCT, processes events from the MCT and the periphery of the MCT.

MCP software is divided into the following two functions: media control functions MCP manager functions Per MCP up to 126 MCTs for controlling of media gateway ports and intersoftswitch connection or up to 32 MCTs for controlling of IP (H.323, VoDSL, MGCP) users are sup-ported.

The MCP variant for physical E1 / T1 connection supports PCM carrier processing in addition.

from/to MBDE 0

from/to MBDE 1

MCP 0 MCP 7

from/to PCU, IP network

one shelf (F:MCPA)

MCPU0-0

MCPU0-1

MCPU7-0

MCPU7-1

Ethernet switch 1(ETX24)

Ethernet switch 0 (ETX24)

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The MCT software consists of the following functional areas: Call processing

The call processing software comprises general routines and call processing user programs. Call processing is responsible for the connection handling (H.323, MGCP, SIP-NNI / SIP-T)

SafeguardingThe safeguarding software detects software faults and errors on the one hand due to the failures resulting from the faults/errors, and on the other hand, by means of routines, audits and self-supervision circuits even though no failure must necessarily occur. In both cases the safeguarding function prompts the media control task (MCT) or network service platform (NSP) to take appropriate measures.

AdministrationThe administration software handles connection-related events according to the state of the connection. MCT administration includes parameter administration, traffic measurement and overload handling.

OperationAll incoming events are received by the MCT operation software and transferred to the appropriate programs.

UtilitiesThe utilities software provides programs for determining and correcting software errors during the installation phase of a network node.

5.4 Technical data

Call process-

MCT software

Safe-guarding

Operation

Adminis-tration

Utilities

Media control platform unit (MCPU)

Interface to Ethernet switch 4 x 10/100BaseT(X) Ethernet ports per MCP

max. transfer rate MCP bus 800 kbyte/s

Management Management system based

Ethernet - I/F 8 * 100Base-TX (for connection of MBD, PCU, IP control network, other Ethernet switches)

service interface via RS-232

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Processor M:MCPUF Pentium - M1.6 GHz CoreBus: Data 4x 133 MHzAddr 2x 133 MHz

Processor M:MCPUE INTEL LV pentium III 800 MHz Core133 MHz Bus

main memory M:MCPUF DDR2:Data 2x 133 MHzAddr 133 MHz

main memory M:MCPUE 133 MHz SDRAM

Core ASIC (MECA) 0.18 Technology

Boot-Memory 8 Mbytes

on board power supply 1.05 V / 1.2 V / 1.8 V / 3.3 V

Power dissipation 30 W

IO-Interfaces (Debug) V.24

interfaces via PCI Ethernet / Fast-Ethernet FEPROM

2x 10/100 Mbit/s32 Mbyte
Central HardwareTable of Contents1Call & Feature Control - Overview1.1Functions1.2Structure1.3Software2Coordination Processor 113E (CP113E)2.1Functions2.2Structure2.3Mechanical design2.4Technical data3Central Clock Generator, Type E (CCGE)3.1Functions3.2Structure3.3Mechanical Design3.4Technical Data4Message Buffer D (MBD)4.1Functions4.2Structure4.3Mechanical design4.4Technical data5Media Control Platform (MCP)5.1Functions5.2Structure5.3Software5.4Technical data

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