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Chap. 4 Modules and Ports
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Modules and Ports
Modules Ports Hierarchical Names Summary
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Modules
Basic component in Verilog for describing/defining a hardware
module <module_name> (<module_terminal_list>);<I/O declaration><parameter declaration>…<module internals>……endmodule
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Components of Modules - I
Variables Declaration Dataflow Statement Module Instantiation Behavior Statement Tasks and Functions
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Components of Modules - II
These components are optional!
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An Example – SR Gate
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Module Description of SR Gate
No “variable declaration”, “dataflow statement” and “behavioral statement” are included in this module
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Testbench for SR Gate
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Modules and Ports
Modules Ports Hierarchical Names Summary
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Ports
I/O Interface used to communicate with external module
“No” port declaration if do not need to communicate with other module, such as Top module
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Module fulladd4 has five ports while top has no port.a, b, and c_in are input ports and sum and c_out are output ports.
List of Ports - I
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List of Ports - II
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Port Declaration
Three types input output inout
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Port Declaration of fulladd4
Default data type of I/O ports is regarded as “wire”.
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Port Declaration of D Flip-Flop
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ANSI C Port Declaration
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Input Port Internal view － viewed as “a wire/net” External view － can be connected to a reg or wire
Output Port Internal view － declared as a reg or wire External view － only be connected to a wire
Inout Port viewed as a wire/net regardless of internal or extern
al module
Port Connection Rules - I
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Port Connection Rules - II
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Mismatch of internal and external port connections Simulation should issue a warning for this conditio
n Floating of port connection
Fulladd4 fa0(sum, , a, b, c_in); // c_out floating
Illegal connection of internal and external ports
Port Connection Rules - II
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An Example of Illegal Internal/External Port Connection
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Connecting Ports to External Signals Connecting ports by module declaration
sequence Connecting ports by name
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Connecting Ports by Module Declaration Sequence
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Connecting Ports by Name Fulladd4 fa_byname(.c_out(c_out), .sum(sum),
.b(b), .c_in(c_in), .a(a));
Fulladd4 fa_byname(.sum(sum), .b(b),
.c_in(c_in), .a(a));
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Modules and Ports
Modules Ports Hierarchical Names Summary
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Hierarchical Names
Named each instance, variables and signals in hierarchical design
Root module Never be referenced by other modules, such as
stimulus Hierarchical instances are separated by dot
sign “.” $display (“%m”)
display hierarchical level of that module
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An Example of Hierarchical Names
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Modules and Ports
Modules Ports Hierarchical Names Summary
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Summary
A module contains module, endmodule keyword Port list, port declaration, variable declaration, dataflow statement,
behavioral block, module instantiation, task and function Ports provide an interface communicated with external environm
ent Input, output, inout
Connecting ports to external signals By port declaration sequence By port name
Hierarchical name Root module Separated by “.” between instances
