Chapter 5. Computer Architecture Organization and Design

Computer System Architecture

Database Lab, SANGJI University

Computer Architecture Organization and Design

• Instruction Codes

• Computer Registers

• Computer Instructions

• Timing and Control

• Instruction Cycle

• Memory Reference Instructions

• Input-Output and Interrupt

• Complete Computer Description

• Design of Basic Computer

• Design of Accumulator Logic

5.1 Instruction CodeA process is controlled by a program

– A program is a set of instructions that specify the operations, data, and the control sequence

– An instruction is stored in binary code that specifies a sequence of microoperations

– Instruction codes together with data are stored in memory (Stored Program Concept)

5.1 Instruction Codes• A computer instruction is

– a binary code that specifies a sequence of micro-operationsfor the computer.

– Each computer has its unique instruction set

• Instruction codes and data are stored in memory

• The computer reads each instruction – from memory and places it in a control register

• The control unit – interprets the binary code of the instruction and – proceeds to execute it by issuing a sequence of micro-

operations

5.1 Instruction Codes• Instructions can be formatted to fit in one

or more memory words.• An instruction may contain

– An opcode + data (immediate operand)– An opcode + the address of data (direct

addressing)– An opcode + an address where the address of

the data is found (indirect addressing)– Data only (location has no instructions)– An opcode only (register-reference or

input/output instruction)

5.1 Instruction Codes• The Basic Computer has two components, a processor and memory

• The memory has 4096 words in it– 4096 = 212, so it takes 12 bits to select a word in memory

• Each word is 16 bits long

• Program– A sequence of (machine) instructions

• (Machine) Instruction– A group of bits that tell the computer to perform a specific operation (a sequence of

micro-operation)

• The instructions of a program, along with any needed data are stored in memory

• The CPU reads the next instruction from memory

• It is placed in an Instruction Register (IR)

CPU RAM0

4095

015

5.1 Instruction Codes 1. Memory

2. Program Counter

0101010101010101

1010101010101010

1100110011001100

0011001100110011

0101010101010011

1010101010101010

1100110011001100

0011001100110011

000000000001PC

3. Instruction Register0101 010101010101IR

address

0000000000000001

0000000000000010

0000000000000011

0000000000000100

0000000000000101

0000000000000110

0000000000000111

0000000000001000

contents

5.1 Instruction Codes• An Instruction code is

– a group of bits that instructs the computer to perform a specific operation (sequence of microoperations).

– It is divided into parts (basic part is the operation part)

• The operation code of an instruction is – a group of bits that defines certain operations such as

add, subtract, shift, and complement– The number of bits required for the operation code

depends on the total number of operations available in the computer

– 2n (or little less) distinct operations n bit operation code

Op. Code Address

15 12 11 0

Instruction format

5.1 Instruction Codes• An operation must be performed

– on some data stored in processor registers or in memory

• An instruction code must therefore specify – not only the operation, – but also the location of the operands

• (in registers or in the memory), and

– where the result will be stored (registers/memory)

Op. Code Address

15 12 11 0

Instruction format

5.1 Instruction CodesStored Program Organization• An instruction code is usually divided into

– operation code, – operand address, – addressing mode, etc.

• The simplest way to organize a computer is – to have one processor register (accumulator AC) and – an instruction code format

• with two parts (op code, address)

5.1 Instruction CodesStored Program Organization

Opcode Address

Instruction Format

Binary Operand

Operands (data)Processor register

(Accumulator AC)

4096 words = 12bits address

15 12 11 0

15 0 Instructions (program)

15 0

015Memory 4096x16

5.1 Instruction CodesAddressing Mode• Immediate:

– the operand is given in the address portion (constant)

• Direct: – the address points to the operand stored in the

memory

• Indirect: – the address points to the pointer (another address)

stored in the memory that references the operand in memory

• Effective address: – Address where an operand is physically located

• One bit of the instruction code can be used to distinguish between direct & indirect addresses

5.1 Instruction CodesAddressing Mode

Opcode Address

Instruction Format15 14 12 0I

11

0 ADD 45722

Operand457

1 ADD 30035

1350300

Operand1350

+AC

+AC

Direct Address Indirect address

Effectiveaddress

5.2 Computer Registers• A processor has many registers to hold instructions, addresses,

data, etc

• The processor has a register, the Program Counter (PC) that holds the memory address of the next instruction to get

– Since the memory in the Basic Computer only has 4096 locations, the PC only needs 12 bits

• In a direct or indirect addressing, the processor needs to keep track of what locations in memory it is addressing: The Address Register (AR) is used for this

– The AR is a 12 bit register in the Basic Computer

• When an operand is found, using either direct or indirect addressing, it is placed in the Data Register (DR). The processor then uses this value as data for its operation

• The Basic Computer has a single general purpose register – the Accumulator (AC)

5.2 Computer Registers• Often a processor will need a scratch register to store

intermediate results or other temporary data; in the Basic Computer this is the Temporary Register (TR)

• The Basic Computer uses a very simple model of input/output (I/O) operations

– Input devices are considered to send 8 bits of character data to the processor

– The processor can send 8 bits of character data to output devices

• The Input Register (INPR) holds an 8 bit character gotten from an input device

• The Output Register (OUTR) holds an 8 bit character to be send to an output device

5.2 Computer Registers

List of BC RegistersDR 16 Data Register Holds memory operandAR 12 Address Register Holds address for memoryAC 16 Accumulator Processor registerIR 16 Instruction Register Holds instruction codePC 12 Program Counter Holds address of instructionTR 16 Temporary Register Holds temporary dataINPR 8 Input Register Holds input characterOUTR 8 Output Register Holds output character

Registers in the Basic Computer11 0

PC

15 0IR

15 0TR

7 0OUTR

15 0DR

15 0AC

11 0AR

INPR0 7

Memory

4096 x 16

5.2 Computer RegistersCommon Bus System

The basic computer has eight registers, a memory unit, and a control unit.

• Paths must be provided to transfer information from one register to another and between memory and registers

• A more efficient scheme for transferring information in a system with many registers is to use a common bus.

5.2 Computer RegistersCommon Bus System

S2S1S0

Bus

Memory unit4096 x 16

LD INR CLR

AddressReadWrite

AR

LD INR CLR

PC

LD INR CLR

DR

LD INR CLR

ACALUE

INPR

IRLD

LD INR CLR

TR

OUTRLD

Clock

16-bit common bus

7

1

2

3

4

5

6

5.2 Computer RegistersCommon Bus System

AR

PC

DR

L I C

L I C

L I C

AC

L I C

ALUE

IR

L

TR

L I C

OUTR LD

INPRMemory

4096 x 16

Address

Read

Write

16-bit Common Bus7 1 2 3 4 5 6

S0 S1 S2

5.2 Computer SystemCommon Bus System

– The connection of the registers and memory of the basic computer to a common bus system :

• The outputs of seven registers and memory are connected to the common bus

• The specific output is selected by mux(S0, S1, S2) :

• Memory(7), AR(1), PC(2), DR(3), AC(4), IR(5), TR(6)

• When LD(Load Input) is enable, the particular register receives the data from the bus

• Control Input : LD, INC, CLR, Write, Read

5.2 Computer SystemCommon Bus System

5.3 Computer Instruction

5.3 Computer Instructions• The set of instructions are said to be complete

– if the computer includes a sufficient number of instructions in each of the following categories:

• Arithmetic, logical, and shift instructions• Instructions for moving information to and from memory

and processor registers• Program control instructions together with instructions

that check status conditions• Input & output instructions

5.4 Timing and Control• Control unit (CU) of a processor translates from machine

instructions to the control signals for the microoperations that implement them

• Control units are implemented in one of two ways• Hardwired Control

– CU is made up of sequential and combinational circuits to generate the control signals

• Microprogrammed Control– A control memory on the processor contains microprograms that

activate the necessary control signals

• We will consider a hardwired implementation of the control unit for the Basic Computer

5.4 Timing and ControlControl unit of Basic Computer

Instruction register (IR)15 14 13 12 11 - 0

3 x 8decoder

7 6 5 4 3 2 1 0

ID0

15 14 . . . . 2 1 04 x 16

decoder

4-bitsequence

counter(SC)

Increment (INR)Clear (CLR)Clock

Other inputs

Controlsignals

D

T

T

7

15

0

CombinationalControl

logic

5.4 Timing and Control

ClockT0 T1 T2 T3 T4 T0

T0

T1

T2

T3

T4

D3

CLR SC

- Generated by 4-bit sequence counter and 4×16 decoder- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.

D3T4: SC ← 0

5.4 Timing and Control

5.5 Instruction Cycle• In Basic Computer, a machine instruction is executed

in the following cycle:1. Fetch an instruction from memory

2. Decode the instruction

3. Read the effective address from memory if the instruction has an indirect address

4. Execute the instruction

• After an instruction is executed, the cycle starts again at step 1, for the next instruction [ PC +1]

5.5 Instruction CycleFetch and Decode

• Fetch and Decode T0: AR ← PC (S0S1S2=010, T0=1)T1: IR ← M [AR], PC ← PC + 1 (S0S1S2=111, T1=1)T2: D0, . . . , D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)

S2

S1

S0

Bus

7Memoryunit

AddressRead

AR

LD

PC

INR

IR

LD Clock

1

2

5

Common bus

T1

T0

5.5 Instruction Cycle

5.5 Instruction Cycle

5.5 Instruction CycleRegister Reference Instruction

r = D7 I’ T3 => Register Reference InstructionBi = IR(i) , i=0,1,2,...,11, the ith bit of IR.

- D7 = 1, I = 0- Register Ref. Instr. is specified in B0 ~ B11 of IR- Execution starts with timing signal T3

Register Reference Instructions are identified when

r: SC ← 0CLA rB11: AC ← 0CLE rB10: E ← 0CMA rB9: AC ← AC’CME rB8: E ← E’CIR rB7: AC ← shr AC, AC(15) ← E, E ← AC(0)CIL rB6: AC ← shl AC, AC(0) ← E, E ← AC(15)INC rB5: AC ← AC + 1SPA rB4: if (AC(15) = 0) then (PC ← PC+1)SNA rB3: if (AC(15) = 1) then (PC ← PC+1)SZA rB2: if (AC = 0) then (PC ← PC+1)SZE rB1: if (E = 0) then (PC ← PC+1)HLT rB0: S ← 0 (S is a start-stop flip-flop)

5.6 Memory Reference Instruction• Opcode (000 - 110) or the decoded output Di (i = 0, ..., 6) are use

d – to select one memory-reference operation out of 7.

5.6 Memory Reference Instruction• - The effective address of the instruction is in AR and

was placed there during – timing signal T2 when I = 0, or during timing signal T3

when I = 1

• Memory cycle is assumed to be short enough to be completed in a CPU cycle

• The execution of MR Instruction starts with T4

AND to ACD0T4: DR ← M[AR] Read operandD0T5: AC ← AC ∧ DR, SC ← 0 AND with AC

ADD to ACD1T4: DR ← M[AR] Read operandD1T5: AC ← AC + DR, E ← Cout, SC ← 0 Add to AC and store carry in E

5.6 Memory Reference Instruction

Memory, PC after execution

21

0 BSA 135Next instruction

Subroutine

20Return address: PC = 21

AR = 135136

1 BUN 135

Memory, PC, AR at time T4

0 BSA 135Next instruction

Subroutine

2021

135PC = 136

1 BUN 135Memory Memory

LDA: Load to ACD2T4: DR ← M[AR]D2T5: AC ← DR, SC ← 0

STA: Store ACD3T4: M[AR] ← AC, SC ← 0

BUN: Branch UnconditionallyD4T4: PC ← AR, SC ← 0

BSA: Branch and Save Return AddressM[AR] ← PC, PC ← AR + 1

5.6 Memory Reference Instruction

BSA: executed in a sequence of two micro-operations:D5T4: M[AR] ← PC, AR ← AR + 1D5T5: PC ← AR, SC ← 0

ISZ: Increment and Skip-if-ZeroD6T4: DR ← M[AR]D6T5: DR ← DR + 1D6T6: M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ← 0

5.6 Memory Reference InstructionMemory-reference instruction

DR M[AR] DR M[AR] DR M[AR] M[AR] ACSC 0

AND ADD LDA STA

AC AC DRSC <- 0

AC AC + DRE CoutSC 0

AC DRSC 0

D T0 4 D T1 4 D T2 4 D T3 4

D T0 5 D T1 5 D T2 5

PC ARSC 0

M[AR] PCAR AR + 1

DR M[AR]

BUN BSA ISZ

D T4 4 D T5 4 D T6 4

DR DR + 1

D T5 5 D T6 5PC ARSC 0

M[AR] DRIf (DR = 0)then (PC PC + 1)SC 0

D T6 6

∧

5.7 Input-Output and Interrupt

5.7 Input-Output and Interrupt

5.7 Input-Output and Interrupt

5.7 Input-Output and Interrupt• Interrupt

5.7 Input-Output and Interrupt

5.8 Complete Computer Description

5.8 Complete Computer Description

5.8 Complete Computer Description