CMOS processing technology.pdf

Rung-Bin LinChapter 3: CMOS Processing Technology 3-1

Chapter 3. CMOS Processing Technology

• Purpose – To introduce the CMOS designer to the technology that is responsible for the semiconductor devices that

might be designed. The basics of semiconductor manufacturing are first introduced. Following this, a number of enhancements to the basic CMOS technology are described. Next, layout design rules and the nature of CMOS latch are introduced. Finally, CAD issues related to process technology are covered.

• 3.1 Silicon Semiconductor Technology: An Overview.– MOS transistor material: Silicon

• It is a semiconductor in its pure state with resistance somewhere between that of a conductor and insulator.

• Conductivity can be varied over several orders of magnitude by introducing impurity atoms into the silicon crystal lattice.

• Dopants may either supply free electrons or holes.• Acceptors are impurity elements (dopants) that accept some of the electrons already in the silicon,

leaving vacancies or holes.• Donors are impurity elements that provide electrons.• Silicon that contains a majority of donors is known as n-type.• Silicon that contains a majority of acceptors is known as p-type.


• A junction is the region where the silicon changes from n-type to p-type material where n-type and p-type materials are brought together.

• By arranging junction in certain physical structures and combining these with other physical structures, various semiconductor devices may be constructed.

• 3.1.1 Wafer Processing– Wafers are cut from ingots of single-crystal silicon that have been pulled from a crucible melt of pure

molten polycrystalline silicon. ( see Figure 3.1 )

• wafer diameter: 75 mm to 300 mm.• wafer thickness: 0.25 mm to 1.0 mm.• crystal orientation determined by a

seed crystal.• Ingot growth rate: 30 to 180 mm/hour.


• 3.1.2 Oxidation – Forming silicon dioxide (SiO2)

– Two common approaches to oxidation of silicon:

• Wet oxidation: when the oxidizing atmosphere contains wafer vapor. The temperature is usually between 900 oC and 1000 oC. This is a rapid process.

• Dry oxidation: when the oxidizing atmosphere is pure oxygen. Temperatures are in the region of 1200 oC to achieve an acceptable growth rate.

– Since SiO2 has approximately twice the volume of silicon, the SiO2 layer grows almost equally in both vertical directions. (see Figure 3.2)


• 3.1.3 Epitaxy, Deposition, Ion-Implantation, and Diffusion– Epitaxy involves growing a single-crystal film on the silicon surface by subjecting the silicon wafer

surface to elevated temperature and a source of dopant material.

– Deposition might involve evaporating dopant material onto the silicon surface followed by a thermal cycle, which is used to drive the impurities form the silicon surface into the bulk.

– Ion implantation involves subjecting the silicon substrate to highly energized donor or acceptor atoms. When these atoms strike on the silicon surface, they travel below the surface of the silicon, forming regions with varying doping concentrations.

– Diffusion at an elevated temperature will occur between any silicon that has differing densities of impurities, with impurities tending to diffuse from areas of high concentration to areas of low concentration.

– Construction of transistors depends on the ability to control where and how much and what type of impurities are introduced into the silicon surface.

• What type of impurities are introduced is controlled by the dopant source. Boron is frequently used for creating acceptor silicon, while arsenic and phosphorous are commonly used to create donor silicon.


• How much impurity used is determined by the energy and time of the ion-implantation or the time and temperature of the deposition and diffusion step.

• Where it is used is determined by using special materials as masks.

– The common materials used as mask include:

• photoresist• polysilicon• silicon dioxide (SiO2)• silicon nitride (Si3N4)

– Selective diffusion entails:

• Patterning windows in a mask material on the surface of the wafer.• Subjecting exposed area to a dopant source.• Removing any unrequired mask material.

– Example: The process of creating an oxide mask:

Step 1: Covering the surface of the oxide with an acid resistant coating (called photoresist), and on topof this covering a mask which contains desired oxide windows.

Step 2: Polymerizing the acid resistant coating by passing the coated silicon through the UV light.Step 3: Removing the polymerized areas with an organic solvent. This is called a positive resist.Step 3’:Removing the unexposed photoresist area by the solvent (either Step 3 or 3’ is done). This is

called a negative resist..


• Step 4: Etching of exposed SiO2.

– Figure 3.3 shows an example of negative resist process.


– Using photoresist in conjunction with UV light sources, diffraction around the edges of the mask patterns and alignment tolerances limit line widths to around 0.8 um.

– Electron beam lithography (EBL) can produce line widths smaller than 0.5 um.

– Main advantages of EBL:

• Patterns are derived directly from digital data.• No intermediate hardware image such as masks is needed (i.e., masks are stored as the form of data).• Different patterns may be accommodated in different sections of wafers.• Changes to patterns can be implemented quickly.

– Main disadvantages of EBL:

• Cost of the equipment.• Requiring the large amount of time (i.e., the desired patterns are generated sequentially and only one

wafer can be handled at a time).


• 3.1.4 Silicon Gate Process– Polysilicon, not having a single crystalline structure, can be used as interconnect in silicon ICs and as the

gate electrode on MOS transistors.

– Polysilicon gate can be further used as a mask to allow precise definition of source and drain electrodes.

– Polysilicon is formed when silicon is deposited on SiO2 or other surface. Undoped polysilicon has high resistivity. Polysilicon gate and source/drain regions are doped at the same time to increase their conductivity.

– Figure 3.4 shows the processing steps after the initial patterning of the SiO2.


– Two kinds of silicon oxides:

• Gate-oxide (thinox): A thin highly controlled layer of SiO2 which defines the gate area of a transistor.• Field-oxide: A thick layer of SiO2 is required elsewhere to isolate the individual transistors.

– Figure 3.4(b) forms gate oxide.

– Figure 3.4(c) grows polysilicon gate.

– Figure 3.4(d) dopes the gate and source/drain regions. Doping of substrate only occurs at the regions where the polysilicon gate does not shadow the underlying substrate or where is not covered by SiO2. The case of using silicon gate as a mask is referred to as self-aligned process because the source and drain do not extend under the gate.

– Figure 3.4(e) forms the contact cuts.

– Figure 3.4(f) forms the contacts and interconnect.

– Note that parasitic MOS transistors exist between

unrelated transistors as shown in Figure 3.5.

These transistors have very thick gate oxide such

that their threshold voltage is much higher than

that of a regular transistor.


• 3.2 Basic CMOS Technology– The four main CMOS technologies:

• n-well process• p-well process• twin-tub process• silicon on insulator

– Figure 3.6 summarizes the drawing convention for presenting CMOS process technology.


• 3.2.1 A Basic n-well CMOS Process– Start with a lightly doped p-type substrate, creating the n-type well for the p-channel devices and building

the n-channel devices on the native p-substrate.

– Figure 3.7 illustrates the major steps involved in a typical n-well CMOS process.

• n-well definition: By ion implantation or deposition and diffusion (see Fig. 3.7(a)).• Active area definition: Defining the areas of thin oxide that are needed to implement transistor gates

and allow implantation to form p- or n-type diffusions for transistor source/drain regions. A thin layer of SiO2 is grown on this area and covered with Si3N4 (see Fig. 3.7(b)).

• Channel-stop implant: Using p-well mask (the complement of n-well mask) and doping the p-substrate in areas where separate the two transistors. This, in conjunction with the thick field oxide will raise the threshold voltage of the parasitic MOS transistor, which prevents conduction between unrelated transistor source/drains. (see Figure 3.7(c))

• Growing of thick field oxide:This grows in areas where the Si3N4 layer is absent. The oxide grows in both directions vertically and also laterally under the SiO2/ Si3N4 sandwich. This lateral movement results in what is call a “bird’s beak”. This general oxide construction technique is called LOCOS for LOcal Oxidation Of Silicon. The bird’s beak effect reduces the width dimension of a transistor (see Fig 3.7(d)).

• Adjustment of n/p transistor threshold voltage: With normal doping concentration, the threshold voltage for n-devices is around 0.5~0.7 volts, while the p-device threshold voltage is around -1.5 to -2.0 volts. Thus the p-device has to have its threshold voltage adjust more than n-device. This is done by creating a “buried channel” that is formed by introducing an additional negatively charged layer at the silicon/oxide interface (so that the channel is moved further done into the silicon).

• Completion of polysilicon gate definition (see Fig. 3.7(e)).



• Implanting of n+ by an n_plus mask: A thin-oxide area exposed by the n-plus mask will become an n+ diffusion area. If the n-plus area is in the p-substrate, then an n-channel transistor (see Figure 3.7(f)) or n-type diffusion wire may be constructed. If the n-plus area is in the n-well (not shown), then an ohmic contact to the n-well may be constructed. (An ohmic contact is one which is only resistive in nature and is not rectifying. In other words, there is no junction. Current can flow in ohmic contact.) To reduce hot electron effects for modern small dimension processes , “drain engineering” is performed. This consists of performing a shallow n-LDD (Light Doped Drain) implant that covers the source/drain region where there is no poly. A spacer oxide is then grow over the polysilicon gate. An n+ implant is then used to produce n+ implant that are spaced from the edge of the original poly gate edges. The spacer is then removed, resulting in a structure that is more resistant to hot-electron effects (see Fig. 3.7(g)).

• Implanting of p+ by a complement (i.e. p+ mask) of the n-plus mask: A thin-oxide area exposed by the p+ mask will become a p+ (or p-active) diffusion area. P-active in the n-well defines possible p-transistors and wires (see Fig. 3.7(h)). A p-active area in the p-substrate allows an ohmic contact to be made. The LDD step is not needed for p-transistors.

• Defining of contact cuts (see Fig. 3.7(i)).• Metalization ( see Fig. 3.7(j))• passivation (not shown)


– The cross section of a CMOS inverter is shown in Figure 3.8.

– Substrate contacts:

• Topside p-substrate contact to VSS is preferred because it reduces parasitic resistances that could cause latch-up.

• Well contacts to VDD is also from topside.

– Substrate (p-substrate versus n-well) contacts are formed by placing n+ regions in the n-well (VDD contacts) and p+ in the p-type substrate (VSS contacts) as shown in Figure 3.9(a).


• 3.2.2 The P-well Process– Typical p-well fabrication steps are similar to an n-well process, except that a p-well is implanted to form

n-transistors rather than an n-well.

– P-well processes are preferred in circumstances where the characteristics of the n- and p-transistors are required to be more balanced than that achievable in an n-well process. Because the transistor that resides in the native substrate tends to have better characteristic, the p-well process has better p-devices than an n-well process. Fig. 3.10

• 3.2.3 Twin-Tub Processes– The starting material is either an n+ or p+ substrate

with a lightly doped epitaxial layer, which is used

for protection against latch up (see Figure 3.10).

– The process similar to n-well process entails the following steps

• Tub formation• Thin-oxide construction• Source and drain implantations• Contact cut definition• Metallization

– This process provides separately optimized wells, balanced performance n-transistors and p-transistors may be constructed.


• 3.2.4 Silicon On Insulator (SOI)– Rather than using silicon as the substrate, technologies such as SOI have sought to use an insulating

substrate to improve process characteristics such as latch up and speed.

– The steps used in typical SOI CMOS process are as follows (see Figure 3.11):

• A thin film (7-8 um) of very lightly doped n-type Si is epitaxially grown over an insulator. Sapphire or SiO2 is a commonly used insulator. (Figure 3.11(a))

• An anisotropic etch is used to etch away the Si except where a diffusion area will be needed. (Figure 3.11(b) & (c).

• Implantation of the p-island where an n-transistor is formed. (Figure 3.11(d))• Implantation of the n-island where a p-transistor is formed. (Figure 3.11(e))• growing of a thin gate oxide (100 - 250 Å).• Depositing of phosphorus-doped polysilicon film over the oxide. (Figure 3.11(f))• Patterning of polysilicon gate. (Figure 3.11(g))• Forming of the n-doped source and drain of the n-channel devices in the p-islands. (Figure 3.11(h))• Forming of the p-doped source and drain of the p-channel devices in the n-islands. (Figure 3.11(i))• Depositing of a layer of insulator material such as phosphorus glass or SiO2 over the entire structure.• Etching of the insulator at contact-cut locations. The metallization layer is formed next. (Figure

3.11(j))• Depositing of pssivation layer and etching of bonding pad location.


– Because the diffusion regions extend down to the insulating substrate, only “sidewall” areas associated with source and drain diffusions contribute to the parasitic junction capacitance.

– Since sapphire and SiO2 are extremely good insulators, leakage currents between transistors and substrate and adjacent devices are almost eliminated.


– In order to improve the yield, some processes use “preferential etch,” where the island edges are tapered (Figure 3.12).

– Figure 3.12

– Advantages of SOI:

• Due to the absence of wells, transistor structures denser than bulk silicon are feasible.• Lower substrate capacitance.• No field-inversion problems (the existence of parasitic transistor between two normal transistors)• No latch up is possible because of the isolation of transistors by insulating substrate.


• No body-effect problems because of no conducting substrate.• With enhanced radiation tolerance.

– Disadvantages of SOI :

• Lack of substrate diodes makes I/O protection difficult.• Coupling capacitance still exists.• More expensive to build.


• 3.3 CMOS Process Enhancement– Enhancement to increase routability of circuits, provide high-quality capacitor, or provide resistors of

variable characteristics. These enhancements include :

• multiple levels of metal (more than five levels).• double or triple-level poly.• combinations of the above.

– 3.3.1 Interconnect

• More levels of metal improve the power and clock distribution to modules and ease the signal routability.

– 3.3.1.1 Metal Interconnect

• If planarization is employed, the second level metal pitch can be the same as the first. However, if the vertical topology becomes more varied, the width and spacing of metal has to increase to prevent the metal from breaking.

• Contacting the second-layer metal to the first-layer metal is achieved by via as shown in Figure 3.13 and a number of contact geometries are shown in Figure 3.14.


• No restrictions on the placement of the via with respect to underlying layers (Figure 3.14(a)).• Placement of via inside (Figure 3.14(b)) or outside (Figure 3.14(c)) the underlying polysilicon or

diffusion areas.• Stacking of vias on top of contacts (Figure 3.14(d)).

– The steps for a two-metal process

• The oxide below the first-metal layer is deposited by atmospheric chemical vapor deposition (CVD).• The second oxide layer between the two metal layers is applied in a similar manner.• Removal of the oxide by a plasma etcher.


• 3.3.1.2 Polysilicon/Refractory Metal Interconnect– A doped-polysilicon with sheet resistance ranged from 20 to 40 Ω/square can also be used as interconnect

layer.

– To further reduce the resistance of polysilicon, a refractory metal can be coated upon the polysiliconwithout extra mask with the following three approaches.

• As shown in Figure 3.15(a), a silicide (e.g., silicon and tantalum) is used as gate material. Sheet resistances of the order of 1 to 5 Ω/square may be obtained. This is called the silicide gate approach.

• Figure 3.15(b) uses a sandwich of silicide upon polysilicon, which is commonly called the polycideapproach.

• The approach presented in Figure 3.15 (a) & (b) can be applied to the formation of source and drain region using the salicide process (Self Aligned SILICLDE) (Figure 3.15(c)). An increasing trend is to use the salicide approach.


• 3.3.1.3 Local Interconnect– The silicide (eg., TiN) itself may be used as a “local interconnect” layer for connection within logic cells.

– Local interconnect allows a direct connection between polysilicon and diffusion, thus reducing the need for area-intensive contacts and metal.

– Figure 3.16 shows a portion of a six transistor

SRAM Cell that uses local interconnect.

Thus, area is reduced by 25%.


• 3.3.2 Circuit Elements• 3.3.2.1 Resistors

– Undoped polysilicon is highly resistive. This property is used to build resistor used in static memory. Resistors in the tera-Ω (1012Ω) region are used. A value of 3 TΩ results in a standby current of 2µA for 1 M-bit memory.

– High quality resistors can be obtained by

• adding a resistive metal such as nichrome.• laser trimming.

– Sheet resistance values in the kΩ/square are normal.

• 3.3.2.2 Capacitors– Figure 3.17 shows a typical polysilicon capacitor for analog applications. One extra layer of polysilicon

and a second thin-oxide layer are required.


– Figure 3.18(a) shows a structure of the trench capacitor used as a memory capacitor. The trench is 4 µm deep and has a capacitance of 90 fF.

• The sides of the trench are doped n+ and coated with a 10nm oxide.This forms the top plate of the capacitor and one side of the pass transistor.

• The trench is filled with a polysilicon plug, which forms the bottom plate of the cell storage capacitor. This is held at VDD/2 via a metal connection.

• The bottom of the trench has a p+ plug that forms a channel stop region to isolate adjacent capacitors.

– Figure 3.18(b) shows a fin-type capacitor used in a 64-Mb DRAM.


• 3.3.2.3 Electrically Alterable ROM– Figure 3.19 shows a typical memory structure, which consists of a stacked-gate structure. The normal gate

is left floating, while a control gate is placed above the floating gate. A very thin oxide (10 nm) called the tunnel oxide separates the floating gate from the source, drain and substrate.

– By controlling the control gate, source and drain voltages, the very thin tunnel oxide between the floating gate and the drain of the device is used to allows electrons to “tunnel” to or from the floating gate to turn the cell on or off, respectively, using Fowler-Nordheim tunneling.


• 3.4 Layout Design Rules– Layout (design) rules can be considered as a prescription for preparing the photomask used in the

fabrication of integrated circuits.

– The main objective associated with layout rules is to obtain a circuit with optimum yield in as small an area as possible without compromising reliability of a circuit.

– Two sets of design rule constraints in a process relate line widths and interlayer spacing.

– The design rules primarily address two issues:

• (1) the geometrical reproduction of features that can be reproduced by the mask-making and lithographical process.

• (2) the interactions between different layers.

– Two commonly used approaches to describing design rules:

• (1) ‘Micro’ rules stated at some micron resolution (e.g., 1µm) and given as a list of minimum feature sizes and spacing for all the masks required in a given process. This is the normal style for industry.

• (2) Lambda(λ)-based rules popularized by Mead and Conway are based on a single parameter,λ, which characterizes the linear feature - the resolution of the complete wafer implementation process - and permits first order scaling. This is not sufficient for submicron process.


• 3.4.1 Layer Representations– Although, CMOS process is generally complex, at a sufficiently high conceptual level, all CMOS

processes use the following features:

• Two different substrates• Doped regions of both p- and n-transistor forming material.• Transistor gate electrodes.• Interconnect paths• Interlayer contacts.

– Table 3.1 shows typical layer representation for the n-well CMOS process.


• 3.4.2 CMOS n-well Rules– Table 3.2 shows a version of n-well rules based on the MOSIS CMOS Scalable Rules and the rules for a

commercial 1µ CMOS process. The MOSIS rules are expressed in terms of λ. See Figure 3.25 for illustration.

– The design rules are defined in terms of

• feature sizes• separations and overlaps

– Drawn dimensions of the mask usually have to be biased to allow for varying types of processing (e.g., active mask is bloated to take into account the encroachment of field oxide during LOCOS and contacts are shrunk for excessive etching).




– Comparisons of λ-rules versus micron-rules (at λ=0.5 µm)

• Metal 1 contact pitch is 3.5 µm for λ-rule, but 2.75 µm for micron-rule.• Metal 2 via pitch is 4.0 µm for λ-rule, but 2.75 µm for micron-rule.• Transistor pitch (contact-poly-contact pitch) is 4 µm for λ-rule, but 3.75 µm for micron-rule.

– Table 3.3 summarizes the basic dimensions for the representative processes ranged from 0.25 - 0.6 µm.


• 3.4.3 Design Rule Backgrounder– Well Rules :

• The outside dimension should provide sufficient clearance between the n-well edges and the adjacent n+ diffusion.

• N-well must be thoroughly connected to Vdd to reduce sheet resistance.

– Transistor Rules :

• Gate extension: poly is required to extend beyond the edges of the diffusion (see Figure 3.26(a)), otherwise there may be a shorted path between the source and drain of the transistor.

• Source /drain must be extended beyond the poly gate so that diffused regions exist to carry charge into and out of the channel. (See Figure 3.26(b))


– Contact Rules :

• Contact types– Metal to p-active (p-diffusion) contact.– Metal to n-active (n-diffusion) contact.– Metal to polysilicon contact.– VDD and VSS substrate contacts.– Split (substrate contacts).

• Well and substrate contacts must be employed to tie the well to VDD and to tie the substrate to VSS, respectively.

• The split (merged, abutting) contact is equivalent to two separate metal-diffusion contacts that are strapped together with metal (Figure 3.27). This structure is used to tie transistor sources to either the substrate or the n-well.


– Guard Rings (Figure 3.28):

• p+ guard ring is a p+ diffusion on p-substrate whereas n+ guard ring is a n+ diffusion on n-well to collect injected minority carriers.

• n-devices are constructed upon p-substrate with n+ diffusion source/drain. The minority carriers are holes. Thus, p+ guard ring connected to VSS is employed to collect holes.

• p-devices are constructed upon n-well with p+ diffusion source/drain. The minority carriers are electrons. Thus, n+ guard ring connected to VDD is employed to collect electrons.

32

n+ guard ring

p+ guard ring


– Metal Rules :

• Metal spacings may vary with the width of the metal line (so-called flat-metal rules).• There may also be maximum-metal rules.• There may require the whole chip to be covered by a certain portion (e.g., 2/3 ) of metal.

– Special via rules, metal2 rules, via2 rules, and metal3 rules may be specifically presented for manufacturability requirement.


• 3.4.5 Layer Assignments– Table 3.4 shows an example of layer assignments for MOSIS Scalable CMOS Design-rule.

– CIF: Caltech Intermediate Form.


• 3.5 Latchup– Latchup is the shorting of the VDD and VSS lines due to the parasitic circuit effect present in CMOS

structure. This usually results in chip self-destruction or at least system failure with the requirement to power down.

• 3.5.1 The Physical Origin of Latchup– The source of the latchup effect may be explained by examining the process cross section of a CMOS

inverter, shown in Figure 3.29(a).

– Under the right conditions, the parasitic circuit has the VI characteristics shown in Figure 3.29(c ).

– If a current is drawn from the npn-emitter, the emitter voltage Vne becomes negative with respect to the base until the base-emitter voltage is approximately 0.7 volts. At this point the npn transistor turns on and a current flows through the well resistor. This raises the base-emitter voltage of the pnp transistor, which turns on when the pnp Vbe=-0.7 volts. This in turn raises the npn base voltage causing a positive feedback condition as shown in Figure 3.29( c). This is in effect a short circuit.

– At a certain npn base-emitter voltage, called the trigger point, the emitter voltage suddenly “snap back”and enters a stable state called the “ON” state. This state will persist as long as the voltage across the two transistor is greater than the holding voltage.

– As the emitter of the npn is the source/drain of the n-transistor, these terminals are now at roughly 4 volts (holding voltage). Thus there is about 1 volt across the CMOS inverter (i.e., Vds is at most 1 volt).


– Latchup Triggering

• Two distinct triggering are possible :(1) Lateral triggering occurs when a current flows in the emitter of the lateral npn-transistor. The

static trigger point is set by , where

» Vpnp-on ∼ 0.7 volts – the turn-on voltage of the vertical pnp-transistor.» αnpn=common base gain of the lateral npn transistor.» Rwell=well resistance.

(2) Vertical triggering occurs when a sufficient current is injected into emitter of the vertical-pnp transistor.

– Current has to be injected into either the npn-or pnp-emitter to initiate latch up. This may occur for internal circuit due to supply voltage transients. It commonly happens at the I/O circuits where internal circuit meets the external world and large currents can flow.

wellnpn

onpnpntrigger R

VI

α−=


– Figure 3.30(a) shows an example where the source of an nMOS output transistor experiences undershoot with respect to VSS. When the output dips below VSS by more than 0.7V, the drain of the nMOS output driver is forward biased, which initiates latch up.

– Figure 3.30(b) shows a complementary case where the pMOS output transistor experiences an overshoot more than 0.7V beyond VDD.


• 3.5.3 Latchup Prevention– For latchup to occur, an analysis of the circuit in Figure 3.29(b) finds

where

– Reducing the resistor values and reducing the gain of the parasitic transistors are the basis for eliminating latchup. This can be approached by,

• Latchup resistant CMOS process• Layout techniques

RsubstrateDD

pnpRwellRsubstratenpnpnpnpn II

II−

+++>

))(1(1

ββββ

substrate

npnbeRsubstrate R

VI −=

well

pnpbeRwell R

VI −=

currentsupply total=DDI


– Latch up resistant process (Layout techniques will be presented in the following section) :

• Use of silicon starting-material with a thin epitaxial layer on top of a highly doped substrate. This decreases the value of the substrate resistor.

• Retrograde well structure formed by a highly doped area at the bottom of the well and by lightly doping on the top portion of the well. This preserves good characteristics for the p-transistors and also reduces the well resistance deep in the well.

• Increasing holding voltage above VDD such that latchup will not occur.• It is hard to reduce the betas (gains) of the bipolar transistors.


• 3.5.4 Internal Latchup Prevention Technique– Reducing Rsubstrate and Rwell by substrate contact. The following rules are presented to achieve this goal.

• Every well must have a substrate contact of the appropriate type.• Every substrate contact should be connected to metal directly to a supply pad.

– Place substrate contacts as close as possible to the source connection of transistors and connect them to supply rails (i.e., VSS for n-device, VDD for p-devices).

– A very conservative rule would place one substrate contact for every supply connection. A less conservative rule is to place a substrate contact for every 5-10 transistors or every 25-100µm.

– Lay out n- and p- transistors with packing of n-device toward VSS and packing of p-device toward VDD.


• 3.5.5 I/O Latchup Prevention– Guard rings can be used to reduce the gain of the parasitic transistors.

– A p+ guard ring is shown in Figure 3.31(a) for an n+ source/drain, while Figure 3.31(b) shows an n+ guard ring for a p+ source/drain. Figure 3.31(c) uses double guard rings.

– As shown in the figures, these guard bands act as “dummy-collectors” and reduce the gain of the parasitic transistors by collecting minority carriers and preventing them from being injected into the respective base.

– Double guard rings usually employed in I/O circuits to prevent latchup from happening.

– Some other rules listed in the text book by Weste can be found for preventing I/O circuits from latchup.


• 3.6 Technology-related CAD Issues– Two basic checks have to be completed to ensure that the mask of a circuit can be turned into a working

chip after fabrication.

• The specified geometric design rules must be obeyed.• The interrelationship of the mask must produce the correct interconnected set of circuit elements.

– Two CAD tools are employed to check these two requirements

• Design Rule Check (DRC) program checks the geometric design rules• Circuit extraction program checks the proper forming of circuit elements and their interconnection.

• 3.7 Summary• CMOS fabrication processes are studied : n-well process, p-well process, twin-tub process, and SOI

process.• Process enhancement is introduced

– multiple metal interconnect, polysilicon/refractory metal interconnect, local interconnect.– resistors, capacitors, programmable ROM.

• Layout design rules.• Latch up.• CAD issues.

Documents

CMOS processing technology.pdf