Collections Labs

Cadence Design Systems, Inc.

RAPID ADOPTION KIT

Usage of collections in EDI & ETS

To get the testcase click on download

Version

Encounter Digital Implementation 11 and above Encounter Timing System 11 and above

May - 2013

RAK to demonstrate Usage of collections in EDI & ETS

COPYRIGHT 2013, CADENCE DESIGN SYSTEMS, INC. PAGE 2 ALL RIGHTS RESERVED.

Table of Contents To download testcase click here ......................................................................................................... 1

Purpose ................................................................................................................................................... 3

Lab 1-1 Loading the Database .............................................................................................................. 3

Lab 1-2 Explore the design with the All Star (all_*) commands ............................................................. 3

Lab 1-3 Querying and Manipulating Collections ................................................................................... 5

Lab 1-4 Exploring Instances (cells) and Instance (cell) Properties.......................................................... 9

Lab 1-5 Exploring Clocks and Clock Properties.................................................................................... 10

Lab 1-6 Exploring Designs and Design Properties ............................................................................... 10

Lab 1-7 Exploring Libraries and Library Properties .............................................................................. 11

Lab 1-8 Exploring Library Cells and Library Cell Properties .................................................................. 11

Lab 1-9 Exploring Library Pin and Library Pin Properties ..................................................................... 11

Lab 1-10 Exploring Library Cell Timing Arcs and their Properties ........................................................ 12

Lab 1-11 Exploring Nets and Net Properties ....................................................................................... 13

Lab 1-12 Exploring Pins and Pin Properties......................................................................................... 14

Lab 1-13 Exploring Ports and Port Properties ..................................................................................... 15

Lab 1-14 Exploring Timing Paths and Timing Path Properties ............................................................. 15

Lab 1-15 Exploring Timing Points and Timing Point Properties ........................................................... 16

Lab 1-16 Exploring Timing Arcs and Timing Arc Properties ................................................................. 17

Lab 1-17 Exploring Path Group Properties.......................................................................................... 19

Lab 2-1 Application - Some real life examples ........................................................................................ 20



Purpose

The EDI/ETS documentation describes the properties available through advanced timing Tcl programming. But sometimes accessing that data isn't as easy as it appears. The goal of this lab is to show the functions that serve as the fundamental building blocks of collections. And demonstrate how they can work together to provide quick and easy access to data that otherwise would be difficult to attain. Note that the collection commands do not return lists of objects. They return a collection handle. It is up to the user to then query the collection to gain visibility into specific object names.

Lab 1-1 Loading the Database

1) cd into the collections directory 2) start encounter:

unix> encounter nowin -init data/run.tcl

3) Now we are ready to start querying the database.

Lab 1-2 Explore the design with the All Star (all_*) commands

1) To find all input pins

all_inputs

2) To find all input pins those are not defined as clocks in the .sdc. You can see that the ref_clk and test_clk ports are missing from the list.

all_inputs -no_clock

3) To find all output pins:

all_outputs

4) Similarly, finding all sdc defined clocks is quite easy. This also returns the virtual clock io_clk and the generated clock pll_clk

all_clocks

5) all_fanout traces the timing arcs downstream from an object. By default it will stop at timing endpoints, like a register. To find all pins in the fanout cone of ref_clk, do the following. It will return both input/output pins (as highlighted in red in the example) in the data path from the ref_clk pin, through a buffer to instance U0s ref_clk pin.

all_fanout -from [get_ports ref_clk]



encounter> all_fanout -from [get_ports ref_clk] ref_clk ref_clk__L1_I0/A ref_clk__L1_I0/Y u0/ref_clk

6) To only report endpoints (and exclude intermediate pins)

all_fanout -from [get_ports ref_clk] -endpoints_only

7) The above reported pins. To report instances:

all_fanout -from [get_ports ref_clk] -endpoints_only -only_cells

8) Similarly, use all_fanin to trace backwards from an object. Here, trace back from a reset pin on a flop, to the top port ref_clk. Note its reporting all pins in the path.

all_fanin -to [ get_pins u0/ref_clk ] encounter 144> all_fanin -to [ get_pins u0/ref_clk ] u0/ref_clk ref_clk__L1_I0/Y ref_clk__L1_I0/A ref_clk

9) To find instances in the design that are registers:

all_registers cells

10) To find instance/pins in the design that are clock pins.

all_registers -clock_pins encounter 146> all_registers -clock_pins AO1/COEF_reg_0_0/CK AO1/COEF_reg_0_1/CK AO1/COEF_reg_0_2/CK AO1/COEF_reg_0_3/CK AO1/COEF_reg_1_3/CK...

11) You can also query data or output pins.

all_registers data_pins

or

all_registers output_pins

12) To find instance/clock pins associated with a particular clock.

all_registers -clock_pins -clock [get_clocks ref_clk] all_registers -clock_pins -clock [get_clocks pll_clk]

13) To find instance/pins that are register outputs associated with a particular clock:

all_registers -output_pins -clock [get_clocks test_clk]



encounter 148> all_registers -output_pins -clock [get_clocks test_clk] AO1/COEF_reg_0_0/Q AO1/COEF_reg_0_1/Q AO1/COEF_reg_0_2/Q AO1/COEF_reg_0_3/Q AO1/MULT16_reg_2_1/Q AO1/MULT16_reg_2_10/Q AO1/MULT16_reg_2_11/Q ...

14) To find all pins connected to the net n_144:

all_connected n_144

encounter 149> all_connected n_144 ISO_RULE_ISO_HIER_INST_0/CPF_ISO_DATA column/Xn_out[0]

15) To find the instance names of module at the top level:

all_instances [get_design FIR_filter_1] encounter 150> all_instances [get_design FIR_filter_1] ring

Note: FIR_filter_1 is a module. EDI returns "ring" which is the instance name. This may not be very useful in this design because it is so small.

16) To find the instance names of a module within the design hierarchy:

all_instances -hierarchical [get_design add_signed_7]

Lab 1-3 Querying and Manipulating Collections

Once you have a collection, what data does it contain? report_property lists all available properties and their values. To query a specific property, use get_property.

1) To see all properties associated with the port rst:

report_property [ get_ports rst ]

Some properties reported by report_property can vary from one analysis view to another, such as a maximum slack value. Unfortunately report_property does not have a view option. However, get_property, which queries any one of the properties reported by report_property does support a view option for some objects.

2) To report one particular property, use get_property. To see the direction of the rst pin:

get_property [ get_ports rst ] direction encounter 154> get_property [ get_ports rst ] direction in



3) To query the max slack associated with different views for the rst pin:

get_property [get_ports rst] slack_max -view VIEW1

get_property [get_ports rst] slack_max -view VIEW2

4) Heres another get_property example. Here we find the number of pins on a hierarchical instance;

get_property [ all_instances [get_design FIR_filter_1] ] pin_count

Note, report_property and get_property will be used extensively in this lab. So try getting comfortable using them.

5) To see the types of properties associated with an object:

list_property -type where is: cell, clock, design, lib, lib_cell, lib_pin, lib_timing_arc, net, path_group, pin, port, timing_arc, timing_path or timing_point For instance, to see the properties associated with an instance: list_property type cell

6) Now, create a collection of ports

set ports_C [ get_ports * ]

7) To find the number of objects in the collection.

sizeof_collection $ports_C

encounter 156> sizeof_collection $ports_C 72

8) Put the them together to quickly find the number of ports in the design:

sizeof_collection [get_ports *]

9) To extract the 5th item in the collection and report its properties:

set fifth_C [ index_collection $ports_C 5 ]

report_property $fifth_C

10) To iterate through the collection and report all port names:

foreach_in_collection item_C $ports_C { set name [ get_property $item_C escaped_name ]



puts $name }

11) Prepare to manipulate multiple collections

set ports_C [ get_ports * ] sizeof_collection $ports_C; # it has 72 objects set nets_C [ get_nets * ] sizeof_collection $nets_C; # it has 182 objects

12) Make a copy of the collection $ports_C

set copy_C [ copy_collection $ports_C ] sizeof_collection $copy_C; # prove it contains 72 objects, just like collection1

13) Compare collections. A return value of 0 means they are the same; 1 means they are different

compare_collection $ports_C $copy_C; # this reports 0; indicating they are the same compare_collection $nets_C $copy_C; # this reports 1; indicating they are different

14) To add one collection to another:

set ports_C [ add_to_collection $ports_C $nets_C ] sizeof_collection $ports_C; # returns 254 (72 + 182)

15) Alternatively, we can append to collection:

append_to_collection ports_C $nets_C sizeof_collection $ports_C; # returns 436 (254 + 182)

16) Use remove_from_collection to remove objects from a collection. Interestingly, size_of_collection returns 72. That is because the objects in $nets_C actually get removed twice (436 182 182 = 72)

set remove_C [remove_from_collection $ports_C $nets_C] sizeof_collection $remove_C;

17) get_object_name reports the names of all objects in a collection, PROVIDED the objects are all of the same type.

get_object_name $ports_C ; # reports an error because its a collection of nets and ports get_object_name $nets_C ; # reports names of 182 nets in the collection

18) query_objects reports the name of all objects in a collection, even if the objects are not of the same type. The default is to return 100 names. Use -limit to change the default.

query_objects $ports_C ; # lists 100 object namesnote this gave an error earlier query_objects $nets_C -limit 20 ; # lists 20 out of 182 object names



19) A user can add properties to some object types (but not all). Here, create a new property for the "net" object type. It will be of type "integer".

define_property -object_type net -type int custom_prop

20) Now, find the net n_2

set myNet_C [ get_net n_2 ]

21) To set a value on this property, you must be in interactive constraint mode:

set_interactive_constraint_modes [all_constraint_modes]

22) Now assign a value to the property and report it:

set_property $myNet_C custom_prop 10 report_property $myNet_C get_property $myNet_C custom_prop

23) You can iterate on collections using a for each-like command:

set nets_C [ get_nets -hierarchical * ] foreach_in_collection net $nets_C { set name [get_property $net name] puts "$name" }

24) Sorting can be done on collections as long as they are homogenous...meaning the collection objects are of the same type. The best way to demonstrate sorting is with an example. If you want to sort all nets (in descending order) to find the largest pin_capacitance_max value

foreach_in_collection net [sort_collection $nets_C pin_capacitance_max -descending] { set name [get_property $net name] set cap [get_property $net pin_capacitance_max ] puts "$name $cap" }

25) The net with the largest pin_capacitance_max is:

index_collection [sort_collection $nets_C pin_capacitance_max ] 0

26) Or the net with the smallest pin_capacitance:

index_collection [sort_collection $nets_C pin_capacitance_max -descending] 0

27) To find all nets with the custom_prop value > 5 (remember we put a value of 10 on net n_2)

foreach_in_collection net [get_nets * -filter {custom_prop > 5}] {



set name [get_property $net name] set prop [get_property $net custom_prop] puts "$name $prop" }

Lab 1-4 Exploring Instances (cells) and Instance (cell) Properties

1) Here are some basic instance queries

get_cells * get_cells * -hierarchical get_cells AO1/add_94_37_I2/g703

2) Lets focus on one particular instance

set myCell_C [ get_cells AO1/add_94_37_I2/g703 ]

3) Do report_property to see all properties that can be queried and their values

report_property $myCell_C

4) Now use get_property to query the specific cell properties.

get_property $myCell_C ref_lib_cell_name get_property $myCell_C area get_property $myCell_C early_rise_clk_cell_derate_factor get_property $myCell_C is_combinational get_property $myCell_C is_dont_touch get_property $myCell_C pin_count get_property $myCell_C x_coordinate_max

5) Find all hierarchical instances that have more than 3 pins. Note: is_hierarchical == true for this search.

foreach_in_collection inst_C [filter_collection [get_cells * -hierarchical] {pin_count > 3 && is_hierarchical == true}] {

set name [ get_property $inst_C name ] set count [ get_property $inst_C pin_count ] set cell [ get_property $inst_C ref_lib_cell_name ] puts "$name $count $cell" }

6) If you change is_hierarchical == false, then you'll find all library cells with more than 3 pins.

foreach_in_collection inst_C [filter_collection [get_cells * -hierarchical] {pin_count > 3 && is_hierarchical == false}] {



set name [ get_property $inst_C name ] set count [ get_property $inst_C pin_count ] set cell [ get_property $inst_C ref_lib_cell_name ] puts "$name $count $cell" }

Lab 1-5 Exploring Clocks and Clock Properties

1) To find all of the clocks in the design

get_clocks * get_generated_clocks *

2) Create a collection for the clock ref_clk

set myClock_C [ get_clocks ref_clk ]


report_property $myClock_C

4) Now use get_property to query the specific clock properties. Note it returns multiple values, each representing a different analysis view.

get_property $myClock_C waveform; get_property $myClock_C is_generated get_property $myClock_C period get_property $myClock_C clock_network_pins ; # returns all pins in the clock network (big list) get_property $myClock_C sources ;

Lab 1-6 Exploring Designs and Design Properties

Designs actually represent hierarchical modules in the design

1) create a collection of modules

get_designs *

2) Select the top design

set myDesign_C [ get_designs FIR_filter ]


report_property $myDesign_C

4) Use get_property to query specify design property



get_property $myDesign_C is_dont_touch

Lab 1-7 Exploring Libraries and Library Properties

1) To see all of the library names:

get_libs *

2) Select one

set myLib_C [ get_libs slow ]


report_property $myLib_C

4) Use get_property to query specific library properties.

get_property $myLib_C source_file_name get_property $myLib_C source_file_name get_property $myLib_C hierarchical_name

Lab 1-8 Exploring Library Cells and Library Cell Properties

1) See all of the library cells. The format is library/cell.

get_lib_cells *

2) Select one. If the cell is in two libraries, it will return two (fast/XOR2X2 and slow/XOR2X2)

get_lib_cells XOR2X2 set myLibCell_C [ get_lib_cells slow/XOR2X2 ]


report_property $myLibCell_C

4) Example library cell queries get_property $myLibCell_C name get_property $myLibCell_C pin_count get_property $myLibCell_C is_macro_cell

Lab 1-9 Exploring Library Pin and Library Pin Properties

1) See all of the library cell pins (this can be a very large list)



get_lib_pins *

2) See all pins of cells that begin with DFF

get_lib_pins DFF*/*

3) Now, select just one

set myLibPin_C [ get_lib_pins slow/DFFXL/CK ]


report_property $myLibPin_C

5) Here are some example library pin queries

get_property $myLibPin_C name get_property $myLibPin_C is_clock get_property $myLibPin_C pin_capacitance_max_rise

6) Find all input pins (that happen to be clocks) on cells beginning with DFF*. We are querying the library, not instances in the design.

filter_collection [ get_lib_pins DFF*/* ] {direction == in} foreach_in_collection pin_C [filter_collection [ get_lib_pins DFF*/* ] {direction == in && is_clock == true}] { set name [ get_property $pin_C hierarchical_name ] set clock [ get_property $pin_C is_clock ] puts "$name clock = $clock"; }

Lab 1-10 Exploring Library Cell Timing Arcs and their Properties

1) Identify a library cell

set myLibCell_C [ get_lib_cells slow/DFFXL ]

2) Now create a collection of timing arcs for that cell.

set arcs_C [ get_lib_arc -of_object $myLibCell_C ]

3) See what's properties are available. Youll get a list of properties for each timing arc of that cell.

report_property $arcs_C

4) Lets iterate through this cells timing arcs. The from_lib_pin and to_lib_pin properties are actually collections. So you can query property "name" on the pins to find the from/to pins. The arc collection has a property describing the type of arc (setup_rising, clear, rising_edge, etc)



foreach_in_collection arc $arcs_C { set from [ get_property [ get_property $arc from_lib_pin ] name ] set to [ get_property [ get_property $arc to_lib_pin ] name ] set type [get_property $arc timing_type ] puts "type: $type $from --> $to "; }

5) This is not going to report timing values because we're looking at the library cell and not a particular instance.

Lab 1-11 Exploring Nets and Net Properties

1) Find top level nets that match the pattern n_*:

get_net n_*

2) Now, search the design hierarchy for nets that match n_*

get_net -hierarchical n_*

3) Find all nets in the instance AO1

get_net AO1/*

4) Find a net connected to a particular pin:

get_net -of_objects [get_pins g4/Y]

5) Select a single net:

set myNet_C [ get_net n_2 ]

6) Examine the available properties:

report_property $myNet_C

7) Here are some example net properties:

get_property $myNet_C name get_property $myNet_C has_detailed_parasitics get_property $myNet_C is_dont_touch get_property $myNet_C driver_pins get_property $driver_C hierarchical_name get_property $driver_C slew_max_rise view VIEW1 get_property $driver_C slew_max_fall view VIEW2



8) We can search for nets in the design by filtering properties. In this example, find all nets in the design with a set_dont_touch. You can verify this by looking at the SDC file data/base1.sdc

get_nets * -hierarchical -filter "@dont_touch == true"

9) Now search for all netlist with a total capacitance greater that 50fF.

get_nets * -hierarchical -filter "@total_capacitance_max_rise > .15"

10) To find nets that have more than 10 load pins

foreach_in_collection pin_C [ get_nets * ] { set name [ get_property $pin_C hierarchical_name ] set load_C [ get_property $pin_C load_pins ] set fanout [ sizeof_collection $load_C ] if { $fanout > 10 } { puts "$fanout $name" } }

Lab 1-12 Exploring Pins and Pin Properties

1) Find all pins in the design

get_pins *

2) Identify pins on instances inside the module AO1

get_pins -of_objects [get_cells AO1/*]

3) Get the pins of the module

get_pins -of_objects [get_cells AO1]

4) Get the output pins of the module:

get_pins -of_objects [get_cells AO1] -filter "@direction == out"

5) Review the properties of a particular pin:

get_pins g4/Y set myPin_C [ get_pins g4/Y ] report_property $myPin_C

6) Here are some example pin properties:

get_property $myPin_C net_name get_property $myPin_C is_clock get_property $myPin_C arrival_window view VIEW1



7) Find pins with outputs that fanout to more than 10 pins. This doesn't include top level ports

foreach_in_collection pin_C [ get_pins * -filter {direction == out && fanout > 10 } ] { set name [ get_property $pin_C hierarchical_name ] set fanout [ get_property $pin_C fanout ] puts "$fanout $name"; }

Lab 1-13 Exploring Ports and Port Properties

1) Find all top level ports

get_ports *

2) Now, use the -filter option to find all output ports

get_ports * -filter "@direction == out"

3) Get the top port "start" and get query various properties

get_ports start set myPort_C [ get_ports start ]

4) Here are some example port properties:

report_property $myPort_C get_property $myPort_C fanin get_property $myPort_C fanout get_property $myPort_C is_port get_property $myPort_C driving_cell_rise_max

Lab 1-14 Exploring Timing Paths and Timing Path Properties

Finding netlist and physical properties (such as connectivity, capacitance values and fanout) is fine. But the real power of collections becomes evident when you query values in a timing report. The command report_timing has the collection argument which returns the all data in the form of a collection.

1) Here the base report_timing command well be examining:

report_timing -net -path_type full_clock -from AO1/SUM_reg_3_15 -to AO1/SUM_reg_2_15 -clock_from pll_clk -clock_to pll_clk view VIEW1

2) Heres the same report, but returned as a collection:

set paths_C [ report_timing -path_type full_clock -from AO1/SUM_reg_3_15 -to AO1/SUM_reg_2_15 -clock_from pll_clk -clock_to pll_clk view VIEW1 -collection ]



3) Query information shown in the header of the report

report_property $paths_C Much of the information that is found in the header of the textual timing report can be found as properties. But where are the clock and data paths?

4) Before we investigate the clock and data paths, lets review some of the report properties.

get_property $paths_C view_name get_property $paths_C arrival get_property $paths_C required_time get_property $paths_C slack

5) The clock and data paths are collections themselves that can be queried. They are the properties called: launch_clock_path, capture_clock path and timing_points

Lab 1-15 Exploring Timing Points and Timing Point Properties

The data path information is stored as the timing_points property. It is a collection of timing_points which consists of the following properties: arrival time, delta_delay, pin slew and transition type. And you iterate through each timing_point in the collection to query the properties at each point.

1) Here we iterate on each timing point in the path to query properties in the data path

set timingPts_C [get_property $paths_C timing_points] foreach_in_collection timingPt $timingPts_C { set instPin [ get_object_name [ get_property $timingPt pin ] ] set netName [ get_object_name [ get_nets -of_objects $instPin ] ] set arrival [ get_property $timingPt arrival ] set slew [ get_property $timingPt slew ]



set tran [ get_property $timingPt transition_type ] puts "PIN: $instPin NET: $netName ARR: $arrival SLEW: $slew TRAN_TYPE: $tran" }

2) The launch and capture clock properties of the timing path return collections. One of which is a is a collection of timing_points representing the clock paths.

report_property [get_property $paths_C launch_clock_path]

3) Here, we query the arrival times of the launch and capture clocks:

get_property [get_property $paths_C launch_clock_path] arrival get_property [get_property $paths_C capture_clock_path] arrival

4) And like the data path, you can investigate the timing points in the launch/capture clock paths :

set launchPts_C [get_property [get_property $paths_C launch_clock_path] timing_points ] foreach_in_collection timingPt $launchPts_C { set instPin [ get_object_name [ get_property $timingPt pin ] ] set netName [ get_object_name [ get_nets -of_objects $instPin ] ] set arrival [ get_property $timingPt arrival ] set slew [ get_property $timingPt slew ] set tran [ get_property $timingPt transition_type ] puts "PIN: $instPin NET: $netName ARR: $arrival SLEW: $slew TRAN_TYPE: $tran" }

5) To query the capture clock

set capturePts_C [get_property [get_property $paths_C capture_clock_path] timing_points ] foreach_in_collection timingPt $capturePts_C { set instPin [ get_object_name [ get_property $timingPt pin ] ] set netName [ get_object_name [ get_nets -of_objects $instPin ] ] set arrival [ get_property $timingPt arrival ] set slew [ get_property $timingPt slew ] set tran [ get_property $timingPt transition_type ] puts "PIN: $instPin NET: $netName ARR: $arrival SLEW: $slew TRAN_TYPE: $tran" }

Lab 1-16 Exploring Timing Arcs and Timing Arc Properties

You may have noticed that the paths didnt contain any delay information. Delay information can be extracted from the timing graph by iterating through the timing points and using get_arcs to query from one point to the next.



1) This is the timing report well be investigating. Our goals is to report the base and incremental net delays in the data path

report_timing -net -path_type full_clock -from AO1/SUM_reg_3_15 -to AO1/SUM_reg_2_15 -clock_from pll_clk -clock_to pll_clk view VIEW1

2) Now create a collection from the report_timing command.

set path_C [ report_timing -path_type full_clock -from AO1/SUM_reg_3_15 -to AO1/SUM_reg_2_15 -clock_from pll_clk -clock_to pll_clk view VIEW1 -collection ]

3) Grab the data path's timing points from the collection returned by report_timing

set points [ get_property $path_C timing_points ]

4) We need to look at each arc, which is done by querying from one timing point to the next. To do this, well iterate on the timing points defining a current and previous timing point. For the first pass, the first timing point will be both the current and previous points. But the script could be enhanced to filter this out.

set prev_point [index_collection $points 0] foreach_in_collection curr_point $points { set prev_pin_name [get_object_name [get_property $prev_point pin]] set curr_pin_name [get_object_name [get_property $curr_point pin]] # Get timing arc from previous point to current point set arc [get_arcs -from $prev_pin_name -to $curr_pin_name] puts "Arc: $prev_pin_name ---> $curr_pin_name" # Determine if the arc is min/max and rise/fall set RF [get_property $curr_point transition_type] set MM [get_property $path_C path_type] # Build up the property to query set delay_type delay_${MM}_${RF} set si_delay_type delta_delay_${MM}_${RF} # Use the is_cellarc property to determine if the arc is a net or cell arc if {[get_property $arc is_cellarc] == false} {

# Query the full net delay and the incremental net delay set full_net_delay [get_property [get_arcs -from $prev_pin_name -to $curr_pin_name] $delay_type ]



set incr_net_delay [get_property [get_arcs -from $prev_pin_name -to $curr_pin_name] $si_delay_type ] # generate a report puts " Full Net Delay: $full_net_delay Incremental: $incr_net_delay" } # Update previous point to point to the curr_point set prev_point $curr_point }

5) Note, the above did not report the clock paths. That is because they are not part of the timing paths timing point. The same methodology could be used to query the launch and capture clock paths. The clock paths are a collection belonging to the timing paths capture/launch_clock_path properties. So it's basically like querying the data path, but you have to go down one extra level of hierarchy.

Lab 1-17 Exploring Path Group Properties

1) The initial design db does not include path groups. So create one:

group_path -name clk2clk -from [all_registers] -to [all_registers]

2) Now we can query it.

get_path_groups set myPathGroup_C [get_path_groups]

3) What properties are available? There isnt very much.

report_property $myPathGroup_C



Lab 2-1 Application - Some real life examples

1) Lets apply an input delay to all inputs (except a clock)?

set_input_delay .75 -clock [get_clocks {io_clk}] [all_inputs no_clock]

2) To find the clock that drives a particular net

query_objects [get_property [get_property [get_nets ring/n_130] driver_pins] clock_sources]

3) Identifying all integrated clock gating cells in your design.

Puts "" Puts "Instances of Integrated Clock Gating Cells and Their CellType:" Puts "--------------------------------------------------------------" set icgInsts [filter_collection [all_registers] "is_integrated_clock_gating_cell == true"] foreach_in_collection icgInstPtr $icgInsts { set instName [get_object_name $icgInstPtr] set cellName [get_property $icgInstPtr ref_lib_cell_name] Puts "Instance: $instName ($cellName)" } set numOfIcgs [sizeof_collection $icgInsts] Puts "" Puts "Total ICG Instances: $numOfIcgs" Puts ""

4) Select all LVT cells on the critical paths proc selectCriticalLvtInst {targetSlack} { set maxPaths 100000 group_path -name in2reg -from [all_inputs] -to [all_registers] group_path -name reg2reg -from [all_registers] -to [all_registers] group_path -name reg2out -from [all_registers] -to [all_outputs] foreach_in_collection group [get_path_groups] { set groupName [get_object_name $group] puts "Processing path group $groupName ..." set rt [report_timing -path_group $groupName -max_slack $targetSlack -max_paths $maxPaths -collection] if {[sizeof_collection $rt] >= 1} { set pinList [filter_collection [get_property [get_property $rt timing_points] pin] {object_type == pin}] if {[sizeof_collection $pinList] >= 1} { deselectAll foreach_in_collection pin $pinList { set instName [get_object_name [get_cells -of_objects [get_pins $pin]]] set refCell [get_property [get_cells $instName] ref_lib_cell_name]



if {[regexp LVT $refCell]} { selectInst $instName } } } } } }

5) Return a list of module names that are used inside a hierarchical inst # example : getSubModuleList ia # => D C # to get the sub module under the top module (design) specify the top design name # example : getSubModuleList top # ==> D C D A B # the list is purposely not sorted in case user needs to find out the number of instantiations as well. proc getSubModuleList {hInst} { if {$hInst == [dbGet top.name]} { get_property [get_cells -hier -regexp .* -filter "@is_hierarchical==true"] ref_lib_cell_name } else { get_property [get_cells -hier -regexp ${hInst}/.* -filter "@is_hierarchical==true"] ref_lib_cell_name } }

6) List all endpoints with hold violations, i.e. D and SI inputs to flops. set rtc [report_timing -collection -early -max_points 1000000 -max_slack 0] set endpoint_list [list] foreach_in_collection rt $rtc { lappend endpoint_list [get_property [get_property $rt capturing_point] hierarchical_name] }

7) Replace all of the X1 cells in the worst path in the design with X2 cells (this script can be used for HVT-non-HVT swapping)

set collection [report_timing -collection] set timing_points [get_property $collection timing_points] set instNameList {} foreach_in_collection timing_point $timing_points { set pin_name [get_property [get_property $timing_point pin] hierarchical_name] set inst_name [file dirname $pin_name] if {[lsearch $instNameList $inst_name] == -1} { lappend instNameList $inst_name }



} foreach instName $instNameList { set inst [dbGetInstByName $instName] set cellName [dbGet $inst.cell.name] if {[string match *X1 $cellName]} { regsub {X1$} $cellName {X2} newCellName ecoChangeCell -inst $instName -cell $newCellName } }

8) A procedure for creating a custom report_timing report format proc my_report_timing { args } { # Create a collection of timing paths # set rptTimingCmd "report_timing -collection $args" set timingPaths_C [eval $rptTimingCmd] set pathNum 0 # Iterate over the set of paths, and process them one at-a-time foreach_in_collection timingPath_C $timingPaths_C { incr pathNum # Some objects returned by get_property will themselves be collections, so # additional processing is required to, for instance, get the name of a # particular pin or port # This section pulls "bannder/header" information about the path set timingPts_C [get_property $timingPath_C timing_points] set startPoint [query_objects [get_property $timingPath_C launching_point]] set endPoint [query_objects [get_property $timingPath_C capturing_point]] set launchClk [query_objects [get_property $timingPath_C launching_clock]] set captureClk [query_objects [get_property $timingPath_C capturing_clock]] set launchClkEdge [get_property $timingPath_C launching_clock_open_edge_type] set captureClkEdge [get_property $timingPath_C capturing_clock_close_edge_type] puts "\n" puts "Path $pathNum" puts "Startpoint: $startPoint launched by $launchClk $launchClkEdge" puts "Endpoint: $endPoint latched by $captureClk $captureClkEdge" # This section iterates over the pins/ports for a specific path and prints



# out the pin name and the edge of the transition # foreach_in_collection point_C $timingPts_C { set pin [get_property [get_property $point_C pin] hierarchical_name] set pinEdge [get_property $point_C transition_type] puts "$pin \t $pinEdge" } } }

To get the testcase click on downloadPurposeLab 1-1 Loading the DatabaseLab 1-2 Explore the design with the All Star (all_*) commandsLab 1-3 Querying and Manipulating CollectionsLab 1-4 Exploring Instances (cells) and Instance (cell) PropertiesLab 1-5 Exploring Clocks and Clock PropertiesLab 1-6 Exploring Designs and Design PropertiesLab 1-7 Exploring Libraries and Library PropertiesLab 1-8 Exploring Library Cells and Library Cell PropertiesLab 1-9 Exploring Library Pin and Library Pin PropertiesLab 1-10 Exploring Library Cell Timing Arcs and their PropertiesLab 1-11 Exploring Nets and Net PropertiesLab 1-12 Exploring Pins and Pin PropertiesLab 1-13 Exploring Ports and Port PropertiesLab 1-14 Exploring Timing Paths and Timing Path PropertiesLab 1-15 Exploring Timing Points and Timing Point PropertiesLab 1-16 Exploring Timing Arcs and Timing Arc PropertiesLab 1-17 Exploring Path Group Properties

Lab 2-1 Application - Some real life examples

Documents

Collections Labs