Combinational Circuit

7/21/2019 Combinational Circuit

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Digital Electronics

Combinational Circuits

Part 1

Israt Ferdous



Objectives• Arithmetic Circuits

• Adder

• Subtractor • Carry Look Ahead Adder

• BCD Adder

• Multiplier



Combinational Circuit Design

Procedure• Given a problem statement

– Determine the number o! inputs and outputs

– Derive the truth table – Simpli!y the Boolean e"pression !or each output

– #roduce the re$uired circuit



Designing Combinational LogicCircuit• Desi%n a lo%ic circuit that has three inputs& A&B and C& and 'hose

output 'ill be (IG( only 'hen a ma)ority o! the inputs are (IG(*Step+* Set up the truth table

A B C x

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

Step,* -rite the A.D term !or each case 'here the output is +

ABC

ABC

ABC

ABC



Step /* -rite the S0# e"pression !or the output

Step 1* Simpli!y the output e"pression

Step 2 Implement the circuit





Adder Desi%n an Adder !or +3bit numbers4




1. Specification:, inputs 56&78

, outputs 5C&S8




1. Specification:, inputs 56&78

, outputs 5C&S8

2. Formulation:

X Y C S

9 9 9 9

9 + 9 +

+ 9 9 +

+ + + 9




1. Specification: 3. Optimization/Circuit

, inputs 56&78

, outputs 5C&S8

2. Formulation:X Y C S

9 9 9 9

9 + 9 +

+ 9 9 +

+ + + 9



Half Adder :his adder is called a (al! Adder

: !"#$

X Y C S

9 9 9 9

9 + 9 +

+ 9 9 +

+ + + 9



Full Adder A combinational circuit that adds / input bits to

%enerate a Sum bit and a Carry bit





X Y % C S

9 9 9 9 9

9 9 + 9 +

9 + 9 9 +

9 + + + 9

+ 9 9 9 +

+ 9 + + 9

+ + 9 + 9

+ + + + +





X Y % C S

9 9 9 9 9

9 9 + 9 +

9 + 9 9 +

9 + + + 9

+ 9 9 9 +

+ 9 + + 9

+ + 9 + 9

+ + + + +

6

7;

9

+

99 9+ ++ +90 1 0 1

1 0 1 0

6

7;

9

+

99 9+ ++ +90 0 1 0

0 1 1 1

Sum

Carry

S < 6=7=; > 6=7;=

> 67=;= >67;

< 6 ⊕ 7 ⊕ ;

C < 67 > 7; > 6;



Binary Adder!ormal Design"• Full Adder

x

y

z

S

C

x

y

z

S

C

S = xy'z' + x'yz' + x'y'z + xyz = x y z

C = xy + xz + yz



Full Adder # $ Half Adders

&anipulatin' t"e ()uation*:

S < 6 ⊕ 7 ⊕ ;

C < 67 > 6; > 7;





S < 5 6 ⊕ 7 8 ⊕ ;

C < 67 > 6; > 7;

< 67 > 67; > 67=; > 6=7; > 67;

< 675 + > ;8 > ;567= > 6=78

< 67 > ;56 ⊕ 7 8





S < 5 6 ⊕ 7 8 ⊕ ;

C < 67 > 6; > 7; < 67 > ;56 ⊕ 7 8

Src Mano=s Book

:hink o!

; as acarry in



Bigger Adders

• (o' to build an adder !or n3bit numbers4

• ?"ample 13Bit Adder

• Inputs 4• 0utputs 4

• -hat is the si@e o! the truth table4

• (o' many !unctions to optimi@e4



Bigger Adders

• (o' to build an adder !or n3bit numbers4

• ?"ample 13Bit Adder

• Inputs 4 inputs• 0utputs 4 2 outputs

• -hat is the si@e o! the truth table4 2+, ro's

• (o' many !unctions to optimi@e4 2 !unctions



Binary Parallel Adder

:o add n3bit numbers

• se n Full3Adders in parallel

•:he carries propa%ates as in addition by hand

• se ; in the circuit as a Cin

+ 9 9 9

9 + 9 + 9 + + 9

+ 9 + +



Binary Parallel Adder



•:he carries propa%ates as in addition by hand

:his adder is called ripple carry adder

Src Mano=s Book



%i&&le Adder Delay

• Assume %ate delay < :

• : to compute the last

carry

• :otal delay < > + < :• + delay !orm !irst hal!

adder

• Delay < 5,n>+8:

Src Course CD



'ubtraction $(s Com&lement"

(o' to build a subtractor usin% ,=s

complement4



'ubtraction $(s Com&lement"

(o' to build a subtractor usin% ,=s

complement4

1

S = A + ( -B)Src Mano=s Book



Adder)'ubtractor

(o' to build a circuit that per!orms both

addition and subtraction4



Adder)'ubtractor

Src Mano=s Book

sin% !ull adders and 60E 'e can build an AdderSubtractor

9 Add

+ subtract



Binary Parallel Adder Again"



• :he carries propa%ates as in addition by hand

:his adder is called ripple carry adder

Src Mano=s Book



%i&&le Adder Delay

• Assume %ate delay < :

• : to compute the last

carry

• :otal delay < > + < :• + delay !orm !irst hal!

adder

• Delay < 5,n>+8:

Src Course CD

+o, to impro-e$



BCD Adder

BCD di%its are valid !or decimal numbers 93

Addition o! t'o BCD numbers 'ill %enerate an output&that may be %reater than +99+ 58*

In such cases& the BCD number 9++9 is added to theresult as a correction step

-hen addin% t'o BCD numbers& the ma"imum resultthat can be obtained is > < +

I! 'e include a carry in bit& then the ma"imum result that canbe obtained is + 5+99++8

Both numbers + and + are invalid BCD di%its* :here!ore& a needs to be added to brin% them to correct BCD !ormat*



Adding t*o BCD numbers +

,rut- ,able:he truth table de!ines the

outputs 'hen t'o BCD

numbers are added

:he !unction F is + !or all invalid

BCD di%its& and there!ore actsas a BCD veri!ier

:o minimi@e the e"pression& a 2

variable can be used& or

3 A 1 variable k map can be

used to minimi@e the !unction F&and

3:he result is 0Eed 'ith C0&

since the !unction is al'ays +

'henever C0 is +

H From course CD




.inimi/ation

;/;,

99

9+

++

+9

99 9+ ++ +9

0 0 0 0

0 0 0 0

1 1 1 1

0 0 1 1

;+;9F

F < ;/;, > ;/;+ > C0




Circuit B3 B2B1B0 A3A2A1A0

Carry In

%3 %2 %1 %0

9

S3 S2 S1 S0

Cout 13bit Binary

Adder

13bit Binary

Adder

CorrectionStep



Adding t*o BCD numbers 0

'te&s

:he t'o 13bit BCD inputs are added by the 13bit binaryadder to produce the sum ;/;,;+;9 and a Carry 0ut5Cout8

-hen Cout <9& the correction step e"ecutes by addin% 9999to ;/;,;+;9& and the output remains the same

-hen Cout <+& the correction step adds 9++9 to ;/;,;+;9to %enerate the corrected output

:he output carry is the same as Cout

I! additional decimal di%its need to be added& the BCD addercan be cascaded& 'ith the output carry o! one phaseconnected to the input o! the other



Parallel Adders

• Eeduce the carry propa%ation delay

– ?mploy !aster %ates

– Look3ahead carry 5more comple" mechanism& yet !aster8

– Carry propa%ate P i = Ai ⊕Bi

– Carry %enerate Gi = Ai Bi

– Sum Si < P i ⊕C i

– Carry C i+1 = Gi +P i C i

– C 9 = Input carry

– C + = G9+P 9C 9

– C , = G++P +C + = G++P +5G9+P 9C 98 = G++P +G9+P +P 9C 9

– C / = G,+P ,C , = G,+P ,G++P ,P +G9+ P ,P +P 9C 9



Carry Loo0a-ead Adder 1)$"

• Lo%ic dia%ram

Fig. 4.11 Logic Diagram of Carry Look-ahead Generator



Carry Loo0a-ead Adder $)$"

• 13bit carry3look

ahead adder –

#ropa%ation delayo! C /& C , and C +

are e$ual*

Fig. 4.12 4-Bit Adder with Carry Look-ahead



E2ercise

From the !i%& an analo%3to3di%ital converter is monitorin% the dc

volta%e o! a +, stora%e battery on an orbitin% spaceship* :he

converter=s output is a !our3bit binary number& ABCD&

correspondin% to the battery volta%e in steps o! +& 'ith A as

the MSB* :he converter=s binary outputs are !ed to a lo%iccircuit that is to produce a (IG( output as lon% as the binary

value is %reater than 59++98,<58+9J that is the battery volta%e is

%reater than * Desi%n the lo%ic circuit*



E2ercise



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Combinational Circuit